From f502c8e13b2381ad32379d15f36f2631e442db46 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Tue, 7 Jun 2022 14:03:27 +0200
Subject: [PATCH 01/44] exit simulation on loop to self instruction

---
 examples/SW/riscv/cmake/pulpino_tumeda/syscalls.c |  1 -
 src/CPUCore.cpp                                   | 14 ++++++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/examples/SW/riscv/cmake/pulpino_tumeda/syscalls.c b/examples/SW/riscv/cmake/pulpino_tumeda/syscalls.c
index 423b9e4a0c..5c5f7e75f2 100644
--- a/examples/SW/riscv/cmake/pulpino_tumeda/syscalls.c
+++ b/examples/SW/riscv/cmake/pulpino_tumeda/syscalls.c
@@ -115,7 +115,6 @@ void _exit_(int exit_status)
 #ifdef DEBUG_SYSTEM
     printf_fromisr("exit called with code: %i\n", exit_status);
 #endif
-    asm("ebreak");
     while (1)
         ;
 }
diff --git a/src/CPUCore.cpp b/src/CPUCore.cpp
index 1aad4f0280..64bbd6a424 100644
--- a/src/CPUCore.cpp
+++ b/src/CPUCore.cpp
@@ -727,6 +727,11 @@ etiss::int32 CPUCore::execute(ETISS_System &_system)
                 // cpu->instructionPointer)){
                 // Transalte virtual address to physical address if MMU is enabled
                 uint64_t pma = cpu_->instructionPointer;
+
+                // remember pc and cpu time to check for loop to self instructions
+                uint64_t old_pc = cpu_->instructionPointer;
+                uint64_t old_time = cpu_->cpuTime_ps;
+
                 if (mmu_enabled_)
                 {
                     if (mmu_->cache_flush_pending)
@@ -785,6 +790,15 @@ etiss::int32 CPUCore::execute(ETISS_System &_system)
                     // a variable of the plugin
                     exception = (*(blptr->execBlock))(cpu_, system, plugins_handle_);
 
+
+                    // exit simulator when a loop to self instruction is encountered
+                    if (!exception &&
+                            old_time + cpu_->cpuCycleTime_ps == cpu_->cpuTime_ps &&
+                            old_pc == cpu_->instructionPointer)
+                    {
+                        exception = RETURNCODE::CPUFINISHED;
+                    }
+
 #if ETISS_CPUCORE_DBG_APPROXIMATE_INSTRUCTION_COUNTER
                     instrcounter +=
                         blptr->end - oldinstrptr; // TESTING ///TODO handle early exception exit? ///BUG:

From 9308a8d10e1028ad4447d8cc228956b7c38b8527 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Tue, 7 Jun 2022 14:04:38 +0200
Subject: [PATCH 02/44] add exception members to cpu struct

---
 include_c/etiss/jit/CPU.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include_c/etiss/jit/CPU.h b/include_c/etiss/jit/CPU.h
index 6fa4f17691..7752014bc7 100644
--- a/include_c/etiss/jit/CPU.h
+++ b/include_c/etiss/jit/CPU.h
@@ -105,6 +105,9 @@ extern "C"
         void *_etiss_private_handle_; ///< private helper handle for plugins
 
         etiss_uint32 mode; ///< instruction set mode of the processor
+
+        etiss_uint32 exception; // currently active exception of the processor
+        etiss_uint32 return_pending; // flags whether a return from the JIT code is needed
     };
 #pragma pack(pop)
 

From e62742759fac2c3a3fe488ac1cc97f4c75573205 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Tue, 7 Jun 2022 14:58:49 +0200
Subject: [PATCH 03/44] begin coredsl exception stuff

---
 ArchImpl/RV32IMACFD/RV32IMACFD.h              |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp        |  5 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         | 57 ++++++++++---
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp | 56 ++++++-------
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     | 18 ++--
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp | 10 +--
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     | 18 ++--
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp | 10 +--
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 66 +++++++--------
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 82 +++++++++----------
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |  6 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    | 16 ++--
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    |  8 +-
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    | 10 +--
 14 files changed, 199 insertions(+), 165 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD.h b/ArchImpl/RV32IMACFD/RV32IMACFD.h
index 3cad50c017..c4c8c11cfb 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 01 Mar 2022 00:20:25 +0100.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the registers for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
index 0a6e512baa..678fadc6ac 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 01 Mar 2022 00:20:25 +0100.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
@@ -207,7 +207,8 @@ void RV32IMACFDArch::initCodeBlock(etiss::CodeBlock & cb) const
 {
 	cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFD.h\"\n");
 	cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFDFuncs.h\"\n");
-	cb.functionglobalCode().insert("etiss_uint32 exception = 0;\n");
+	cb.functionglobalCode().insert("cpu->exception = 0;\n");
+	cb.functionglobalCode().insert("cpu->return_pending = 0;\n");
 }
 
 etiss::plugin::gdb::GDBCore & RV32IMACFDArch::getGDBCore()
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index a8cffc66a6..1ffd0d0447 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 09 May 2022 21:14:16 +0200.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -15,10 +15,41 @@
 #endif
 
 
-
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void raise(etiss_int32 irq, etiss_int32 mcause);
-#endif
+static inline etiss_int32 raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
+{
+if (irq != 0U) {
+return -9U;
+} else {
+if (mcause == 0U || mcause == 1U) {
+return -7U;
+}
+if (mcause == 2U) {
+return -11U;
+}
+if (mcause == 3U) {
+return 2147483648U;
+}
+if (mcause == 4U || mcause == 5U) {
+return -5U;
+}
+if (mcause == 6U || mcause == 7U) {
+return -6U;
+}
+if (mcause == 8U || mcause == 9U || mcause == 10U || mcause == 11U) {
+return -17U;
+}
+if (mcause == 12U || mcause == 20U) {
+return -13U;
+}
+if (mcause == 13U || mcause == 21U) {
+return -14U;
+}
+if (mcause == 15U || mcause == 23U) {
+return -15U;
+}
+return -11U;
+}
+}
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline void leave(etiss_int32 priv_lvl);
@@ -154,17 +185,23 @@ static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system,
 {
 if (csr == 1U) {
 *((RV32IMACFD*)cpu)->CSR[3] = (*((RV32IMACFD*)cpu)->CSR[3U] & 224U) | (val & 31U);
-} else {
-if (csr == 2U) {
+} else if (csr == 2U) {
 *((RV32IMACFD*)cpu)->CSR[3] = ((val & 7U) << 5U) | (*((RV32IMACFD*)cpu)->CSR[3U] & 31U);
-} else {
-if (csr == 3U) {
+} else if (csr == 3U) {
 *((RV32IMACFD*)cpu)->CSR[3] = val & 255U;
 } else {
 *((RV32IMACFD*)cpu)->CSR[csr] = val;
 }
 }
+#endif
+static inline etiss_int32 translate_exc_code(etiss_int32 cause)
+{
+if (cause == -5U) {
+return 5U;
 }
+if (cause == -6U) {
+return 7U;
+}
+return 2U;
 }
-#endif
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index b53b7e3496..2bc6f7ef62 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 09 May 2022 22:10:34 +0200.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -55,13 +55,13 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n";
 }
 partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -141,16 +141,16 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -230,16 +230,16 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -319,16 +319,16 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -408,16 +408,16 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -497,16 +497,16 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -586,16 +586,16 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -675,16 +675,16 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 > *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -764,16 +764,16 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index 8a625e65eb..7fda4cb334 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 03 Mar 2022 12:13:52 +0100.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -50,10 +50,10 @@ uimm += R_uimm_3.read(ba) << 3;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = res;\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -123,9 +123,9 @@ uimm += R_uimm_3.read(ba) << 3;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -194,10 +194,10 @@ uimm += R_uimm_5.read(ba) << 5;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -263,9 +263,9 @@ uimm += R_uimm_3.read(ba) << 3;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index 0b9a4c2882..d23af8edc7 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 09 May 2022 21:45:21 +0200.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -48,10 +48,10 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -119,9 +119,9 @@ imm += R_imm_5.read(ba) << 5;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 363ec9b47c..c834057239 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 03 Mar 2022 21:04:49 +0100.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -52,10 +52,10 @@ uimm += R_uimm_3.read(ba) << 3;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = -4294967296UL | res;\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -129,9 +129,9 @@ uimm += R_uimm_3.read(ba) << 3;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -202,10 +202,10 @@ uimm += R_uimm_5.read(ba) << 5;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | res;\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -271,9 +271,9 @@ uimm += R_uimm_2.read(ba) << 2;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 419241809c..18c4c917b7 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 09 May 2022 21:04:41 +0200.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -48,10 +48,10 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -119,9 +119,9 @@ imm += R_imm_5.read(ba) << 5;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index b9f4c33c8f..0001c71c5f 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 09 May 2022 22:10:34 +0200.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -52,9 +52,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 if (imm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(imm) + ";\n";
 } else {
-partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -128,9 +128,9 @@ uimm += R_uimm_3.read(ba) << 3;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_int32)(mem_val_0);\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -205,9 +205,9 @@ uimm += R_uimm_3.read(ba) << 3;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -405,7 +405,7 @@ imm += R_imm_11.read(ba) << 11;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(1U) + "] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[1U], 32);
@@ -541,12 +541,12 @@ imm += R_imm_17.read(ba) << 17;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (imm == 0U) {
-partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
 }
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -614,9 +614,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 if (nzimm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
 } else {
-partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -677,8 +677,8 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -793,10 +793,6 @@ rs1 += R_rs1_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (shamt) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> " + std::to_string(shamt) + ";\n";
-} else {
-if (0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> 64U;\n";
-}
 }
 // -----------------------------------------------------------------------------
 
@@ -1171,7 +1167,7 @@ imm += R_imm_11.read(ba) << 11;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1250,7 +1246,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] == 0U) {\n";
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->instructionPointer != " + std::to_string(ic.current_address_ + 2) + ") return exception;\n";
+partInit.code() += "if (cpu->instructionPointer != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -1327,7 +1323,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] != 0U) {\n";
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->instructionPointer != " + std::to_string(ic.current_address_ + 2) + ") return exception;\n";
+partInit.code() += "if (cpu->instructionPointer != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -1460,14 +1456,14 @@ uimm += R_uimm_5.read(ba) << 5;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_int32 res = mem_val_0;\n";
 if (rd % 32U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 } else {
-partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -1591,9 +1587,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 if (rs1) {
 partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2U;\n";
 } else {
-partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
-partInit.code() += "return exception;\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1642,8 +1638,8 @@ static InstructionDefinition __reserved_cmv_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1756,7 +1752,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(1U) + "] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->instructionPointer = new_pc & -2U;\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1806,8 +1802,8 @@ static InstructionDefinition cebreak_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "exception = ETISS_RETURNCODE_CPUFINISHED;\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1862,9 +1858,9 @@ uimm += R_uimm_2.read(ba) << 2;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -1919,8 +1915,8 @@ static InstructionDefinition dii_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index de8acc1d26..1a07e52db1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 09 May 2022 21:04:41 +0200.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -170,14 +170,14 @@ imm += R_imm_20.read(ba) << 20;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if (imm % 2U) {
-partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 }
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
 }
-partInit.code() += "return exception;\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -246,7 +246,7 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2U;\n";
 partInit.code() += "if (new_pc % 2U) {\n";
-partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
 if ((rd % 32U) != 0U) {
@@ -254,7 +254,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = "
 }
 partInit.code() += "cpu->instructionPointer = new_pc & -2U;\n";
 partInit.code() += "}\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -327,12 +327,12 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n";
+partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -411,12 +411,12 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n";
+partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -495,12 +495,12 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
 if (imm % 2U) {
-partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n";
+partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -579,12 +579,12 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
 if (imm % 2U) {
-partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n";
+partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -663,12 +663,12 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n";
+partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -747,12 +747,12 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n";
+partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -825,12 +825,12 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
 partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -897,12 +897,12 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
 partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -969,12 +969,12 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1041,12 +1041,12 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
 partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
 }
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1113,12 +1113,12 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
 partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
 }
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1187,9 +1187,9 @@ imm += R_imm_5.read(ba) << 5;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1260,9 +1260,9 @@ imm += R_imm_5.read(ba) << 5;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1333,9 +1333,9 @@ imm += R_imm_5.read(ba) << 5;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
 
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2751,8 +2751,8 @@ static InstructionDefinition ecall_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "exception = ETISS_RETURNCODE_SYSCALL;\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -2797,8 +2797,8 @@ static InstructionDefinition ebreak_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "exception = ETISS_RETURNCODE_CPUFINISHED;\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -2843,8 +2843,8 @@ static InstructionDefinition wfi_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "exception = ETISS_RETURNCODE_CPUFINISHED;\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "cpu->exception = ETISS_RETURNCODE_CPUFINISHED;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -2890,13 +2890,13 @@ static InstructionDefinition dret_ (
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (((RV32IMACFD*)cpu)->PRIV < 4U) {\n";
-partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
 partInit.code() += "cpu->instructionPointer = ((RV32IMACFD*)cpu)->DPC;\n";
 partInit.code() += "((RV32IMACFD*)cpu)->PRIV = (((RV32IMACFD*)cpu)->PRIV & 3U) & 0x7;\n";
 partInit.code() += "}\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index 299183b2fa..0f6dbbb74c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 01 Mar 2022 12:43:46 +0100.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
@@ -45,10 +45,10 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//FENCE_I\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
+partInit.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(1) + "] = " + std::to_string(imm) + ";\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index 5da43a3bca..6936cf3c29 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 09 May 2022 21:04:41 +0200.
+ * Generated on Wed, 25 May 2022 14:13:44 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
@@ -49,10 +49,10 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
 } else {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
 }
 // -----------------------------------------------------------------------------
 
@@ -121,7 +121,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if (rs1 != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | xrs1);";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | xrs1);\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
@@ -193,7 +193,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if (rs1 != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & ~(xrs1));";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & ~(xrs1));\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
@@ -263,7 +263,7 @@ csr += R_csr_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", " + std::to_string((etiss_uint32)(zimm)) + ");";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", " + std::to_string((etiss_uint32)(zimm)) + ");\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
 }
@@ -332,7 +332,7 @@ csr += R_csr_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 if (zimm != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | " + std::to_string((etiss_uint32)(zimm)) + ");";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | " + std::to_string((etiss_uint32)(zimm)) + ");\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
@@ -402,7 +402,7 @@ csr += R_csr_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 if (zimm != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + ");";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + ");\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 32dfa2769b..3cfc826f31 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 03 Mar 2022 12:13:52 +0100.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
@@ -42,7 +42,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] = *((RV
 partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(65U) + "];\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "];\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "];\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -93,7 +93,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((
 partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(321U) + "];\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "];\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "];\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -144,7 +144,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((
 partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(833U) + "];\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "];\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "];\n";
-partInit.code() += "return exception;\n";
+partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 7bcc8f67d3..edac7aaf21 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 09 May 2022 21:04:41 +0200.
+ * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -51,13 +51,13 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";
 if (rd) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -134,14 +134,14 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) {\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 
 partInit.code() += "}\n";
 if (rd) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
 }
 partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1U;\n";
-partInit.code() += "if (exception) return exception;\n";
+partInit.code() += "if (cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);

From 798fb36ffe6ea43644aba50e841f7a55fa11aa6e Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 1 Jul 2022 00:12:59 +0200
Subject: [PATCH 04/44] initial coredsl exceptions

---
 ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp        |  3 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         | 27 ++++++++----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp | 38 ++++++++++++-----
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     | 14 ++++---
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp |  8 ++--
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     | 14 ++++---
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp |  8 ++--
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 24 ++++++-----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 42 +++++++++++--------
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |  8 ++--
 10 files changed, 122 insertions(+), 64 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
index 678fadc6ac..3b5de6f014 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
@@ -209,6 +209,7 @@ void RV32IMACFDArch::initCodeBlock(etiss::CodeBlock & cb) const
 	cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFDFuncs.h\"\n");
 	cb.functionglobalCode().insert("cpu->exception = 0;\n");
 	cb.functionglobalCode().insert("cpu->return_pending = 0;\n");
+	cb.functionglobalCode().insert("etiss_uint32 mem_ret_code = 0;\n");
 }
 
 etiss::plugin::gdb::GDBCore & RV32IMACFDArch::getGDBCore()
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index dd6583f77a..502e7f51d4 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Thu, 30 Jun 2022 19:53:54 +0200.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -15,8 +15,11 @@
 #endif
 
 
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_int32 raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
 {
+cpu->return_pending = 1;
 if (irq != 0U) {
 return -9U;
 } else {
@@ -50,6 +53,7 @@ return -15U;
 return -11U;
 }
 }
+#endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline void leave(etiss_int32 priv_lvl);
@@ -224,14 +228,23 @@ if (csr == 1U) {
 }
 }
 #endif
-static inline etiss_int32 translate_exc_code(etiss_int32 cause)
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
 {
+etiss_int32 code = 0U;
 if (cause == -5U) {
-return 5U;
-}
-if (cause == -6U) {
-return 7U;
+code = 5U;
+} else if (cause == -14U) {
+code = 13U;
+} else if (cause == -6U) {
+code = 7U;
+} else if (cause == -15U) {
+code = 15U;
+} else {
+code = 2U;
 }
-return 2U;
+cpu->exception = raise(cpu, system, plugin_pointers, 0U, code);
 }
 #endif
+#endif
\ No newline at end of file
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index 2bc6f7ef62..75911a6f21 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -56,12 +56,14 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n";
 }
 partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -142,6 +144,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
@@ -149,8 +152,9 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 partInit.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -231,6 +235,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
@@ -238,8 +243,9 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -320,6 +326,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
@@ -327,8 +334,9 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 partInit.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -409,6 +417,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
@@ -416,8 +425,9 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 partInit.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -498,6 +508,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
@@ -505,8 +516,9 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -587,6 +599,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
@@ -594,8 +607,9 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -676,6 +690,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n";
@@ -683,8 +698,9 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e
 partInit.code() += "etiss_uint32 res2 = (res1 > *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -765,6 +781,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n";
@@ -772,8 +789,9 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e
 partInit.code() += "etiss_uint32 res2 = (res1 < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index 7fda4cb334..c63dc592d0 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -51,9 +51,10 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = res;\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -124,8 +125,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -195,9 +197,10 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -264,8 +267,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index d23af8edc7..b4ee27350c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -49,9 +49,10 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -120,8 +121,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index c834057239..2dc785ae2c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -53,9 +53,10 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = -4294967296UL | res;\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -130,8 +131,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -203,9 +205,10 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | res;\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -272,8 +275,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 18c4c917b7..f6df9d6425 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -49,9 +49,10 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -120,8 +121,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index 0001c71c5f..2fe8922ec6 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -54,7 +54,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *(
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -129,8 +129,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_int32)(mem_val_0);\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -206,8 +207,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -546,7 +548,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U)
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
 }
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -616,7 +618,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] = *((RV32
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -678,7 +680,7 @@ rd += R_rd_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1457,13 +1459,14 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res = mem_val_0;\n";
 if (rd % 32U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -1639,7 +1642,7 @@ static InstructionDefinition __reserved_cmv_ (
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1859,8 +1862,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 1a07e52db1..82d1277a39 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -332,7 +332,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -416,7 +416,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -500,7 +500,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -584,7 +584,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -668,7 +668,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -752,7 +752,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -826,11 +826,12 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -898,11 +899,12 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -970,11 +972,12 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1042,11 +1045,12 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
 }
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1114,11 +1118,12 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
 }
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1188,8 +1193,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1261,8 +1267,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1334,8 +1341,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2844,7 +2852,7 @@ static InstructionDefinition wfi_ (
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "cpu->exception = ETISS_RETURNCODE_CPUFINISHED;\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -2896,7 +2904,7 @@ partInit.code() += " else {\n";
 partInit.code() += "cpu->instructionPointer = ((RV32IMACFD*)cpu)->DPC;\n";
 partInit.code() += "((RV32IMACFD*)cpu)->PRIV = (((RV32IMACFD*)cpu)->PRIV & 3U) & 0x7;\n";
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index edac7aaf21..3a1e7679d0 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -52,12 +52,13 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";
 if (rd) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -135,13 +136,14 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) {\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 
 partInit.code() += "}\n";
 if (rd) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
 }
 partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1U;\n";
-partInit.code() += "if (cpu->exception) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);

From a2e31cab2f958ca5e52a12ffc8da818d9ab20afc Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Tue, 12 Jul 2022 09:50:35 +0200
Subject: [PATCH 05/44] new arch files

---
 ArchImpl/RV32IMACFD/CMakeLists.txt            |  4 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         | 60 ++++++++--------
 .../RV32IMACFD/RV32IMACFD_RISCVBaseInstr.cpp  | 15 ----
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     |  6 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp | 36 +++++-----
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     | 10 +--
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp | 70 +++++++++----------
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 18 ++---
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp |  6 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp | 10 +--
 ArchImpl/RV32IMACFD/RV32IMACFD_ZicsrInstr.cpp | 15 ----
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    | 36 +++++-----
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |  4 +-
 13 files changed, 129 insertions(+), 161 deletions(-)
 delete mode 100644 ArchImpl/RV32IMACFD/RV32IMACFD_RISCVBaseInstr.cpp
 delete mode 100644 ArchImpl/RV32IMACFD/RV32IMACFD_ZicsrInstr.cpp

diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index 0938e4628f..3b84fca035 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Wed, 25 May 2022 18:09:21 +0200.
+# Generated on Mon, 11 Jul 2022 15:43:25 +0200.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
@@ -9,11 +9,9 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFDArchLib.cpp
 	RV32IMACFDArchSpecificImp.cpp
 	RV32IMACFDInstr.cpp
-	RV32IMACFD_RISCVBaseInstr.cpp
 	RV32IMACFD_RV32IInstr.cpp
 	RV32IMACFD_RV32ICInstr.cpp
 	RV32IMACFD_RV32MInstr.cpp
-	RV32IMACFD_ZicsrInstr.cpp
 	RV32IMACFD_RV32FInstr.cpp
 	RV32IMACFD_RV32FCInstr.cpp
 	RV32IMACFD_RV32DInstr.cpp
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index 502e7f51d4..b0508630ee 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 30 Jun 2022 19:53:54 +0200.
+ * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -21,36 +21,36 @@ static inline etiss_int32 raise(ETISS_CPU * const cpu, ETISS_System * const syst
 {
 cpu->return_pending = 1;
 if (irq != 0U) {
-return -9U;
+return -9;
 } else {
-if (mcause == 0U || mcause == 1U) {
-return -7U;
+if (mcause == 0 || mcause == 1) {
+return -7;
 }
-if (mcause == 2U) {
-return -11U;
+if (mcause == 2) {
+return -11;
 }
-if (mcause == 3U) {
-return 2147483648U;
+if (mcause == 3) {
+return 2147483648;
 }
-if (mcause == 4U || mcause == 5U) {
-return -5U;
+if (mcause == 4 || mcause == 5) {
+return -5;
 }
-if (mcause == 6U || mcause == 7U) {
-return -6U;
+if (mcause == 6 || mcause == 7) {
+return -6;
 }
-if (mcause == 8U || mcause == 9U || mcause == 10U || mcause == 11U) {
-return -17U;
+if (mcause == 8 || mcause == 9 || mcause == 10 || mcause == 11) {
+return -17;
 }
-if (mcause == 12U || mcause == 20U) {
-return -13U;
+if (mcause == 12 || mcause == 20) {
+return -13;
 }
-if (mcause == 13U || mcause == 21U) {
-return -14U;
+if (mcause == 13 || mcause == 21) {
+return -14;
 }
-if (mcause == 15U || mcause == 23U) {
-return -15U;
+if (mcause == 15 || mcause == 23) {
+return -15;
 }
-return -11U;
+return -11;
 }
 }
 #endif
@@ -233,16 +233,16 @@ if (csr == 1U) {
 static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
 {
 etiss_int32 code = 0U;
-if (cause == -5U) {
-code = 5U;
-} else if (cause == -14U) {
-code = 13U;
-} else if (cause == -6U) {
-code = 7U;
-} else if (cause == -15U) {
-code = 15U;
+if (cause == -5) {
+code = 5;
+} else if (cause == -14) {
+code = 13;
+} else if (cause == -6) {
+code = 7;
+} else if (cause == -15) {
+code = 15;
 } else {
-code = 2U;
+code = 2;
 }
 cpu->exception = raise(cpu, system, plugin_pointers, 0U, code);
 }
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RISCVBaseInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RISCVBaseInstr.cpp
deleted file mode 100644
index e36c0f55a0..0000000000
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RISCVBaseInstr.cpp
+++ /dev/null
@@ -1,15 +0,0 @@
-/**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
- *
- * This file contains the instruction behavior models of the RISCVBase
- * instruction set for the RV32IMACFD core architecture.
- */
-
-#include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
-#include "RV32IMACFDFuncs.h"
-
-using namespace etiss;
-using namespace etiss::instr;
-
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index c63dc592d0..1c55b8c59f 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
+ * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -194,7 +194,7 @@ uimm += R_uimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
@@ -264,7 +264,7 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index b4ee27350c..8ffd27eb90 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
+ * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -198,7 +198,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -276,7 +276,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -354,7 +354,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -432,7 +432,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -507,7 +507,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -579,7 +579,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -651,7 +651,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -723,7 +723,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -792,7 +792,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1050,7 +1050,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 0U);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1116,7 +1116,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 1U);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1180,7 +1180,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL + res;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L + res;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1313,7 +1313,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1383,7 +1383,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1453,7 +1453,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1581,7 +1581,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1651,7 +1651,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 2dc785ae2c..e5caf1b20e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
+ * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -55,7 +55,7 @@ partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = -4294967296UL | res;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = -4294967296L | res;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -202,12 +202,12 @@ uimm += R_uimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | res;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | res;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -272,7 +272,7 @@ uimm += R_uimm_2.read(ba) << 2;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index f6df9d6425..1ffe065d1e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
+ * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -51,7 +51,7 @@ partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -196,9 +196,9 @@ rs3 += R_rs3_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -274,9 +274,9 @@ rs3 += R_rs3_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -355,9 +355,9 @@ partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::t
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n";
 partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -436,9 +436,9 @@ partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::t
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n";
 partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -513,9 +513,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -587,9 +587,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -661,9 +661,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -735,9 +735,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -805,9 +805,9 @@ rs1 += R_rs1_0.read(ba) << 0;
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -873,7 +873,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -939,7 +939,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1005,7 +1005,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1071,9 +1071,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1139,9 +1139,9 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1211,7 +1211,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1282,7 +1282,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1354,7 +1354,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1426,7 +1426,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1498,7 +1498,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1625,7 +1625,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1690,7 +1690,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1811,7 +1811,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]);\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index 2fe8922ec6..5d3153cf29 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
+ * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -50,7 +50,7 @@ imm += R_imm_4.read(ba) << 4;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (imm) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(imm) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + ";\n";
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
@@ -405,7 +405,7 @@ imm += R_imm_11.read(ba) << 11;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(1U) + "] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -614,7 +614,7 @@ nzimm += R_nzimm_9.read(ba) << 9;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (nzimm) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[2U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
@@ -1456,7 +1456,7 @@ uimm += R_uimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
@@ -1588,7 +1588,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (rs1) {
-partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2U;\n";
+partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2;\n";
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
@@ -1753,8 +1753,8 @@ rs1 += R_rs1_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(1U) + "] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->instructionPointer = new_pc & -2U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->instructionPointer = new_pc & -2;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1859,7 +1859,7 @@ uimm += R_uimm_2.read(ba) << 2;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 82d1277a39..ee6ed2bd1e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
+ * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -244,7 +244,7 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2U;\n";
+partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
 partInit.code() += "if (new_pc % 2U) {\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 partInit.code() += "}\n";
@@ -252,7 +252,7 @@ partInit.code() += " else {\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 }
-partInit.code() += "cpu->instructionPointer = new_pc & -2U;\n";
+partInit.code() += "cpu->instructionPointer = new_pc & -2;\n";
 partInit.code() += "}\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index eec12666b1..dc5355c5c9 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 09 May 2022 21:04:41 +0200.
+ * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
@@ -325,7 +325,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 if ((rd % 32U) != 0U) {
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n";
 etiss_uint32 MMIN = 2147483648U;
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1U) {\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(MMIN) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
@@ -333,7 +333,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1;\n";
 partInit.code() += "}\n";
 }
 // -----------------------------------------------------------------------------
@@ -406,7 +406,7 @@ partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1;\n";
 partInit.code() += "}\n";
 }
 // -----------------------------------------------------------------------------
@@ -477,7 +477,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr
 if ((rd % 32U) != 0U) {
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n";
 etiss_uint32 MMIN = 2147483648U;
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1U) {\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = 0U;\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZicsrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZicsrInstr.cpp
deleted file mode 100644
index f81f0e19bb..0000000000
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZicsrInstr.cpp
+++ /dev/null
@@ -1,15 +0,0 @@
-/**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
- *
- * This file contains the instruction behavior models of the Zicsr
- * instruction set for the RV32IMACFD core architecture.
- */
-
-#include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
-#include "RV32IMACFDFuncs.h"
-
-using namespace etiss;
-using namespace etiss::instr;
-
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 3cfc826f31..e2a8299aea 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
@@ -37,11 +37,11 @@ static InstructionDefinition uret_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(3088U) + "] = 0U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] ^ ((*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] & 16U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] & 1U);\n";
-partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(65U) + "];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = 0U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[0U] ^ ((*((RV32IMACFD*)cpu)->CSR[0U] & 16U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[0U] & 1U);\n";
+partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[65U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -87,12 +87,12 @@ static InstructionDefinition sret_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(3088U) + "] = (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] & 256U) >> 8U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] ^ (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] & 256U);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] ^ ((*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] & 32U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] & 2U);\n";
-partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(321U) + "];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[256U] & 256U) >> 8U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[256U] ^ (*((RV32IMACFD*)cpu)->CSR[256U] & 256U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[256U] ^ ((*((RV32IMACFD*)cpu)->CSR[256U] & 32U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[256U] & 2U);\n";
+partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[321U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[256U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[256U];\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -138,12 +138,12 @@ static InstructionDefinition mret_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(3088U) + "] = (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] & 6144U) >> 11U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] ^ (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] & 6144U);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] ^ ((*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] & 128U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] & 8U);\n";
-partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(833U) + "];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[768U] & 6144U) >> 11U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[768U] ^ (*((RV32IMACFD*)cpu)->CSR[768U] & 6144U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[768U] ^ ((*((RV32IMACFD*)cpu)->CSR[768U] & 128U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[768U] & 8U);\n";
+partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[833U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[768U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[768U];\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 3a1e7679d0..c6f86e34db 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
+ * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -142,7 +142,7 @@ partInit.code() += "}\n";
 if (rd) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
 }
-partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1U;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 

From ce46144a6afc13e9d7951a6fefacc5ad7830ee2e Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Mon, 18 Jul 2022 21:51:40 +0200
Subject: [PATCH 06/44] add nextPc member

---
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         |  34 ++--
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp |  20 +--
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     |  10 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp |  54 +++---
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     |  10 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp |  54 +++---
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     |  78 ++++-----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 164 ++++++------------
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp |  18 +-
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |   4 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    |  14 +-
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    |  78 ++++-----
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |   6 +-
 include_c/etiss/jit/CPU.h                     |   2 +
 src/CPUCore.cpp                               |   2 +-
 15 files changed, 250 insertions(+), 298 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index b0508630ee..87a078b9f0 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -186,28 +186,28 @@ static inline etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint32 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
 {
-if (csr == 1U) {
-return *((RV32IMACFD*)cpu)->CSR[3U] & 31U;
+if (csr == 1) {
+return *((RV32IMACFD*)cpu)->CSR[3] & 31U;
 }
-if (csr == 2U) {
-return (*((RV32IMACFD*)cpu)->CSR[3U] >> 5U) & 7U;
+if (csr == 2) {
+return (*((RV32IMACFD*)cpu)->CSR[3] >> 5U) & 7U;
 }
-if (csr == 3072U) {
+if (csr == 3072) {
 return etiss_get_cycles(cpu, system, plugin_pointers);
 }
-if (csr == 3200U) {
+if (csr == 3200) {
 return etiss_get_cycles(cpu, system, plugin_pointers) >> 32U;
 }
-if (csr == 3073U) {
+if (csr == 3073) {
 return etiss_get_time();
 }
-if (csr == 3201U) {
+if (csr == 3201) {
 return etiss_get_time() >> 32U;
 }
-if (csr == 3074U) {
+if (csr == 3074) {
 return etiss_get_instret(cpu, system, plugin_pointers);
 }
-if (csr == 3202U) {
+if (csr == 3202) {
 return etiss_get_instret(cpu, system, plugin_pointers) >> 32U;
 }
 return *((RV32IMACFD*)cpu)->CSR[csr];
@@ -217,12 +217,14 @@ return *((RV32IMACFD*)cpu)->CSR[csr];
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
 {
-if (csr == 1U) {
-*((RV32IMACFD*)cpu)->CSR[3] = (*((RV32IMACFD*)cpu)->CSR[3U] & 224U) | (val & 31U);
-} else if (csr == 2U) {
-*((RV32IMACFD*)cpu)->CSR[3] = ((val & 7U) << 5U) | (*((RV32IMACFD*)cpu)->CSR[3U] & 31U);
-} else if (csr == 3U) {
+if (csr == 1) {
+*((RV32IMACFD*)cpu)->CSR[3] = (*((RV32IMACFD*)cpu)->CSR[3] & 224U) | (val & 31U);
+} else if (csr == 2) {
+*((RV32IMACFD*)cpu)->CSR[3] = ((val & 7U) << 5U) | (*((RV32IMACFD*)cpu)->CSR[3] & 31U);
+} else if (csr == 3) {
 *((RV32IMACFD*)cpu)->CSR[3] = val & 255U;
+} else if (csr == 768) {
+*((RV32IMACFD*)cpu)->CSR[768] = val & 136U;
 } else {
 *((RV32IMACFD*)cpu)->CSR[csr] = val;
 }
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index 75911a6f21..01701153d4 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -51,7 +51,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOSWAPW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
@@ -140,7 +140,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOADDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -231,7 +231,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOXORW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -322,7 +322,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOANDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -413,7 +413,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOORW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -504,7 +504,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMINW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -595,7 +595,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMAXW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -686,7 +686,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMINUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -777,7 +777,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMAXUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index 1c55b8c59f..a50efffde5 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -47,7 +47,7 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
@@ -121,7 +121,7 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
@@ -193,7 +193,7 @@ uimm += R_uimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CFLDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
@@ -263,7 +263,7 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFSDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index 8ffd27eb90..a253327e87 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -45,7 +45,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//FLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
@@ -117,7 +117,7 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//FSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
@@ -194,7 +194,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -272,7 +272,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -350,7 +350,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -428,7 +428,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -503,7 +503,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -575,7 +575,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -647,7 +647,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMUL_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -719,7 +719,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FDIV_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -788,7 +788,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FSQRT_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -854,7 +854,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJ_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 // -----------------------------------------------------------------------------
@@ -918,7 +918,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJN_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 // -----------------------------------------------------------------------------
@@ -982,7 +982,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJX_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) & 9223372036854775808UL);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 // -----------------------------------------------------------------------------
@@ -1046,7 +1046,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMIN_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 0U);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -1112,7 +1112,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMAX_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 1U);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -1178,7 +1178,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L + res;\n";
 // -----------------------------------------------------------------------------
@@ -1242,7 +1242,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 // -----------------------------------------------------------------------------
@@ -1306,7 +1306,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FEQ_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = 0U;\n";
 partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 0U);\n";
 if ((rd % 32U) != 0U) {
@@ -1376,7 +1376,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLT_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = 0U;\n";
 partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 2U);\n";
 if ((rd % 32U) != 0U) {
@@ -1446,7 +1446,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLE_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = 0U;\n";
 partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 1U);\n";
 if ((rd % 32U) != 0U) {
@@ -1513,7 +1513,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCLASS_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
 // -----------------------------------------------------------------------------
 
@@ -1574,7 +1574,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_W_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_int64 res = 0U;\n";
 partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 0U, " + std::to_string(rm) + ");\n";
 if ((rd % 32U) != 0U) {
@@ -1644,7 +1644,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_WU_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = 0U;\n";
 partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 0U, " + std::to_string(rm) + ");\n";
 if ((rd % 32U) != 0U) {
@@ -1714,7 +1714,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 // -----------------------------------------------------------------------------
@@ -1779,7 +1779,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_WU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index e5caf1b20e..51fad71407 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -49,7 +49,7 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -127,7 +127,7 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -201,7 +201,7 @@ uimm += R_uimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CFLWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -271,7 +271,7 @@ uimm += R_uimm_2.read(ba) << 2;
 		partInit.code() = std::string("//CFSWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 1ffe065d1e..63f58e3a45 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -45,7 +45,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//FLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -117,7 +117,7 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//FSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -194,7 +194,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -272,7 +272,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
@@ -350,7 +350,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n";
@@ -431,7 +431,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n";
@@ -509,7 +509,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
@@ -583,7 +583,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
@@ -657,7 +657,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMUL_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
@@ -731,7 +731,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FDIV_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
@@ -802,7 +802,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FSQRT_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
@@ -869,7 +869,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJ_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
@@ -935,7 +935,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJN_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
@@ -1001,7 +1001,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJX_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
@@ -1067,7 +1067,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMIN_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
@@ -1135,7 +1135,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMAX_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
@@ -1203,7 +1203,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_W_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_int32 res = 0U;\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + ");\n";
@@ -1274,7 +1274,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_WU_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + ");\n";
@@ -1345,7 +1345,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FEQ_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
@@ -1417,7 +1417,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLT_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
@@ -1489,7 +1489,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLE_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
@@ -1558,7 +1558,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCLASS_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
 partInit.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
 if ((rd % 32U) != 0U) {
@@ -1623,7 +1623,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 // -----------------------------------------------------------------------------
@@ -1688,7 +1688,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_WU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 // -----------------------------------------------------------------------------
@@ -1750,7 +1750,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FMV_X_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "];\n";
 }
@@ -1810,7 +1810,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FMV_W_X\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]);\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index 5d3153cf29..e3d4372b22 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -48,7 +48,7 @@ imm += R_imm_4.read(ba) << 4;
 		partInit.code() = std::string("//CADDI4SPN\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (imm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + ";\n";
 } else {
@@ -125,7 +125,7 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -203,7 +203,7 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -276,7 +276,7 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//CADDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if ((rs1 % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
@@ -338,7 +338,7 @@ nzimm += R_nzimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CNOP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -404,9 +404,9 @@ imm += R_imm_11.read(ba) << 11;
 		partInit.code() = std::string("//CJAL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -477,7 +477,7 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//CLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
@@ -541,7 +541,7 @@ imm += R_imm_17.read(ba) << 17;
 		partInit.code() = std::string("//CLUI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (imm == 0U) {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
@@ -612,7 +612,7 @@ nzimm += R_nzimm_9.read(ba) << 9;
 		partInit.code() = std::string("//CADDI16SP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (nzimm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[2U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
 } else {
@@ -678,7 +678,7 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//__reserved_clui\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -733,7 +733,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] >> " + std::to_string(shamt) + ";\n";
 // -----------------------------------------------------------------------------
 
@@ -792,7 +792,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (shamt) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> " + std::to_string(shamt) + ";\n";
 }
@@ -855,7 +855,7 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//CANDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 // -----------------------------------------------------------------------------
 
@@ -916,7 +916,7 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CSUB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
 // -----------------------------------------------------------------------------
 
@@ -976,7 +976,7 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CXOR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
 // -----------------------------------------------------------------------------
 
@@ -1036,7 +1036,7 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//COR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
 // -----------------------------------------------------------------------------
 
@@ -1096,7 +1096,7 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CAND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
 // -----------------------------------------------------------------------------
 
@@ -1167,8 +1167,8 @@ imm += R_imm_11.read(ba) << 11;
 		partInit.code() = std::string("//CJ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1244,11 +1244,11 @@ imm += R_imm_8.read(ba) << 8;
 		partInit.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] == 0U) {\n";
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->instructionPointer != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -1321,11 +1321,11 @@ imm += R_imm_8.read(ba) << 8;
 		partInit.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] != 0U) {\n";
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->instructionPointer != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -1390,7 +1390,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (nzuimm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(nzuimm) + ";\n";
 }
@@ -1455,7 +1455,7 @@ uimm += R_uimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CLWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -1528,7 +1528,7 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CMV\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
@@ -1586,9 +1586,9 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CJR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (rs1) {
-partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2;\n";
+partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2;\n";
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
@@ -1640,7 +1640,7 @@ static InstructionDefinition __reserved_cmv_ (
 		partInit.code() = std::string("//__reserved_cmv\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1692,7 +1692,7 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CADD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
@@ -1751,10 +1751,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CJALR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->instructionPointer = new_pc & -2;\n";
+partInit.code() += "cpu->nextPc = new_pc & -2;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1804,7 +1804,7 @@ static InstructionDefinition cebreak_ (
 		partInit.code() = std::string("//CEBREAK\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 3U);\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1858,7 +1858,7 @@ uimm += R_uimm_2.read(ba) << 2;
 		partInit.code() = std::string("//CSWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -1918,7 +1918,7 @@ static InstructionDefinition dii_ (
 		partInit.code() = std::string("//DII\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index ee6ed2bd1e..1de17e0601 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -42,7 +42,7 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//LUI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string((etiss_int32)(imm)) + ";\n";
 }
@@ -102,7 +102,7 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//AUIPC\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
 }
@@ -168,14 +168,14 @@ imm += R_imm_20.read(ba) << 20;
 		partInit.code() = std::string("//JAL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if (imm % 2U) {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 }
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
 }
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -243,7 +243,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//JALR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
 partInit.code() += "if (new_pc % 2U) {\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
@@ -252,7 +252,7 @@ partInit.code() += " else {\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 }
-partInit.code() += "cpu->instructionPointer = new_pc & -2;\n";
+partInit.code() += "cpu->nextPc = new_pc & -2;\n";
 partInit.code() += "}\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -324,15 +324,15 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -408,15 +408,15 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -492,15 +492,15 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
 if (imm % 2U) {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -576,15 +576,15 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
 if (imm % 2U) {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -660,15 +660,15 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -744,15 +744,15 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
-partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -822,7 +822,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
@@ -895,7 +895,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
@@ -968,7 +968,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -1041,7 +1041,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LBU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
@@ -1114,7 +1114,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LHU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
@@ -1189,7 +1189,7 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//SB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
@@ -1263,7 +1263,7 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//SH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
@@ -1337,7 +1337,7 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//SW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -1409,7 +1409,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//ADDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
@@ -1476,7 +1476,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//SLTI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
 }
@@ -1543,7 +1543,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//SLTIU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ")) ? (1U) : (0U);\n";
 }
@@ -1610,7 +1610,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//XORI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
@@ -1677,7 +1677,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//ORI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
@@ -1744,7 +1744,7 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//ANDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
@@ -1811,7 +1811,7 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(shamt) + ";\n";
 }
@@ -1878,7 +1878,7 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> " + std::to_string(shamt) + ";\n";
 }
@@ -1945,7 +1945,7 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> " + std::to_string(shamt) + ";\n";
 }
@@ -2012,7 +2012,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//ADD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
@@ -2080,7 +2080,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SUB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
@@ -2148,7 +2148,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SLL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
 }
@@ -2216,7 +2216,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SLT\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n";
 }
@@ -2284,7 +2284,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SLTU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n";
 }
@@ -2352,7 +2352,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//XOR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
@@ -2420,7 +2420,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SRL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
 }
@@ -2488,7 +2488,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SRA\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
 }
@@ -2556,7 +2556,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//OR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
@@ -2624,7 +2624,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//AND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
@@ -2698,7 +2698,7 @@ fm += R_fm_0.read(ba) << 0;
 		partInit.code() = std::string("//FENCE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(0) + "] = " + std::to_string(pred << 4U | succ) + ";\n";
 // -----------------------------------------------------------------------------
 
@@ -2758,7 +2758,7 @@ static InstructionDefinition ecall_ (
 		partInit.code() = std::string("//ECALL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 11U);\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -2804,7 +2804,7 @@ static InstructionDefinition ebreak_ (
 		partInit.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 3U);\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -2850,7 +2850,7 @@ static InstructionDefinition wfi_ (
 		partInit.code() = std::string("//WFI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "cpu->exception = ETISS_RETURNCODE_CPUFINISHED;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -2873,55 +2873,3 @@ ss << "wfi" << " # " << ba << (" []");
 		return ss.str();
 	}
 );
-
-// DRET ------------------------------------------------------------------------
-static InstructionDefinition dret_ (
-	ISA32_RV32IMACFD,
-	"dret",
-	(uint32_t) 0x7b200073,
-	(uint32_t) 0xffffffff,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
-
-		partInit.code() = std::string("//DRET\n");
-
-// -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "if (((RV32IMACFD*)cpu)->PRIV < 4U) {\n";
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "}\n";
-partInit.code() += " else {\n";
-partInit.code() += "cpu->instructionPointer = ((RV32IMACFD*)cpu)->DPC;\n";
-partInit.code() += "((RV32IMACFD*)cpu)->PRIV = (((RV32IMACFD*)cpu)->PRIV & 3U) & 0x7;\n";
-partInit.code() += "}\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "dret" << " # " << ba << (" []");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index dc5355c5c9..a3f8ede992 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
@@ -45,7 +45,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MUL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
@@ -114,7 +114,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MULH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n";
@@ -183,7 +183,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MULHSU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n";
@@ -252,7 +252,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MULHU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n";
@@ -321,7 +321,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//DIV\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n";
 etiss_uint32 MMIN = 2147483648U;
@@ -400,7 +400,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//DIVU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
@@ -473,7 +473,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//REM\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n";
 etiss_uint32 MMIN = 2147483648U;
@@ -552,7 +552,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//REMU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index 0f6dbbb74c..0d49e2c9c6 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
@@ -46,7 +46,7 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(1) + "] = " + std::to_string(imm) + ";\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index 6936cf3c29..eb766fa976 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 25 May 2022 14:13:44 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
@@ -45,7 +45,7 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
@@ -117,7 +117,7 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRS\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if (rs1 != 0U) {
@@ -189,7 +189,7 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRC\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if (rs1 != 0U) {
@@ -261,7 +261,7 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRWI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", " + std::to_string((etiss_uint32)(zimm)) + ");\n";
 if ((rd % 32U) != 0U) {
@@ -329,7 +329,7 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRSI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 if (zimm != 0U) {
 partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | " + std::to_string((etiss_uint32)(zimm)) + ");\n";
@@ -399,7 +399,7 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRCI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 if (zimm != 0U) {
 partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + ");\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index e2a8299aea..b87430c1f0 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+ * Generated on Mon, 18 Jul 2022 21:37:38 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
@@ -14,11 +14,11 @@ using namespace etiss;
 using namespace etiss::instr;
 
 
-// URET ------------------------------------------------------------------------
-static InstructionDefinition uret_ (
+// MRET ------------------------------------------------------------------------
+static InstructionDefinition mret_ (
 	ISA32_RV32IMACFD,
-	"uret",
-	(uint32_t) 0x200073,
+	"mret",
+	(uint32_t) 0x30200073,
 	(uint32_t) 0xffffffff,
 	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
 	{
@@ -33,15 +33,16 @@ static InstructionDefinition uret_ (
 
 		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//URET\n");
+		partInit.code() = std::string("//MRET\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = 0U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[0U] ^ ((*((RV32IMACFD*)cpu)->CSR[0U] & 16U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[0U] & 1U);\n";
-partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[65U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[768U] & 6144U) >> 11U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[768U] ^ (*((RV32IMACFD*)cpu)->CSR[768U] & 6144U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[768U] ^ ((*((RV32IMACFD*)cpu)->CSR[768U] & 128U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[768U] & 8U);\n";
+partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[768U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[768U];\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -58,17 +59,17 @@ partInit.code() += "return cpu->exception;\n";
 
 		std::stringstream ss;
 // -----------------------------------------------------------------------------
-ss << "uret" << " # " << ba << (" []");
+ss << "mret" << " # " << ba << (" []");
 // -----------------------------------------------------------------------------
 		return ss.str();
 	}
 );
 
-// SRET ------------------------------------------------------------------------
-static InstructionDefinition sret_ (
+// URET ------------------------------------------------------------------------
+static InstructionDefinition uret_ (
 	ISA32_RV32IMACFD,
-	"sret",
-	(uint32_t) 0x10200073,
+	"uret",
+	(uint32_t) 0x200073,
 	(uint32_t) 0xffffffff,
 	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
 	{
@@ -83,16 +84,15 @@ static InstructionDefinition sret_ (
 
 		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRET\n");
+		partInit.code() = std::string("//URET\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[256U] & 256U) >> 8U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[256U] ^ (*((RV32IMACFD*)cpu)->CSR[256U] & 256U);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[256U] ^ ((*((RV32IMACFD*)cpu)->CSR[256U] & 32U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[256U] & 2U);\n";
-partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[321U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[256U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[256U];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = 0U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[0U] ^ ((*((RV32IMACFD*)cpu)->CSR[0U] & 16U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[0U] & 1U);\n";
+partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[65U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -109,17 +109,17 @@ partInit.code() += "return cpu->exception;\n";
 
 		std::stringstream ss;
 // -----------------------------------------------------------------------------
-ss << "sret" << " # " << ba << (" []");
+ss << "uret" << " # " << ba << (" []");
 // -----------------------------------------------------------------------------
 		return ss.str();
 	}
 );
 
-// MRET ------------------------------------------------------------------------
-static InstructionDefinition mret_ (
+// SRET ------------------------------------------------------------------------
+static InstructionDefinition sret_ (
 	ISA32_RV32IMACFD,
-	"mret",
-	(uint32_t) 0x30200073,
+	"sret",
+	(uint32_t) 0x10200073,
 	(uint32_t) 0xffffffff,
 	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
 	{
@@ -134,16 +134,16 @@ static InstructionDefinition mret_ (
 
 		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MRET\n");
+		partInit.code() = std::string("//SRET\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[768U] & 6144U) >> 11U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[768U] ^ (*((RV32IMACFD*)cpu)->CSR[768U] & 6144U);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[768U] ^ ((*((RV32IMACFD*)cpu)->CSR[768U] & 128U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[768U] & 8U);\n";
-partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[833U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[768U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[768U];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[256U] & 256U) >> 8U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[256U] ^ (*((RV32IMACFD*)cpu)->CSR[256U] & 256U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[256U] ^ ((*((RV32IMACFD*)cpu)->CSR[256U] & 32U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[256U] & 2U);\n";
+partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[256U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[256U];\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -160,7 +160,7 @@ partInit.code() += "return cpu->exception;\n";
 
 		std::stringstream ss;
 // -----------------------------------------------------------------------------
-ss << "mret" << " # " << ba << (" []");
+ss << "sret" << " # " << ba << (" []");
 // -----------------------------------------------------------------------------
 		return ss.str();
 	}
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index c6f86e34db..7a805fa5d1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+ * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -48,7 +48,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//LRW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
@@ -131,7 +131,7 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//SCW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) {\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
diff --git a/include_c/etiss/jit/CPU.h b/include_c/etiss/jit/CPU.h
index 7752014bc7..7572a99aa8 100644
--- a/include_c/etiss/jit/CPU.h
+++ b/include_c/etiss/jit/CPU.h
@@ -92,6 +92,8 @@ extern "C"
             instructionPointer; ///< pointer to next instruction. NOTE: not neccessarily the instruction address (e.g
                                 ///< instruction minimal size: 4; instruction pointer: 2  -> instruction address: 2*4)
 
+        etiss_uint64 nextPc;
+
         etiss_uint64 cpuTime_ps; ///< simulation time of cpu
 
         etiss_uint64 resourceUsages[ETISS_MAX_RESOURCES]; ///<how many cycles each resource is used
diff --git a/src/CPUCore.cpp b/src/CPUCore.cpp
index 64bbd6a424..3d86f00199 100644
--- a/src/CPUCore.cpp
+++ b/src/CPUCore.cpp
@@ -789,7 +789,7 @@ etiss::int32 CPUCore::execute(ETISS_System &_system)
                     // In the generated code these plugin handles are named "plugin_pointers" and can be used to access
                     // a variable of the plugin
                     exception = (*(blptr->execBlock))(cpu_, system, plugins_handle_);
-
+                    cpu_->instructionPointer = cpu_->nextPc;
 
                     // exit simulator when a loop to self instruction is encountered
                     if (!exception &&

From 2494c3f6dea6ec5a584477cd7091f927b4ddeb5d Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Wed, 20 Jul 2022 14:00:47 +0200
Subject: [PATCH 07/44] flush printinstruction

---
 src/IntegratedLibrary/PrintInstruction.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/IntegratedLibrary/PrintInstruction.cpp b/src/IntegratedLibrary/PrintInstruction.cpp
index b05b295de2..1e22ad61ff 100644
--- a/src/IntegratedLibrary/PrintInstruction.cpp
+++ b/src/IntegratedLibrary/PrintInstruction.cpp
@@ -110,6 +110,7 @@ extern "C"
     void PrintInstruction_print(const char *c, uint64_t addr)
     {
         std::cout << c;
+        std::cout.flush();
         if (addr == 0x6cac)
         {
             // std::cout << "TCOUNT: " << std::dec << ++pi_6cac << "\n";

From b49be54713d9afc1b2bc21e5a72795029896ec78 Mon Sep 17 00:00:00 2001
From: Malte von Ehren <malte.von.ehren@tum.de>
Date: Mon, 1 Aug 2022 20:56:53 +0200
Subject: [PATCH 08/44] add semihosting - semihosting implemented as a jitlib, 
  to be called from the CoreDSL code

---
 src/ETISS.cpp                           |   1 +
 src/Translation.cpp                     |   2 +
 src/jitlibs/CMakeLists.txt              |   3 +-
 src/jitlibs/semihost/CMakeLists.txt     |  25 ++
 src/jitlibs/semihost/SemihostingCalls.h |  32 ++
 src/jitlibs/semihost/libsemihost.h      |  17 +
 src/jitlibs/semihost/semihost.cpp       | 438 ++++++++++++++++++++++++
 src/jitlibs/semihost/semihosting.md     |  33 ++
 8 files changed, 550 insertions(+), 1 deletion(-)
 create mode 100644 src/jitlibs/semihost/CMakeLists.txt
 create mode 100644 src/jitlibs/semihost/SemihostingCalls.h
 create mode 100644 src/jitlibs/semihost/libsemihost.h
 create mode 100644 src/jitlibs/semihost/semihost.cpp
 create mode 100644 src/jitlibs/semihost/semihosting.md

diff --git a/src/ETISS.cpp b/src/ETISS.cpp
index 0299b98e38..d95e983b5a 100644
--- a/src/ETISS.cpp
+++ b/src/ETISS.cpp
@@ -725,6 +725,7 @@ void etiss_initialize(const std::vector<std::string>& args, bool forced = false)
             ("arch.or1k.ignore_sr_iee", po::value<bool>(), "Ignore exception on OpenRISC.")
             ("arch.or1k.if_stall_cycles", po::value<int>(), "Add instruction stall cycles on OpenRISC.")
             ("arch.cpu_cycle_time_ps", po::value<int>(), "Sets CPU cycles time on OpenRISC and ARM.")
+            ("arch.enable_semihosting", po::value<bool>(), "Enables semihosting operations")
             ("etiss.enable_dmi", po::value<bool>(), "Enables the Direct Memory Interface feature of SystemC to speed up memory accesses. This needs to be disabled for memory tracing.")
             ("etiss.log_pc", po::value<bool>(), "Enables logging of the program counter.")
             ("etiss.max_block_size", po::value<int>(), "Sets maximum amount of instructions in a block.")
diff --git a/src/Translation.cpp b/src/Translation.cpp
index 2a630d2712..85d2dcd05c 100644
--- a/src/Translation.cpp
+++ b/src/Translation.cpp
@@ -321,6 +321,7 @@ BlockLink *Translation::getBlock(BlockLink *prev, const etiss::uint64 &instructi
     block.fileglobalCode().insert("#include \"etiss/jit/CPU.h\"\n"
                                   "#include \"etiss/jit/System.h\"\n"
                                   "#include \"etiss/jit/libresources.h\"\n"
+                                  "#include \"etiss/jit/libsemihost.h\"\n"
                                   "#include \"etiss/jit/ReturnCode.h\"\n"
                                   "#include \"etiss/jit/libCSRCounters.h\"\n");
 
@@ -370,6 +371,7 @@ BlockLink *Translation::getBlock(BlockLink *prev, const etiss::uint64 &instructi
     std::set<std::string> libs;
     //libs.insert("ETISS");
     libs.insert("resources");
+    libs.insert("semihost");
     libs.insert("CSRCounters");
     for(auto & it: jitExtLibraries()){
        if(it != "") libs.insert(it);
diff --git a/src/jitlibs/CMakeLists.txt b/src/jitlibs/CMakeLists.txt
index 0ab8415c91..300e31a4ee 100644
--- a/src/jitlibs/CMakeLists.txt
+++ b/src/jitlibs/CMakeLists.txt
@@ -4,4 +4,5 @@ ENDMACRO()
 
 ADD_SUBDIRECTORY(softfloat)
 ADD_SUBDIRECTORY(resources)
-ADD_SUBDIRECTORY(CSRCounters)
\ No newline at end of file
+ADD_SUBDIRECTORY(semihost)
+ADD_SUBDIRECTORY(CSRCounters)
diff --git a/src/jitlibs/semihost/CMakeLists.txt b/src/jitlibs/semihost/CMakeLists.txt
new file mode 100644
index 0000000000..8fa0b41383
--- /dev/null
+++ b/src/jitlibs/semihost/CMakeLists.txt
@@ -0,0 +1,25 @@
+PROJECT(semihost)
+
+IF(WIN32)
+	SET(CMAKE_WINDOWS_EXPORT_ALL_SYMBOLS ON)
+ENDIF()
+
+ADD_LIBRARY(${PROJECT_NAME} SHARED
+    semihost.cpp
+)
+
+
+add_custom_command(
+  TARGET ${PROJECT_NAME} POST_BUILD VERBATIM
+  COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_BINARY_DIR}/include/jit/etiss/jit/
+  COMMAND ${CMAKE_COMMAND} -E copy "$<TARGET_FILE:${PROJECT_NAME}>" ${CMAKE_BINARY_DIR}/include/jit/etiss/jit/
+)
+
+  
+TARGET_LINK_LIBRARIES(${PROJECT_NAME} PUBLIC ETISS)
+
+INSTALL(FILES
+    libsemihost.h
+    DESTINATION include/jit/etiss/jit
+)
+InstallJitLib(${PROJECT_NAME})
diff --git a/src/jitlibs/semihost/SemihostingCalls.h b/src/jitlibs/semihost/SemihostingCalls.h
new file mode 100644
index 0000000000..5b705b8797
--- /dev/null
+++ b/src/jitlibs/semihost/SemihostingCalls.h
@@ -0,0 +1,32 @@
+#ifndef ETISS_INCLUDE_SEMIHOSTING_CALLS_H_
+#define ETISS_INCLUDE_SEMIHOSTING_CALLS_H_
+
+// taken from
+// https://github.com/ARM-software/abi-aa/releases/download/2022Q1/semihosting.pdf
+
+#define SYS_OPEN 0x01
+#define SYS_CLOSE 0x02
+#define SYS_WRITEC 0x03
+#define SYS_WRITE0 0x04
+#define SYS_WRITE 0x05
+#define SYS_READ 0x06
+#define SYS_READC 0x07
+#define SYS_ISERROR 0x08
+#define SYS_ISTTY 0x09
+#define SYS_SEEK 0x0A
+#define SYS_FLEN 0x0C
+#define SYS_TMPNAM 0x0D
+#define SYS_REMOVE 0x0E
+#define SYS_RENAME 0x0F
+#define SYS_CLOCK 0x10
+#define SYS_TIME 0x11
+#define SYS_SYSTEM 0x12
+#define SYS_ERRNO 0x13
+#define SYS_GET_CMDLINE 0x15
+#define SYS_HEAPINFO 0x16
+#define SYS_EXIT 0x18
+#define SYS_EXIT_EXTENDED 0x20
+#define SYS_ELAPSED 0x30
+#define SYS_TICKFREQ 0x31
+
+#endif
diff --git a/src/jitlibs/semihost/libsemihost.h b/src/jitlibs/semihost/libsemihost.h
new file mode 100644
index 0000000000..019a8bc614
--- /dev/null
+++ b/src/jitlibs/semihost/libsemihost.h
@@ -0,0 +1,17 @@
+#ifndef JITLIB_SEMIHOST_H
+#define JITLIB_SEMIHOST_H
+
+#include <stdint.h>
+#include "etiss/jit/CPU.h"
+#include "etiss/jit/System.h"
+
+/// Checks whether semihosting is enabled in the config
+uint8_t etiss_semihost_enabled();
+
+/// Executes the semihosting call based on the operation number.
+/// For description of all semihosting calls see:
+/// https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst
+int64_t etiss_semihost(ETISS_CPU *const cpu, ETISS_System *const etissSystem, void *const *const _, uint32_t XLEN,
+                       uint64_t operation, uint64_t parameter);
+
+#endif
diff --git a/src/jitlibs/semihost/semihost.cpp b/src/jitlibs/semihost/semihost.cpp
new file mode 100644
index 0000000000..cac6d5f4aa
--- /dev/null
+++ b/src/jitlibs/semihost/semihost.cpp
@@ -0,0 +1,438 @@
+#include <cstdio>
+#include "etiss/ETISS.h"
+
+#include "SemihostingCalls.h"
+
+extern "C"
+{
+#include "libsemihost.h"
+}
+
+// constant for SYS_ELAPSED and SYS_TICKFREQ
+#define TICKER_FREQ 1000 // Hz
+
+// constants for SYS_OPEN
+const char *SYS_OPEN_MODES_STRS[] = { "r", "rb", "r+", "r+b", "w", "wb", "w+", "w+b", "a", "ab", "a+", "a+b" };
+#define SYS_OPEN_MODES_TOTAL 12 // total number of modes
+#define SYS_OPEN_MODES_IN_LIMIT 4
+#define SYS_OPEN_MODES_OUT_LIMIT 8
+
+#define PS_PER_CS 10000000000 // 10 * 10^9
+
+// if var is negative set semihosting errno and return -1
+#define CHECK_NEGATIVE_RETURN(var) \
+    if ((var) < 0)                 \
+    {                              \
+        semihostingErrno = errno;  \
+        return -1;                 \
+    }
+
+// For many semihosting calls parameter points to a data block, so this type of call is very common
+#define FIELD(fieldNo) semihostReadStructField(etissSystem, XLEN / 8, parameter, fieldNo);
+
+// forward declaration for use in extern block:
+
+/// Executes the semihosting call based on the operation number.
+/// For description of all semihosting calls see:
+/// https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst
+etiss_int64 semihostingCall(ETISS_CPU *const cpu, ETISS_System *const etissSystem, etiss_uint32 XLEN,
+                            etiss_uint64 operationNumber, etiss_uint64 parameter);
+
+extern "C"
+{
+    uint8_t etiss_semihost_enabled()
+    {
+        return etiss::cfg().get<bool>("arch.enable_semihosting", false);
+    }
+
+    int64_t etiss_semihost(ETISS_CPU *const cpu, ETISS_System *const etissSystem, void *const *const _, uint32_t XLEN,
+                           uint64_t operation, uint64_t parameter)
+    {
+        return semihostingCall(cpu, etissSystem, XLEN, operation, parameter);
+    }
+}
+
+/// Assumes there is an array of numBytes long integers at address.
+/// Reads the filedNo-th field of this array an returns it as a uint64
+/// (0-indexed)
+etiss_uint64 semihostReadStructField(ETISS_System *etissSystem, etiss_uint32 numBytes, etiss_uint64 address,
+                                     int fieldNo)
+{
+    if (numBytes == 8)
+    {
+        etiss_uint64 field = 0;
+        etissSystem->dbg_read(etissSystem->handle, address + 8 * fieldNo, (etiss_uint8 *)&field, 8);
+        return field;
+    }
+    else if (numBytes == 4)
+    {
+        etiss_uint32 field = 0;
+        etissSystem->dbg_read(etissSystem->handle, address + 4 * fieldNo, (etiss_uint8 *)&field, 4);
+        return field;
+    }
+    else if (numBytes == 2)
+    {
+        etiss_uint16 field = 0;
+        etissSystem->dbg_read(etissSystem->handle, address + 2 * fieldNo, (etiss_uint8 *)&field, 2);
+        return field;
+    }
+    else if (numBytes == 1)
+    {
+        etiss_uint8 field = 0;
+        etissSystem->dbg_read(etissSystem->handle, address + 1 * fieldNo, &field, 1);
+        return field;
+    }
+
+    etiss::log(etiss::ERROR, "semihostReadStructField called with numBytes != 1, 2, 4 or 8");
+    return 0;
+}
+
+/// helper for reading a std::vector of bytes by address and length from an etiss system
+std::vector<etiss_uint8> semihostReadSystemMemory(ETISS_System *etissSystem, etiss_uint64 address, etiss_uint64 length)
+{
+    std::vector<etiss_uint8> buffer;
+    buffer.resize(length);
+    etissSystem->dbg_read(etissSystem->handle, address, buffer.data(), length);
+    return buffer;
+}
+
+/// helper for writing a std::vector of bytes to an etiss system
+void semihostWriteSystemMemory(ETISS_System *etissSystem, etiss_uint64 address, std::vector<etiss_uint8> data)
+{
+    etissSystem->dbg_write(etissSystem->handle, address, data.data(), data.size());
+}
+
+/// helper for reading a std::string by address and length from an etiss system
+std::string semihostReadString(ETISS_System *etissSystem, etiss_uint64 address, etiss_uint64 length)
+{
+    std::vector<etiss_uint8> buffer = semihostReadSystemMemory(etissSystem, address, length);
+    std::string str(buffer.begin(), buffer.end());
+    return str;
+}
+
+/// helper for writing a std::string to an etiss system
+void semihostWriteString(ETISS_System *etissSystem, etiss_uint64 address, std::string str)
+{
+    etissSystem->dbg_write(etissSystem->handle, address, (etiss_uint8 *)str.c_str(), str.length() + 1);
+}
+
+bool is_std_in_out_err(FILE *file)
+{
+    return file == stdin || file == stdout || file == stderr;
+}
+
+etiss_int64 semihostingCall(ETISS_CPU *const cpu, ETISS_System *const etissSystem, etiss_uint32 XLEN,
+                            etiss_uint64 operationNumber, etiss_uint64 parameter)
+{
+    // static variables to keep track of semihosting state
+
+    /// openFiles maps target file descriptors (uint) to host
+    /// file descriptors (FILE *).
+    static std::map<etiss_uint64, FILE *> openFiles;
+    /// next target file descriptor to be allocated.
+    /// starts at 0 for first target fd (stdin)
+    static etiss_uint64 nextFd = 0;
+    /// Local errno variable to set in semihosting functions
+    /// and return using SYS_ERRNO
+    static etiss_int64 semihostingErrno;
+
+    switch (operationNumber)
+    {
+    // share code between all operations that have the
+    // file descriptor as their first argument
+    case SYS_CLOSE:
+    case SYS_WRITE:
+    case SYS_READ:
+    case SYS_ISTTY:
+    case SYS_SEEK:
+    case SYS_FLEN:
+    {
+        etiss_uint64 fd = FIELD(0);
+        if (openFiles.count(fd) == 0)
+        {
+            std::stringstream ss;
+            ss << "Semihosting: invalid file descriptor " << fd << " for semihosting call 0x" << std::hex
+               << std::setfill('0') << std::setw(2) << operationNumber;
+            etiss::log(etiss::INFO, ss.str());
+            semihostingErrno = EBADF;
+            return -1;
+        }
+        auto file = openFiles[fd];
+
+        switch (operationNumber)
+        {
+        case SYS_CLOSE:
+        {
+            std::stringstream ss;
+            ss << "Semihosting: SYS_CLOSE fd " << fd;
+            etiss::log(etiss::VERBOSE, ss.str());
+
+            openFiles.erase(fd);
+            // do not close stdin, stdout, stderr of host process
+            if (!is_std_in_out_err(file))
+                fclose(file);
+            return 0;
+        }
+        case SYS_WRITE:
+        {
+            etiss_uint64 address = FIELD(1);
+            etiss_uint64 count = FIELD(2);
+
+            std::stringstream ss;
+            ss << "Semihosting: SYS_WRITE fd " << fd;
+            etiss::log(etiss::VERBOSE, ss.str());
+
+            std::vector<etiss_uint8> buffer = semihostReadSystemMemory(etissSystem, address, count);
+
+            size_t num_written = fwrite(buffer.data(), 1, count, file);
+            return count - num_written;
+        }
+        case SYS_READ:
+        {
+            etiss_uint64 address = FIELD(1);
+            etiss_uint64 count = FIELD(2);
+
+            std::stringstream ss;
+            ss << "Semihosting: SYS_READ fd " << fd << " count " << count;
+            etiss::log(etiss::VERBOSE, ss.str());
+
+            std::vector<etiss_uint8> buffer;
+            buffer.resize(count);
+
+            size_t num_read = 0;
+            if (file == stdin)
+            {
+                // when reading from stdin: mimic behaviour from read syscall
+                // and return on newline.
+                while (num_read < count)
+                {
+                    char c = fgetc(file);
+                    buffer[num_read] = c;
+                    num_read++;
+                    if (c == '\n')
+                        break;
+                }
+            }
+            else
+            {
+                num_read = fread(buffer.data(), 1, count, file);
+            }
+
+            buffer.resize(num_read);
+            semihostWriteSystemMemory(etissSystem, address, buffer);
+
+            return (etiss_int64)count - num_read;
+        }
+        case SYS_ISTTY:
+        {
+            std::stringstream ss;
+            ss << "Semihosting: SYS_ISTTY fd " << fd;
+            etiss::log(etiss::VERBOSE, ss.str());
+
+            return is_std_in_out_err(file);
+        }
+        case SYS_SEEK:
+        {
+            etiss_uint64 position = FIELD(1);
+
+            std::stringstream ss;
+            ss << "Semihosting: SYS_SEEK fd " << fd << ": " << position;
+            etiss::log(etiss::VERBOSE, ss.str());
+
+            int retval = fseek(file, position, SEEK_SET);
+            CHECK_NEGATIVE_RETURN(retval);
+            return 0;
+        }
+        case SYS_FLEN:
+        {
+            std::stringstream ss;
+            ss << "Semihosting: SYS_FLEN fd " << fd;
+            etiss::log(etiss::VERBOSE, ss.str());
+
+            size_t currentPos = ftell(file);
+            CHECK_NEGATIVE_RETURN(currentPos);
+            fseek(file, 0, SEEK_END);
+            size_t length = ftell(file);
+            fseek(file, currentPos, SEEK_SET);
+            return (etiss_int64)length;
+        }
+        }
+    }
+    case SYS_OPEN:
+    {
+        etiss_uint64 path_str_addr = FIELD(0);
+        etiss_uint64 mode = FIELD(1);
+        etiss_uint64 path_str_len = FIELD(2);
+
+        std::string path_str = semihostReadString(etissSystem, path_str_addr, path_str_len);
+
+        std::stringstream ss;
+        ss << "Semihosting: SYS_OPEN \"" << path_str << "\"";
+        etiss::log(etiss::VERBOSE, ss.str());
+
+        if (mode >= SYS_OPEN_MODES_TOTAL)
+        {
+            // invalid mode
+            semihostingErrno = EINVAL;
+            return -1;
+        }
+
+        FILE *file = nullptr;
+        if (path_str == ":tt")
+        {
+            // special file path for opening stdin, stdout and stderr
+            // open stdin, stdout or stderr depending on mode argument
+            if (mode < SYS_OPEN_MODES_IN_LIMIT) // 0 <= mode <= 3
+                file = stdin;
+            else if (mode < SYS_OPEN_MODES_OUT_LIMIT) // 4 <= mode <= 7
+                file = stdout;
+            else // 8 <= mode <= 11
+                file = stderr;
+        }
+        else
+        {
+            file = fopen(path_str.c_str(), SYS_OPEN_MODES_STRS[mode]);
+            if (file == nullptr)
+            {
+                semihostingErrno = errno;
+                return -1;
+            }
+        }
+        etiss_uint64 fd = nextFd++;
+        openFiles[fd] = file;
+
+        return (etiss_int64)fd;
+    }
+    case SYS_WRITEC:
+    {
+        etiss_uint64 character = semihostReadStructField(etissSystem, 1, parameter, 0);
+        putchar(character);
+        return 0;
+    }
+    case SYS_WRITE0:
+    {
+        etiss_uint64 address = parameter;
+        while (1)
+        {
+            etiss_uint64 character = semihostReadStructField(etissSystem, 1, address, 0);
+            if (character == 0)
+                break;
+            putchar(character);
+            address++;
+        }
+        return 0;
+    }
+    case SYS_READC:
+    {
+        return getchar();
+    }
+    case SYS_ISERROR:
+    {
+        etiss_uint64 value = FIELD(0);
+        return value != 0;
+    }
+    case SYS_TMPNAM:
+    {
+        etiss_uint64 buffer_address = FIELD(0);
+        etiss_uint64 identifier = FIELD(1);
+        etiss_uint64 buffer_len = FIELD(2);
+
+        if (identifier > 255)
+            return -1;
+
+        std::stringstream ss;
+        ss << "etiss-tmp/file-" << std::setfill('0') << std::setw(3) << identifier;
+        std::string filename = ss.str();
+
+        if (buffer_len <= filename.length() + 1)
+            return -1;
+
+        semihostWriteString(etissSystem, buffer_address, filename);
+        return 0;
+    }
+    case SYS_REMOVE:
+    {
+        etiss_uint64 path_str_addr = FIELD(0);
+        etiss_uint64 path_str_len = FIELD(1);
+
+        std::string path_str = semihostReadString(etissSystem, path_str_addr, path_str_len);
+
+        std::stringstream ss;
+        ss << "Semihosting: SYS_REMOVE \"" << path_str << "\"";
+        etiss::log(etiss::VERBOSE, ss.str());
+
+        if (remove(path_str.c_str()) < 0)
+        {
+            semihostingErrno = errno;
+            return -1;
+        }
+        return 0;
+    }
+    case SYS_RENAME:
+    {
+        etiss_uint64 old_str_addr = FIELD(0);
+        etiss_uint64 old_str_len = FIELD(1);
+        etiss_uint64 new_str_addr = FIELD(2);
+        etiss_uint64 new_str_len = FIELD(3);
+
+        std::string old_str = semihostReadString(etissSystem, old_str_addr, old_str_len);
+        std::string new_str = semihostReadString(etissSystem, new_str_addr, new_str_len);
+
+        std::stringstream ss;
+        ss << "Semihosting: SYS_RENAME \"" << old_str << "\" to \"" << new_str << "\"";
+        etiss::log(etiss::VERBOSE, ss.str());
+
+        return rename(old_str.c_str(), new_str.c_str());
+    }
+    case SYS_CLOCK:
+    {
+        // return centiseconds since some arbitrary start point
+        return cpu->cpuTime_ps / PS_PER_CS;
+    }
+    case SYS_TIME:
+    {
+        etiss::log(etiss::VERBOSE, "Semihosting: SYS_TIME");
+        etiss_int64 seconds_since_epoch = (etiss_int64)std::time(0);
+        return seconds_since_epoch;
+    }
+    case SYS_ERRNO:
+    {
+        std::stringstream ss;
+        ss << "Semihosting: SYS_ERRNO (" << semihostingErrno << ")";
+        etiss::log(etiss::VERBOSE, ss.str());
+        return semihostingErrno;
+    }
+    case SYS_EXIT:
+    {
+        etiss::log(etiss::VERBOSE, "Semihosting: SYS_EXIT -> exit simulator");
+
+        cpu->exception = ETISS_RETURNCODE_CPUFINISHED;
+        cpu->return_pending = 1;
+    }
+    case SYS_ELAPSED:
+    {
+        return cpu->cpuTime_ps / TICKER_FREQ;
+    }
+    case SYS_TICKFREQ:
+    {
+        return TICKER_FREQ;
+    }
+    case SYS_SYSTEM:
+    case SYS_GET_CMDLINE:
+    case SYS_HEAPINFO:
+    case SYS_EXIT_EXTENDED:
+    {
+        std::stringstream ss;
+        ss << "Semihosting: operation not implemented: " << operationNumber;
+        etiss::log(etiss::WARNING, ss.str());
+        return 0;
+    }
+    default:
+    {
+        std::stringstream ss;
+        ss << "Semihosting: unknown operation number: " << operationNumber;
+        etiss::log(etiss::WARNING, ss.str());
+        return 0;
+    }
+    }
+}
diff --git a/src/jitlibs/semihost/semihosting.md b/src/jitlibs/semihost/semihosting.md
new file mode 100644
index 0000000000..e02d8d7018
--- /dev/null
+++ b/src/jitlibs/semihost/semihosting.md
@@ -0,0 +1,33 @@
+# Semihosting in ETISS
+
+This JitLib offers semihosting to features to architectures in ETISS.
+The specific semihosting calls implemented by this library are used by Arm and RISC-V (https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst, https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc).
+
+The JitLib provides the functions `etiss_semihost_enabled` and `etiss_semihost`.
+The former returns the value of the config option `arch.enable_semihosting` and is called by the architectures prior to executing a semihosting call.
+The latter is the actual semihosting implementation.
+It is called with the values of the operation and parameter registers, executes the semihosting call, and returns the value of the return register.
+For technical reasons also the bit-width of the architecture, the `ETISS_CPU` and the `ETISS_SYSTEM` are passed to this function.
+
+The JitLib keeps track of some minimal state, such as the open file descriptors.
+
+Semihosting can be used to exit from the simulator.
+For this, the semihosting call `SYS_EXIT` is used.
+Internally, it sets the exception variable of the CPU to `ETISS_RETURNCODE_CPUFINISHED` and `return_pending` to 1.
+
+# CoreDSL Implementation for RISC-V
+
+For RISC-V the instruction sequence
+```
+slli x0, x0, 0x1f       # 0x01f01013    Entry NOP
+ebreak                  # 0x00100073    Break to debugger
+srai x0, x0, 7          # 0x40705013    NOP encoding the semihosting call number 7
+```
+is used to execute the semihosting call.
+
+In the CoreDSL code we override the `ebreak` instruction.
+It first checks whether semihosting is enabled and, if so, checks whether the instruction before and after match the required sequence.
+If they match this JitLib will be called with the values of the `a0` and the `a1` registers as the operation and parameter arguments.
+After this function return the return value is written to register `a0`.
+
+In case semihosting is disabled, or the instruction sequence does not match, the normal action for `ebreak` is executed: raising a breakpoint exception.

From 4c0f8585a3247670eb55c0b5e66b99350dcdc04f Mon Sep 17 00:00:00 2001
From: Malte von Ehren <malte.von.ehren@tum.de>
Date: Mon, 1 Aug 2022 21:42:03 +0200
Subject: [PATCH 09/44] add semihosting to RISC-V

---
 ArchImpl/RISCV/RISCVArch.cpp                  |   94 +-
 ArchImpl/RISCV/RISCVArchSpecificImp.h         |    4 +-
 ArchImpl/RISCV64/RISCV64Arch.cpp              |  105 +-
 ArchImpl/RISCV64/RISCV64ArchSpecificImp.h     |    4 +-
 ArchImpl/RV32IMACFD/CMakeLists.txt            |    3 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp |   47 +-
 .../RV32IMACFD/RV32IMACFD_RV32IInstr_new.cpp  | 2883 +++++++++++++++++
 .../RV32IMACFD_tum_semihostingInstr.cpp       |   88 +
 8 files changed, 3096 insertions(+), 132 deletions(-)
 mode change 100755 => 100644 ArchImpl/RISCV/RISCVArchSpecificImp.h
 create mode 100644 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr_new.cpp
 create mode 100644 ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp

diff --git a/ArchImpl/RISCV/RISCVArch.cpp b/ArchImpl/RISCV/RISCVArch.cpp
index f359d3394c..a3d5e86397 100644
--- a/ArchImpl/RISCV/RISCVArch.cpp
+++ b/ArchImpl/RISCV/RISCVArch.cpp
@@ -6665,46 +6665,62 @@ return true;
 nullptr
 );
 //-------------------------------------------------------------------------------------------------------------------
+// EBREAK ----------------------------------------------------------------------
 static InstructionDefinition ebreak_(
- 		ISA32_RISCV,
- 		"ebreak",
- 		(uint32_t)0x100073,
- 		(uint32_t) 0xffffffff,
- 		[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
- 		{
- 		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
-		partInit.getAffectedRegisters().add("instructionPointer",32);
- 	partInit.code() = std::string("//ebreak\n")+
- 			"etiss_uint32 exception = 0;\n"
- 			"etiss_uint32 temp = 0;\n"
- 			"etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
-			#if RISCV_Pipeline1
-			"etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
-			"etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
-			"etiss_uint32 num_stages = 4;\n"
-			"etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
-			"handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
-			#endif
-			#if RISCV_Pipeline2
-			"etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
-			"etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
-			"etiss_uint32 num_stages = 4;\n"
-			"etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
-			"handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
-			#endif
-
- 			
-"return ETISS_RETURNCODE_CPUFINISHED; \n"
- 			
-		"cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n"
-		
-		"return exception;\n"
-; 
-return true;
-},
-0,
-nullptr
-);
+    ISA32_RISCV, "ebreak", (uint32_t)0x100073, (uint32_t)0xffffffff,
+    [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic)
+    {
+        CodePart &partInit = cs.append(CodePart::INITIALREQUIRED);
+
+        partInit.code() = std::string("//EBREAK\n");
+
+        // -----------------------------------------------------------------------------
+        partInit.code() += "int exception = 0;\n";
+        partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+        partInit.code() += "if (etiss_semihost_enabled()) {\n";
+        partInit.code() += "etiss_uint32 mem_val_0;\n";
+        partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4U) + ", (etiss_uint8*)&mem_val_0, 4);\n";
+        partInit.code() += "etiss_uint32 mem_val_1;\n";
+        partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0U) + ", (etiss_uint8*)&mem_val_1, 4);\n";
+        partInit.code() += "etiss_uint32 mem_val_2;\n";
+        partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4U) + ", (etiss_uint8*)&mem_val_2, 4);\n";
+        partInit.code() += "if ((etiss_uint32)(mem_val_0) == 32509971U && (etiss_uint32)(mem_val_1) == 1048691U && (etiss_uint32)(mem_val_2) == 1081102355U) {\n";
+        partInit.code() += "etiss_uint32 operation = *((RISCV*)cpu)->X[10U];\n";
+        partInit.code() += "etiss_uint32 parameter = *((RISCV*)cpu)->X[11U];\n";
+        partInit.code() += "*((RISCV*)cpu)->X[10U] = etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(32) +
+                           ", operation, parameter);\n";
+        partInit.code() += "}\n";
+        partInit.code() += " else {\n";
+        partInit.code() += "exception = ETISS_RETURNCODE_BREAKPOINT;\n";
+        partInit.code() += "}\n";
+        partInit.code() += "}\n";
+        partInit.code() += " else {\n";
+        partInit.code() += "exception = ETISS_RETURNCODE_BREAKPOINT;\n";
+        partInit.code() += "}\n";
+        partInit.code() += "return exception;\n";
+        // -----------------------------------------------------------------------------
+
+        partInit.getRegisterDependencies().add(reg_name[10U], 32);
+        partInit.getRegisterDependencies().add(reg_name[11U], 32);
+        partInit.getAffectedRegisters().add(reg_name[10U], 32);
+        partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+        return true;
+    },
+    0,
+    [](BitArray &ba, Instruction &instr)
+    {
+        // -----------------------------------------------------------------------------
+
+        // -----------------------------------------------------------------------------
+
+        std::stringstream ss;
+        // -----------------------------------------------------------------------------
+        ss << "ebreak"
+           << " # " << ba << (" []");
+        // -----------------------------------------------------------------------------
+        return ss.str();
+});
 //-------------------------------------------------------------------------------------------------------------------
 static InstructionDefinition sret_(
  		ISA32_RISCV,
diff --git a/ArchImpl/RISCV/RISCVArchSpecificImp.h b/ArchImpl/RISCV/RISCVArchSpecificImp.h
old mode 100755
new mode 100644
index 00b0c4a23f..5766d17981
--- a/ArchImpl/RISCV/RISCVArchSpecificImp.h
+++ b/ArchImpl/RISCV/RISCVArchSpecificImp.h
@@ -362,10 +362,10 @@ void RISCVArch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const
      /* Set default JIT Extensions. Read Parameters set from ETISS configuration and append with architecturally needed */
      std::string cfgPar = "";
      cfgPar = etiss::cfg().get<std::string>("jit.external_headers", ";");
-     etiss::cfg().set<std::string>("jit.external_headers", cfgPar + "etiss/jit/libsoftfloat.h");
+     etiss::cfg().set<std::string>("jit.external_headers", cfgPar + "etiss/jit/libsoftfloat.h;");
 
      cfgPar = etiss::cfg().get<std::string>("jit.external_libs", ";");
-     etiss::cfg().set<std::string>("jit.external_libs", cfgPar + "softfloat");
+     etiss::cfg().set<std::string>("jit.external_libs", cfgPar + "softfloat;");
 
      cfgPar = etiss::cfg().get<std::string>("jit.external_header_paths", ";");
      etiss::cfg().set<std::string>("jit.external_header_paths", cfgPar + "/etiss/jit");
diff --git a/ArchImpl/RISCV64/RISCV64Arch.cpp b/ArchImpl/RISCV64/RISCV64Arch.cpp
index 66864a3021..fe0008ac9c 100644
--- a/ArchImpl/RISCV64/RISCV64Arch.cpp
+++ b/ArchImpl/RISCV64/RISCV64Arch.cpp
@@ -7938,46 +7938,67 @@ return true;
 nullptr
 );
 //-------------------------------------------------------------------------------------------------------------------
+// EBREAK ----------------------------------------------------------------------
 static InstructionDefinition ebreak_(
- 		ISA32_RISCV64,
- 		"ebreak",
- 		(uint32_t)0x100073,
- 		(uint32_t) 0xffffffff,
- 		[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
- 		{
- 		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
-		partInit.getAffectedRegisters().add("instructionPointer",64);
- 	partInit.code() = std::string("//ebreak\n")+
- 			"etiss_uint32 exception = 0;\n"
- 			"etiss_uint32 temp = 0;\n"
- 			"etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
-			#if RISCV64_Pipeline1
-			"etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
-			"etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
-			"etiss_uint32 num_stages = 4;\n"
-			"etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
-			"handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
-			#endif
-			#if RISCV64_Pipeline2
-			"etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
-			"etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
-			"etiss_uint32 num_stages = 4;\n"
-			"etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
-			"handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
-			#endif
-
- 			
-"return ETISS_RETURNCODE_CPUFINISHED; \n"
- 			
-		"cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
-		
-		"return exception;\n"
-; 
-return true;
-},
-0,
-nullptr
-);
+    ISA32_RISCV64, "ebreak", (uint32_t)0x100073, (uint32_t)0xffffffff,
+    [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic)
+    {
+        CodePart &partInit = cs.append(CodePart::INITIALREQUIRED);
+
+        partInit.code() = std::string("//EBREAK\n");
+
+        // -----------------------------------------------------------------------------
+        partInit.code() += "int exception = 0;\n";
+        partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+        partInit.code() += "if (etiss_semihost_enabled()) {\n";
+        partInit.code() += "etiss_uint32 mem_val_0;\n";
+        partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, " +
+                           std::to_string(ic.current_address_ - 4U) + ", (etiss_uint8*)&mem_val_0, 4);\n";
+        partInit.code() += "etiss_uint32 mem_val_1;\n";
+        partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, " +
+                           std::to_string(ic.current_address_ + 0U) + ", (etiss_uint8*)&mem_val_1, 4);\n";
+        partInit.code() += "etiss_uint32 mem_val_2;\n";
+        partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, " +
+                           std::to_string(ic.current_address_ + 4U) + ", (etiss_uint8*)&mem_val_2, 4);\n";
+        partInit.code() += "if ((etiss_uint32)(mem_val_0) == 32509971U && (etiss_uint32)(mem_val_1) == 1048691U && "
+                           "(etiss_uint32)(mem_val_2) == 1081102355U) {\n";
+        partInit.code() += "etiss_uint32 operation = *((RISCV64*)cpu)->X[10U];\n";
+        partInit.code() += "etiss_uint32 parameter = *((RISCV64*)cpu)->X[11U];\n";
+        partInit.code() += "*((RISCV64*)cpu)->X[10U] = etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(64) +
+                           ", operation, parameter);\n";
+        partInit.code() += "}\n";
+        partInit.code() += " else {\n";
+        partInit.code() += "exception = ETISS_RETURNCODE_BREAKPOINT;\n";
+        partInit.code() += "}\n";
+        partInit.code() += "}\n";
+        partInit.code() += " else {\n";
+        partInit.code() += "exception = ETISS_RETURNCODE_BREAKPOINT;\n";
+        partInit.code() += "}\n";
+        partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+        partInit.code() += "return exception;\n";
+        // -----------------------------------------------------------------------------
+
+        partInit.getRegisterDependencies().add(reg_name[10U], 32);
+        partInit.getRegisterDependencies().add(reg_name[11U], 32);
+        partInit.getAffectedRegisters().add(reg_name[10U], 32);
+        partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+        return true;
+    },
+    0,
+    [](BitArray &ba, Instruction &instr)
+    {
+        // -----------------------------------------------------------------------------
+
+        // -----------------------------------------------------------------------------
+
+        std::stringstream ss;
+        // -----------------------------------------------------------------------------
+        ss << "ebreak"
+           << " # " << ba << (" []");
+        // -----------------------------------------------------------------------------
+        return ss.str();
+});
 //-------------------------------------------------------------------------------------------------------------------
 static InstructionDefinition sret_(
  		ISA32_RISCV64,
@@ -8593,7 +8614,7 @@ static InstructionDefinition mulh_rd_rs1_rs2(
 	#if RISCV64_DEBUG_CALL
 	"printf(\"res = %#lx\\n\",res); \n"
 	#endif	
-	"*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(res >> 64);\n"
+	"*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(0);\n"
 	#if RISCV64_DEBUG_CALL
 	"printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
 	#endif	
@@ -8664,7 +8685,7 @@ static InstructionDefinition mulhsu_rd_rs1_rs2(
 	#if RISCV64_DEBUG_CALL
 	"printf(\"res = %#lx\\n\",res); \n"
 	#endif	
-	"*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(res >> 64);\n"
+	"*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(0);\n"
 	#if RISCV64_DEBUG_CALL
 	"printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
 	#endif	
@@ -8730,7 +8751,7 @@ static InstructionDefinition mulhu_rd_rs1_rs2(
 	#if RISCV64_DEBUG_CALL
 	"printf(\"res = %#lx\\n\",res); \n"
 	#endif	
-	"*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(res >> 64);\n"
+	"*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(0);\n"
 	#if RISCV64_DEBUG_CALL
 	"printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
 	#endif	
diff --git a/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h b/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h
index ed283366da..25b9a10f75 100644
--- a/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h
+++ b/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h
@@ -385,10 +385,10 @@ void RISCV64Arch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const
      /* Set default JIT Extensions. Read Parameters set from ETISS configuration and append with architecturally needed */
      std::string cfgPar = "";
      cfgPar = etiss::cfg().get<std::string>("jit.external_headers", ";");
-     etiss::cfg().set<std::string>("jit.external_headers", cfgPar + "etiss/jit/libsoftfloat.h");
+     etiss::cfg().set<std::string>("jit.external_headers", cfgPar + "etiss/jit/libsoftfloat.h;");
 
      cfgPar = etiss::cfg().get<std::string>("jit.external_libs", ";");
-     etiss::cfg().set<std::string>("jit.external_libs", cfgPar + "softfloat");
+     etiss::cfg().set<std::string>("jit.external_libs", cfgPar + "softfloat;");
 
      cfgPar = etiss::cfg().get<std::string>("jit.external_header_paths", ";");
      etiss::cfg().set<std::string>("jit.external_header_paths", cfgPar + "/etiss/jit");
diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index 3b84fca035..234e5b31c5 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+# Generated on Mon, 01 Aug 2022 21:07:00 +0200.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
@@ -21,6 +21,7 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFD_tum_retInstr.cpp
 	RV32IMACFD_RV32AInstr.cpp
 	RV32IMACFD_tum_rvaInstr.cpp
+	RV32IMACFD_tum_semihostingInstr.cpp
 )
 
 FILE(COPY "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}")
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 1de17e0601..c5a43ee7bb 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,6 @@
 /**
  * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * modified for semihosting Mon, 01 Aug 2022 21:00:00 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -2782,52 +2783,6 @@ ss << "ecall" << " # " << ba << (" []");
 	}
 );
 
-// EBREAK ----------------------------------------------------------------------
-static InstructionDefinition ebreak_ (
-	ISA32_RV32IMACFD,
-	"ebreak",
-	(uint32_t) 0x100073,
-	(uint32_t) 0xffffffff,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
-
-		partInit.code() = std::string("//EBREAK\n");
-
-// -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 3U);\n";
-partInit.code() += "return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "ebreak" << " # " << ba << (" []");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
 // WFI -------------------------------------------------------------------------
 static InstructionDefinition wfi_ (
 	ISA32_RV32IMACFD,
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr_new.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr_new.cpp
new file mode 100644
index 0000000000..f419f91b72
--- /dev/null
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr_new.cpp
@@ -0,0 +1,2883 @@
+/**
+ * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
+ * modified for semihosting Mon, 25 Jul 2022 12:49:45 +0200.
+ *
+ * This file contains the instruction behavior models of the RV32I
+ * instruction set for the RV32IMACFD core architecture.
+ */
+
+#include "RV32IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV32IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// LUI -------------------------------------------------------------------------
+static InstructionDefinition lui_rd_imm (
+	ISA32_RV32IMACFD,
+	"lui",
+	(uint32_t) 0x000037,
+	(uint32_t) 0x00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(31, 12);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LUI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string((etiss_int32)(imm)) + ";\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(31, 12);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lui" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AUIPC -----------------------------------------------------------------------
+static InstructionDefinition auipc_rd_imm (
+	ISA32_RV32IMACFD,
+	"auipc",
+	(uint32_t) 0x000017,
+	(uint32_t) 0x00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(31, 12);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AUIPC\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(31, 12);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "auipc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// JAL -------------------------------------------------------------------------
+static InstructionDefinition jal_rd_imm (
+	ISA32_RV32IMACFD,
+	"jal",
+	(uint32_t) 0x00006f,
+	(uint32_t) 0x00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(19, 12);
+imm += R_imm_12.read(ba) << 12;
+static BitArrayRange R_imm_11(20, 20);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(30, 21);
+imm += R_imm_1.read(ba) << 1;
+static BitArrayRange R_imm_20(31, 31);
+imm += R_imm_20.read(ba) << 20;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//JAL\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
+}
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(19, 12);
+imm += R_imm_12.read(ba) << 12;
+static BitArrayRange R_imm_11(20, 20);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(30, 21);
+imm += R_imm_1.read(ba) << 1;
+static BitArrayRange R_imm_20(31, 31);
+imm += R_imm_20.read(ba) << 20;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "jal" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// JALR ------------------------------------------------------------------------
+static InstructionDefinition jalr_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"jalr",
+	(uint32_t) 0x000067,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//JALR\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2U;\n";
+partInit.code() += "if (new_pc % 2U) {\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = new_pc & -2U;\n";
+partInit.code() += "}\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "jalr" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BEQ -------------------------------------------------------------------------
+static InstructionDefinition beq_imm_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"beq",
+	(uint32_t) 0x000063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BEQ\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "beq" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BNE -------------------------------------------------------------------------
+static InstructionDefinition bne_imm_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"bne",
+	(uint32_t) 0x001063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BNE\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "bne" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BLT -------------------------------------------------------------------------
+static InstructionDefinition blt_imm_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"blt",
+	(uint32_t) 0x004063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BLT\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "blt" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BGE -------------------------------------------------------------------------
+static InstructionDefinition bge_imm_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"bge",
+	(uint32_t) 0x005063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BGE\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "bge" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BLTU ------------------------------------------------------------------------
+static InstructionDefinition bltu_imm_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"bltu",
+	(uint32_t) 0x006063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BLTU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "bltu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BGEU ------------------------------------------------------------------------
+static InstructionDefinition bgeu_imm_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"bgeu",
+	(uint32_t) 0x007063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BGEU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "if (cpu->return_pending | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "bgeu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LB --------------------------------------------------------------------------
+static InstructionDefinition lb_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"lb",
+	(uint32_t) 0x000003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LB\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint8 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
+}
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lb" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LH --------------------------------------------------------------------------
+static InstructionDefinition lh_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"lh",
+	(uint32_t) 0x001003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LH\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint16 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
+}
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LW --------------------------------------------------------------------------
+static InstructionDefinition lw_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"lw",
+	(uint32_t) 0x002003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
+}
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LBU -------------------------------------------------------------------------
+static InstructionDefinition lbu_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"lbu",
+	(uint32_t) 0x004003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LBU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint8 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
+}
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lbu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LHU -------------------------------------------------------------------------
+static InstructionDefinition lhu_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"lhu",
+	(uint32_t) 0x005003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LHU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint16 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
+}
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SB --------------------------------------------------------------------------
+static InstructionDefinition sb_imm_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"sb",
+	(uint32_t) 0x000023,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SB\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sb" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SH --------------------------------------------------------------------------
+static InstructionDefinition sh_imm_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"sh",
+	(uint32_t) 0x001023,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SH\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sh" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SW --------------------------------------------------------------------------
+static InstructionDefinition sw_imm_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"sw",
+	(uint32_t) 0x002023,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ADDI ------------------------------------------------------------------------
+static InstructionDefinition addi_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"addi",
+	(uint32_t) 0x000013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ADDI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "addi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLTI ------------------------------------------------------------------------
+static InstructionDefinition slti_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"slti",
+	(uint32_t) 0x002013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLTI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "slti" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLTIU -----------------------------------------------------------------------
+static InstructionDefinition sltiu_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"sltiu",
+	(uint32_t) 0x003013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLTIU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ")) ? (1U) : (0U);\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sltiu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// XORI ------------------------------------------------------------------------
+static InstructionDefinition xori_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"xori",
+	(uint32_t) 0x004013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//XORI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "xori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ORI -------------------------------------------------------------------------
+static InstructionDefinition ori_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"ori",
+	(uint32_t) 0x006013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ORI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ANDI ------------------------------------------------------------------------
+static InstructionDefinition andi_rd_rs1_imm (
+	ISA32_RV32IMACFD,
+	"andi",
+	(uint32_t) 0x007013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ANDI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "andi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLLI ------------------------------------------------------------------------
+static InstructionDefinition slli_rd_rs1_shamt (
+	ISA32_RV32IMACFD,
+	"slli",
+	(uint32_t) 0x001013,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(shamt) + ";\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRLI ------------------------------------------------------------------------
+static InstructionDefinition srli_rd_rs1_shamt (
+	ISA32_RV32IMACFD,
+	"srli",
+	(uint32_t) 0x005013,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> " + std::to_string(shamt) + ";\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRAI ------------------------------------------------------------------------
+static InstructionDefinition srai_rd_rs1_shamt (
+	ISA32_RV32IMACFD,
+	"srai",
+	(uint32_t) 0x40005013,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRAI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> " + std::to_string(shamt) + ";\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ADD -------------------------------------------------------------------------
+static InstructionDefinition add_rd_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"add",
+	(uint32_t) 0x000033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ADD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "add" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SUB -------------------------------------------------------------------------
+static InstructionDefinition sub_rd_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"sub",
+	(uint32_t) 0x40000033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SUB\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sub" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLL -------------------------------------------------------------------------
+static InstructionDefinition sll_rd_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"sll",
+	(uint32_t) 0x001033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLL\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sll" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLT -------------------------------------------------------------------------
+static InstructionDefinition slt_rd_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"slt",
+	(uint32_t) 0x002033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLT\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "slt" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLTU ------------------------------------------------------------------------
+static InstructionDefinition sltu_rd_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"sltu",
+	(uint32_t) 0x003033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLTU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sltu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// XOR -------------------------------------------------------------------------
+static InstructionDefinition xor_rd_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"xor",
+	(uint32_t) 0x004033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//XOR\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "xor" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRL -------------------------------------------------------------------------
+static InstructionDefinition srl_rd_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"srl",
+	(uint32_t) 0x005033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRL\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "srl" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRA -------------------------------------------------------------------------
+static InstructionDefinition sra_rd_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"sra",
+	(uint32_t) 0x40005033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRA\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sra" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// OR --------------------------------------------------------------------------
+static InstructionDefinition or_rd_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"or",
+	(uint32_t) 0x006033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//OR\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "or" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AND -------------------------------------------------------------------------
+static InstructionDefinition and_rd_rs1_rs2 (
+	ISA32_RV32IMACFD,
+	"and",
+	(uint32_t) 0x007033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AND\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "and" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FENCE -----------------------------------------------------------------------
+static InstructionDefinition fence_rd_rs1_succ_pred_fm (
+	ISA32_RV32IMACFD,
+	"fence",
+	(uint32_t) 0x00000f,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 succ = 0;
+static BitArrayRange R_succ_0(23, 20);
+succ += R_succ_0.read(ba) << 0;
+etiss_uint32 pred = 0;
+static BitArrayRange R_pred_0(27, 24);
+pred += R_pred_0.read(ba) << 0;
+etiss_uint32 fm = 0;
+static BitArrayRange R_fm_0(31, 28);
+fm += R_fm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FENCE\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(0) + "] = " + std::to_string(pred << 4U | succ) + ";\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint32 succ = 0;
+static BitArrayRange R_succ_0(23, 20);
+succ += R_succ_0.read(ba) << 0;
+etiss_uint32 pred = 0;
+static BitArrayRange R_pred_0(27, 24);
+pred += R_pred_0.read(ba) << 0;
+etiss_uint32 fm = 0;
+static BitArrayRange R_fm_0(31, 28);
+fm += R_fm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fence" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | succ=" + std::to_string(succ) + " | pred=" + std::to_string(pred) + " | fm=" + std::to_string(fm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ECALL -----------------------------------------------------------------------
+static InstructionDefinition ecall_ (
+	ISA32_RV32IMACFD,
+	"ecall",
+	(uint32_t) 0x000073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ECALL\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ecall" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+
+// WFI -------------------------------------------------------------------------
+static InstructionDefinition wfi_ (
+	ISA32_RV32IMACFD,
+	"wfi",
+	(uint32_t) 0x10500073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//WFI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->exception = ETISS_RETURNCODE_CPUFINISHED;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "wfi" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// DRET ------------------------------------------------------------------------
+static InstructionDefinition dret_ (
+	ISA32_RV32IMACFD,
+	"dret",
+	(uint32_t) 0x7b200073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//DRET\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "if (((RV32IMACFD*)cpu)->PRIV < 4U) {\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "cpu->instructionPointer = ((RV32IMACFD*)cpu)->DPC;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->PRIV = (((RV32IMACFD*)cpu)->PRIV & 3U) & 0x7;\n";
+partInit.code() += "}\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "dret" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
new file mode 100644
index 0000000000..c07738b95c
--- /dev/null
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -0,0 +1,88 @@
+/**
+ * Generated on Mon, 01 Aug 2022 21:07:00 +0200.
+ *
+ * This file contains the instruction behavior models of the tum_semihosting
+ * instruction set for the RV32IMACFD core architecture.
+ */
+
+#include "RV32IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV32IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// EBREAK ----------------------------------------------------------------------
+static InstructionDefinition ebreak_ (
+	ISA32_RV32IMACFD,
+	"ebreak",
+	(uint32_t) 0x100073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//EBREAK\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "if (etiss_semihost_enabled()) {\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4U) + ", (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0U) + ", (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
+partInit.code() += "etiss_uint32 mem_val_2;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4U) + ", (etiss_uint8*)&mem_val_2, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
+partInit.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
+partInit.code() += "etiss_uint32 operation = *((RV32IMACFD*)cpu)->X[10U];\n";
+partInit.code() += "etiss_uint32 parameter = *((RV32IMACFD*)cpu)->X[11U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[10U] = (etiss_int32)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(32) + ", operation, parameter));\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + ");\n";
+partInit.code() += "}\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + ");\n";
+partInit.code() += "}\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[10U], 32);
+		partInit.getRegisterDependencies().add(reg_name[11U], 32);
+		partInit.getAffectedRegisters().add(reg_name[10U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ebreak" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);

From 8364f7e5b965addcdcdc187d2480fe70d38626a4 Mon Sep 17 00:00:00 2001
From: Malte von Ehren <malte.von.ehren@tum.de>
Date: Thu, 4 Aug 2022 19:00:43 +0200
Subject: [PATCH 10/44] avoid fallthrough

---
 src/jitlibs/semihost/semihost.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/jitlibs/semihost/semihost.cpp b/src/jitlibs/semihost/semihost.cpp
index cac6d5f4aa..964a897030 100644
--- a/src/jitlibs/semihost/semihost.cpp
+++ b/src/jitlibs/semihost/semihost.cpp
@@ -408,6 +408,7 @@ etiss_int64 semihostingCall(ETISS_CPU *const cpu, ETISS_System *const etissSyste
 
         cpu->exception = ETISS_RETURNCODE_CPUFINISHED;
         cpu->return_pending = 1;
+        return 0;
     }
     case SYS_ELAPSED:
     {

From 5deddeef57ec4bcd2813748e7eca7773308388ae Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 26 Aug 2022 00:19:56 +0200
Subject: [PATCH 11/44] update architecture

---
 ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp        |   3 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp | 200 +++----
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     |  48 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp | 385 +++++++-------
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     |  48 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp | 377 +++++++-------
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 226 ++++----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 486 ++++++++++--------
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp | 106 ++--
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |  15 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    |  80 +--
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    |  33 +-
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |  41 +-
 src/CPUCore.cpp                               |   1 -
 14 files changed, 1094 insertions(+), 955 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
index 3b5de6f014..fc3a70a5b1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -67,6 +67,7 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
 
 	if (startpointer) cpu->instructionPointer = *startpointer & ~((etiss::uint64)0x1);
 	else cpu->instructionPointer = 0x0;   //  reference to manual
+	cpu->nextPc = cpu->instructionPointer;
 	cpu->mode = 1;
 	cpu->cpuTime_ps = 0;
 	cpu->cpuCycleTime_ps = 31250;
@@ -258,4 +259,4 @@ etiss::instr::InstructionClass ISA16_RV32IMACFDClass(1, "ISA16_RV32IMACFD", 16,
 etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32);
 etiss::instr::InstructionClass ISA32_RV32IMACFDClass(1, "ISA32_RV32IMACFD", 32, ISA32_RV32IMACFD);
 
-etiss::instr::InstructionCollection RV32IMACFDISA("RV32IMACFDISA", ISA16_RV32IMACFDClass, ISA32_RV32IMACFDClass);
\ No newline at end of file
+etiss::instr::InstructionCollection RV32IMACFDISA("RV32IMACFDISA", ISA16_RV32IMACFDClass, ISA32_RV32IMACFDClass);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index 01701153d4..e75161ef5a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -28,19 +28,19 @@ static InstructionDefinition amoswapw_rd_rs1_rs2_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -62,7 +62,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e
 partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -77,19 +77,19 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -117,19 +117,19 @@ static InstructionDefinition amoaddw_rd_rs1_rs2_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -153,7 +153,7 @@ partInit.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::t
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -168,19 +168,19 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -208,19 +208,19 @@ static InstructionDefinition amoxorw_rd_rs1_rs2_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -244,7 +244,7 @@ partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::t
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -259,19 +259,19 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -299,19 +299,19 @@ static InstructionDefinition amoandw_rd_rs1_rs2_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -335,7 +335,7 @@ partInit.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::t
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -350,19 +350,19 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -390,19 +390,19 @@ static InstructionDefinition amoorw_rd_rs1_rs2_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -426,7 +426,7 @@ partInit.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::t
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -441,19 +441,19 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -481,19 +481,19 @@ static InstructionDefinition amominw_rd_rs1_rs2_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -517,7 +517,7 @@ partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -532,19 +532,19 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -572,19 +572,19 @@ static InstructionDefinition amomaxw_rd_rs1_rs2_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -608,7 +608,7 @@ partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -623,19 +623,19 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -663,19 +663,19 @@ static InstructionDefinition amominuw_rd_rs1_rs2_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -699,7 +699,7 @@ partInit.code() += "etiss_uint32 res2 = (res1 > *((RV32IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -714,19 +714,19 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -754,19 +754,19 @@ static InstructionDefinition amomaxuw_rd_rs1_rs2_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -790,7 +790,7 @@ partInit.code() += "etiss_uint32 res2 = (res1 < *((RV32IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -805,19 +805,19 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index a50efffde5..a5070252fd 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -28,13 +28,13 @@ static InstructionDefinition cfld_rd_uimm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(4, 2);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(6, 5);
 uimm += R_uimm_6.read(ba) << 6;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -54,6 +54,7 @@ partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, of
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -66,13 +67,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(4, 2);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(6, 5);
 uimm += R_uimm_6.read(ba) << 6;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -102,13 +103,13 @@ static InstructionDefinition cfsd_rs2_uimm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(6, 5);
 uimm += R_uimm_6.read(ba) << 6;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -126,7 +127,7 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -139,13 +140,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(6, 5);
 uimm += R_uimm_6.read(ba) << 6;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -175,12 +176,12 @@ static InstructionDefinition cfldsp_uimm_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 uimm = 0;
+etiss_uint16 uimm = 0;
 static BitArrayRange R_uimm_6(4, 2);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_3(6, 5);
 uimm += R_uimm_3.read(ba) << 3;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 static BitArrayRange R_uimm_5(12, 12);
@@ -200,6 +201,7 @@ partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, of
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -212,12 +214,12 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 uimm = 0;
+etiss_uint16 uimm = 0;
 static BitArrayRange R_uimm_6(4, 2);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_3(6, 5);
 uimm += R_uimm_3.read(ba) << 3;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 static BitArrayRange R_uimm_5(12, 12);
@@ -247,10 +249,10 @@ static InstructionDefinition cfsdsp_rs2_uimm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(6, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint16 uimm = 0;
 static BitArrayRange R_uimm_6(9, 7);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_3(12, 10);
@@ -268,7 +270,7 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -281,10 +283,10 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(6, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint16 uimm = 0;
 static BitArrayRange R_uimm_6(9, 7);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_3(12, 10);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index a253327e87..1d6c9d56e3 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -28,13 +28,13 @@ static InstructionDefinition fld_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -52,6 +52,7 @@ partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, of
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -64,13 +65,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -98,13 +99,13 @@ static InstructionDefinition fsd_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(11, 7);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(31, 25);
@@ -122,7 +123,7 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -135,13 +136,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(11, 7);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(31, 25);
@@ -171,19 +172,19 @@ static InstructionDefinition fmadd_d_rd_rm_rs1_rs2_rs3 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -199,6 +200,7 @@ partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -209,19 +211,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -249,19 +251,19 @@ static InstructionDefinition fmsub_d_rd_rm_rs1_rs2_rs3 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -277,6 +279,7 @@ partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -287,19 +290,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -327,19 +330,19 @@ static InstructionDefinition fnmadd_d_rd_rm_rs1_rs2_rs3 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -355,6 +358,7 @@ partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -365,19 +369,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -405,19 +409,19 @@ static InstructionDefinition fnmsub_d_rd_rm_rs1_rs2_rs3 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -433,6 +437,7 @@ partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -443,19 +448,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -483,16 +488,16 @@ static InstructionDefinition fadd_d_rd_rm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -508,6 +513,7 @@ partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)-
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -518,16 +524,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -555,16 +561,16 @@ static InstructionDefinition fsub_d_rd_rm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -580,6 +586,7 @@ partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)-
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -590,16 +597,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -627,16 +634,16 @@ static InstructionDefinition fmul_d_rd_rm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -652,6 +659,7 @@ partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)-
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -662,16 +670,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -699,16 +707,16 @@ static InstructionDefinition fdiv_d_rd_rm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -724,6 +732,7 @@ partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)-
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -734,16 +743,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -771,13 +780,13 @@ static InstructionDefinition fsqrt_d_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -793,6 +802,7 @@ partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -803,13 +813,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -837,13 +847,13 @@ static InstructionDefinition fsgnj_d_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -857,6 +867,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -867,13 +878,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -901,13 +912,13 @@ static InstructionDefinition fsgnjn_d_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -921,6 +932,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -931,13 +943,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -965,13 +977,13 @@ static InstructionDefinition fsgnjx_d_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -985,6 +997,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) & 9223372036854775808UL);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -995,13 +1008,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1029,13 +1042,13 @@ static InstructionDefinition fmin_d_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1051,6 +1064,7 @@ partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)-
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1061,13 +1075,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1095,13 +1109,13 @@ static InstructionDefinition fmax_d_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1117,6 +1131,7 @@ partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)-
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1127,13 +1142,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1161,13 +1176,13 @@ static InstructionDefinition fcvt_s_d_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1181,6 +1196,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L + res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1191,13 +1207,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1225,13 +1241,13 @@ static InstructionDefinition fcvt_d_s_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1245,6 +1261,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1255,13 +1272,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1289,13 +1306,13 @@ static InstructionDefinition feq_d_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1314,6 +1331,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1325,13 +1343,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1359,13 +1377,13 @@ static InstructionDefinition flt_d_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1384,6 +1402,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1395,13 +1414,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1429,13 +1448,13 @@ static InstructionDefinition fle_d_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1454,6 +1473,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1465,13 +1485,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1499,10 +1519,10 @@ static InstructionDefinition fclass_d_rd_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1515,6 +1535,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1526,10 +1547,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fc
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1557,13 +1578,13 @@ static InstructionDefinition fcvt_w_d_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1582,6 +1603,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1593,13 +1615,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1627,13 +1649,13 @@ static InstructionDefinition fcvt_wu_d_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1652,6 +1674,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1663,13 +1686,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1697,13 +1720,13 @@ static InstructionDefinition fcvt_d_w_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1717,6 +1740,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1728,13 +1752,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1762,13 +1786,13 @@ static InstructionDefinition fcvt_d_wu_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1782,6 +1806,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1793,13 +1818,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 51fad71407..61856fd673 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -28,15 +28,15 @@ static InstructionDefinition cflw_rd_uimm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(4, 2);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(5, 5);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 6);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -56,6 +56,7 @@ partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, of
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = -4294967296L | res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -68,15 +69,15 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(4, 2);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(5, 5);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 6);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -106,15 +107,15 @@ static InstructionDefinition cfsw_rs2_uimm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(5, 5);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 6);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -132,7 +133,7 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -145,15 +146,15 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(5, 5);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 6);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -183,12 +184,12 @@ static InstructionDefinition cflwsp_uimm_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(3, 2);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 4);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 static BitArrayRange R_uimm_5(12, 12);
@@ -208,6 +209,7 @@ partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, of
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -220,12 +222,12 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(3, 2);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 4);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 static BitArrayRange R_uimm_5(12, 12);
@@ -255,10 +257,10 @@ static InstructionDefinition cfswsp_rs2_uimm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(6, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(8, 7);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(12, 9);
@@ -276,7 +278,7 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -289,10 +291,10 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(6, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(8, 7);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(12, 9);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 63f58e3a45..08e0c5622a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -28,13 +28,13 @@ static InstructionDefinition flw_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -52,6 +52,7 @@ partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, of
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -64,13 +65,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -98,13 +99,13 @@ static InstructionDefinition fsw_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(11, 7);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(31, 25);
@@ -122,7 +123,7 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -135,13 +136,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(11, 7);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(31, 25);
@@ -171,19 +172,19 @@ static InstructionDefinition fmadd_s_rd_rm_rs1_rs2_rs3 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -199,6 +200,7 @@ partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" +
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -209,19 +211,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -249,19 +251,19 @@ static InstructionDefinition fmsub_s_rd_rm_rs1_rs2_rs3 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -277,6 +279,7 @@ partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" +
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -287,19 +290,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -327,19 +330,19 @@ static InstructionDefinition fnmadd_s_rd_rm_rs1_rs2_rs3 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -358,6 +361,7 @@ partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::t
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -368,19 +372,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -408,19 +412,19 @@ static InstructionDefinition fnmsub_s_rd_rm_rs1_rs2_rs3 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -439,6 +443,7 @@ partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::t
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -449,19 +454,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rs3 = 0;
+etiss_uint8 rs3 = 0;
 static BitArrayRange R_rs3_0(31, 27);
 rs3 += R_rs3_0.read(ba) << 0;
 
@@ -489,16 +494,16 @@ static InstructionDefinition fadd_s_rd_rm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -516,6 +521,7 @@ partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -526,16 +532,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -563,16 +569,16 @@ static InstructionDefinition fsub_s_rd_rm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -590,6 +596,7 @@ partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -600,16 +607,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -637,16 +644,16 @@ static InstructionDefinition fmul_s_rd_rm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -664,6 +671,7 @@ partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -674,16 +682,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -711,16 +719,16 @@ static InstructionDefinition fdiv_s_rd_rm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -738,6 +746,7 @@ partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -748,16 +757,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -785,13 +794,13 @@ static InstructionDefinition fsqrt_s_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -808,6 +817,7 @@ partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -818,13 +828,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -852,13 +862,13 @@ static InstructionDefinition fsgnj_s_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -874,6 +884,7 @@ partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::t
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -884,13 +895,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -918,13 +929,13 @@ static InstructionDefinition fsgnjn_s_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -940,6 +951,7 @@ partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::t
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -950,13 +962,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -984,13 +996,13 @@ static InstructionDefinition fsgnjx_s_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1006,6 +1018,7 @@ partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::t
 partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
 partInit.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1016,13 +1029,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1050,13 +1063,13 @@ static InstructionDefinition fmin_s_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1074,6 +1087,7 @@ partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1084,13 +1098,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1118,13 +1132,13 @@ static InstructionDefinition fmax_s_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1142,6 +1156,7 @@ partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1152,13 +1167,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1186,13 +1201,13 @@ static InstructionDefinition fcvt_w_s_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1212,6 +1227,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1223,13 +1239,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1257,13 +1273,13 @@ static InstructionDefinition fcvt_wu_s_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1283,6 +1299,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1294,13 +1311,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1328,13 +1345,13 @@ static InstructionDefinition feq_s_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1355,6 +1372,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1366,13 +1384,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1400,13 +1418,13 @@ static InstructionDefinition flt_s_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1427,6 +1445,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1438,13 +1457,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1472,13 +1491,13 @@ static InstructionDefinition fle_s_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1499,6 +1518,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1510,13 +1530,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32)
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -1544,10 +1564,10 @@ static InstructionDefinition fclass_s_rd_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1564,6 +1584,7 @@ partInit.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_str
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1575,10 +1596,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1606,13 +1627,13 @@ static InstructionDefinition fcvt_s_w_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1626,6 +1647,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1637,13 +1659,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1671,13 +1693,13 @@ static InstructionDefinition fcvt_s_wu_rd_rm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1691,6 +1713,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1702,13 +1725,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rm = 0;
+etiss_uint8 rm = 0;
 static BitArrayRange R_rm_0(14, 12);
 rm += R_rm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1736,10 +1759,10 @@ static InstructionDefinition fmv_x_w_rd_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1754,6 +1777,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "];\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1765,10 +1789,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1796,10 +1820,10 @@ static InstructionDefinition fmv_w_x_rd_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1812,6 +1836,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1823,10 +1848,10 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index e3d4372b22..10499827b0 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -28,10 +28,10 @@ static InstructionDefinition caddi4spn_rd_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(4, 2);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_3(5, 5);
 imm += R_imm_3.read(ba) << 3;
 static BitArrayRange R_imm_2(6, 6);
@@ -54,6 +54,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *(
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -67,10 +68,10 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(4, 2);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_3(5, 5);
 imm += R_imm_3.read(ba) << 3;
 static BitArrayRange R_imm_2(6, 6);
@@ -104,15 +105,15 @@ static InstructionDefinition clw_rd_uimm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(4, 2);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(5, 5);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 6);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -131,6 +132,7 @@ partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_int32)(mem_val_0);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -144,15 +146,15 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(4, 2);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(5, 5);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 6);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -182,15 +184,15 @@ static InstructionDefinition csw_rs2_uimm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(5, 5);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 6);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -208,7 +210,7 @@ partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -222,15 +224,15 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(5, 5);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 6);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_uimm_3(12, 10);
@@ -260,10 +262,10 @@ static InstructionDefinition caddi_imm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint8 imm = 0;
 static BitArrayRange R_imm_0(6, 2);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(11, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_imm_5(12, 12);
@@ -280,6 +282,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if ((rs1 % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -292,10 +295,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint8 imm = 0;
 static BitArrayRange R_imm_0(6, 2);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(11, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_imm_5(12, 12);
@@ -325,7 +328,7 @@ static InstructionDefinition cnop_nzimm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 nzimm = 0;
+etiss_uint8 nzimm = 0;
 static BitArrayRange R_nzimm_0(6, 2);
 nzimm += R_nzimm_0.read(ba) << 0;
 static BitArrayRange R_nzimm_5(12, 12);
@@ -339,6 +342,7 @@ nzimm += R_nzimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -349,7 +353,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 nzimm = 0;
+etiss_uint8 nzimm = 0;
 static BitArrayRange R_nzimm_0(6, 2);
 nzimm += R_nzimm_0.read(ba) << 0;
 static BitArrayRange R_nzimm_5(12, 12);
@@ -379,7 +383,7 @@ static InstructionDefinition cjal_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_5(2, 2);
 imm += R_imm_5.read(ba) << 5;
 static BitArrayRange R_imm_1(5, 3);
@@ -407,6 +411,7 @@ imm += R_imm_11.read(ba) << 11;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -419,7 +424,7 @@ partInit.code() += "return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_5(2, 2);
 imm += R_imm_5.read(ba) << 5;
 static BitArrayRange R_imm_1(5, 3);
@@ -461,10 +466,10 @@ static InstructionDefinition cli_imm_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint8 imm = 0;
 static BitArrayRange R_imm_0(6, 2);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 static BitArrayRange R_imm_5(12, 12);
@@ -481,6 +486,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -492,10 +498,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = "
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint8 imm = 0;
 static BitArrayRange R_imm_0(6, 2);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 static BitArrayRange R_imm_5(12, 12);
@@ -528,7 +534,7 @@ static InstructionDefinition clui_imm_rd (
 etiss_uint32 imm = 0;
 static BitArrayRange R_imm_12(6, 2);
 imm += R_imm_12.read(ba) << 12;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 static BitArrayRange R_imm_17(12, 12);
@@ -548,6 +554,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U)
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -563,7 +570,7 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 etiss_uint32 imm = 0;
 static BitArrayRange R_imm_12(6, 2);
 imm += R_imm_12.read(ba) << 12;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 static BitArrayRange R_imm_17(12, 12);
@@ -593,7 +600,7 @@ static InstructionDefinition caddi16sp_nzimm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 nzimm = 0;
+etiss_uint16 nzimm = 0;
 static BitArrayRange R_nzimm_5(2, 2);
 nzimm += R_nzimm_5.read(ba) << 5;
 static BitArrayRange R_nzimm_7(4, 3);
@@ -618,6 +625,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[2U] = *((RV32IMACFD*)cpu)->X[2U] + "
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -631,7 +639,7 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 nzimm = 0;
+etiss_uint16 nzimm = 0;
 static BitArrayRange R_nzimm_5(2, 2);
 nzimm += R_nzimm_5.read(ba) << 5;
 static BitArrayRange R_nzimm_7(4, 3);
@@ -667,7 +675,7 @@ static InstructionDefinition __reserved_clui_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -680,6 +688,7 @@ rd += R_rd_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -691,7 +700,7 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -719,10 +728,10 @@ static InstructionDefinition csrli_shamt_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 shamt = 0;
+etiss_uint8 shamt = 0;
 static BitArrayRange R_shamt_0(6, 2);
 shamt += R_shamt_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -735,6 +744,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -747,10 +757,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 shamt = 0;
+etiss_uint8 shamt = 0;
 static BitArrayRange R_shamt_0(6, 2);
 shamt += R_shamt_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -778,10 +788,10 @@ static InstructionDefinition csrai_shamt_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 shamt = 0;
+etiss_uint8 shamt = 0;
 static BitArrayRange R_shamt_0(6, 2);
 shamt += R_shamt_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -796,6 +806,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if (shamt) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> " + std::to_string(shamt) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -808,10 +819,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = (
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 shamt = 0;
+etiss_uint8 shamt = 0;
 static BitArrayRange R_shamt_0(6, 2);
 shamt += R_shamt_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -839,10 +850,10 @@ static InstructionDefinition candi_imm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint8 imm = 0;
 static BitArrayRange R_imm_0(6, 2);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_imm_5(12, 12);
@@ -857,6 +868,7 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -869,10 +881,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint8 imm = 0;
 static BitArrayRange R_imm_0(6, 2);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_imm_5(12, 12);
@@ -902,10 +914,10 @@ static InstructionDefinition csub_rs2_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(9, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -918,6 +930,7 @@ rd += R_rd_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32);
@@ -931,10 +944,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(9, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -962,10 +975,10 @@ static InstructionDefinition cxor_rs2_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(9, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -978,6 +991,7 @@ rd += R_rd_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32);
@@ -991,10 +1005,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(9, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -1022,10 +1036,10 @@ static InstructionDefinition cor_rs2_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(9, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -1038,6 +1052,7 @@ rd += R_rd_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32);
@@ -1051,10 +1066,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(9, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -1082,10 +1097,10 @@ static InstructionDefinition cand_rs2_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(9, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -1098,6 +1113,7 @@ rd += R_rd_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32);
@@ -1111,10 +1127,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(4, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(9, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -1142,7 +1158,7 @@ static InstructionDefinition cj_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_5(2, 2);
 imm += R_imm_5.read(ba) << 5;
 static BitArrayRange R_imm_1(5, 3);
@@ -1169,6 +1185,7 @@ imm += R_imm_11.read(ba) << 11;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1180,7 +1197,7 @@ partInit.code() += "return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_5(2, 2);
 imm += R_imm_5.read(ba) << 5;
 static BitArrayRange R_imm_1(5, 3);
@@ -1222,14 +1239,14 @@ static InstructionDefinition cbeqz_imm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_5(2, 2);
 imm += R_imm_5.read(ba) << 5;
 static BitArrayRange R_imm_1(4, 3);
 imm += R_imm_1.read(ba) << 1;
 static BitArrayRange R_imm_6(6, 5);
 imm += R_imm_6.read(ba) << 6;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_imm_3(11, 10);
@@ -1248,6 +1265,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] == 0U) {\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
 partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1260,14 +1278,14 @@ partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ +
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_5(2, 2);
 imm += R_imm_5.read(ba) << 5;
 static BitArrayRange R_imm_1(4, 3);
 imm += R_imm_1.read(ba) << 1;
 static BitArrayRange R_imm_6(6, 5);
 imm += R_imm_6.read(ba) << 6;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_imm_3(11, 10);
@@ -1299,14 +1317,14 @@ static InstructionDefinition cbnez_imm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_5(2, 2);
 imm += R_imm_5.read(ba) << 5;
 static BitArrayRange R_imm_1(4, 3);
 imm += R_imm_1.read(ba) << 1;
 static BitArrayRange R_imm_6(6, 5);
 imm += R_imm_6.read(ba) << 6;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_imm_3(11, 10);
@@ -1325,6 +1343,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] != 0U) {\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
 partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1337,14 +1356,14 @@ partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ +
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_5(2, 2);
 imm += R_imm_5.read(ba) << 5;
 static BitArrayRange R_imm_1(4, 3);
 imm += R_imm_1.read(ba) << 1;
 static BitArrayRange R_imm_6(6, 5);
 imm += R_imm_6.read(ba) << 6;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(9, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 static BitArrayRange R_imm_3(11, 10);
@@ -1376,10 +1395,10 @@ static InstructionDefinition cslli_nzuimm_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 nzuimm = 0;
+etiss_uint8 nzuimm = 0;
 static BitArrayRange R_nzuimm_0(6, 2);
 nzuimm += R_nzuimm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(11, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1394,6 +1413,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if (nzuimm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(nzuimm) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1406,10 +1426,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 nzuimm = 0;
+etiss_uint8 nzuimm = 0;
 static BitArrayRange R_nzuimm_0(6, 2);
 nzuimm += R_nzuimm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(11, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1437,12 +1457,12 @@ static InstructionDefinition clwsp_uimm_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(3, 2);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 4);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 static BitArrayRange R_uimm_5(12, 12);
@@ -1466,6 +1486,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1479,12 +1500,12 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(3, 2);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(6, 4);
 uimm += R_uimm_2.read(ba) << 2;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 static BitArrayRange R_uimm_5(12, 12);
@@ -1514,10 +1535,10 @@ static InstructionDefinition cmv_rs2_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(6, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -1532,6 +1553,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
@@ -1544,10 +1566,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(6, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -1575,7 +1597,7 @@ static InstructionDefinition cjr_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(11, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1592,6 +1614,7 @@ partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1
 } else {
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1604,7 +1627,7 @@ partInit.code() += "return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(11, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1642,6 +1665,7 @@ static InstructionDefinition __reserved_cmv_ (
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1678,10 +1702,10 @@ static InstructionDefinition cadd_rs2_rd (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(6, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -1696,6 +1720,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rd % 32U], 32);
@@ -1709,10 +1734,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(6, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 
@@ -1740,7 +1765,7 @@ static InstructionDefinition cjalr_rs1 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(11, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1755,6 +1780,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 partInit.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->nextPc = new_pc & -2;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1768,7 +1794,7 @@ partInit.code() += "return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(11, 7);
 rs1 += R_rs1_0.read(ba) << 0;
 
@@ -1806,6 +1832,7 @@ static InstructionDefinition cebreak_ (
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1842,10 +1869,10 @@ static InstructionDefinition cswsp_rs2_uimm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(6, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(8, 7);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(12, 9);
@@ -1863,7 +1890,7 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1877,10 +1904,10 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(6, 2);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 uimm = 0;
+etiss_uint8 uimm = 0;
 static BitArrayRange R_uimm_6(8, 7);
 uimm += R_uimm_6.read(ba) << 6;
 static BitArrayRange R_uimm_2(12, 9);
@@ -1920,6 +1947,7 @@ static InstructionDefinition dii_ (
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 1de17e0601..6664102cdb 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -28,7 +28,7 @@ static InstructionDefinition lui_rd_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 etiss_uint32 imm = 0;
@@ -46,6 +46,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string((etiss_int32)(imm)) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -57,7 +58,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = "
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 etiss_uint32 imm = 0;
@@ -88,7 +89,7 @@ static InstructionDefinition auipc_rd_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 etiss_uint32 imm = 0;
@@ -106,6 +107,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -117,7 +119,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = "
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 etiss_uint32 imm = 0;
@@ -148,7 +150,7 @@ static InstructionDefinition jal_rd_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 etiss_uint32 imm = 0;
@@ -177,6 +179,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = "
 }
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -189,7 +192,7 @@ partInit.code() += "return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
 etiss_uint32 imm = 0;
@@ -226,13 +229,13 @@ static InstructionDefinition jalr_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -254,6 +257,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = "
 }
 partInit.code() += "cpu->nextPc = new_pc & -2;\n";
 partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -267,13 +271,13 @@ partInit.code() += "return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -301,15 +305,15 @@ static InstructionDefinition beq_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -332,6 +336,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -345,15 +350,15 @@ partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -385,15 +390,15 @@ static InstructionDefinition bne_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -416,6 +421,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -429,15 +435,15 @@ partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -469,15 +475,15 @@ static InstructionDefinition blt_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -500,6 +506,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -513,15 +520,15 @@ partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -553,15 +560,15 @@ static InstructionDefinition bge_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -584,6 +591,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -597,15 +605,15 @@ partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -637,15 +645,15 @@ static InstructionDefinition bltu_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -668,6 +676,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -681,15 +690,15 @@ partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -721,15 +730,15 @@ static InstructionDefinition bgeu_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -752,6 +761,7 @@ partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U)
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -765,15 +775,15 @@ partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_11(7, 7);
 imm += R_imm_11.read(ba) << 11;
 static BitArrayRange R_imm_1(11, 8);
 imm += R_imm_1.read(ba) << 1;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(30, 25);
@@ -805,13 +815,13 @@ static InstructionDefinition lb_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -831,6 +841,7 @@ partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -844,13 +855,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -878,13 +889,13 @@ static InstructionDefinition lh_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -904,6 +915,7 @@ partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -917,13 +929,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -951,13 +963,13 @@ static InstructionDefinition lw_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -977,6 +989,7 @@ partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -990,13 +1003,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1024,13 +1037,13 @@ static InstructionDefinition lbu_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1050,6 +1063,7 @@ partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1063,13 +1077,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1097,13 +1111,13 @@ static InstructionDefinition lhu_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1123,6 +1137,7 @@ partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1136,13 +1151,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1170,13 +1185,13 @@ static InstructionDefinition sb_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(11, 7);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(31, 25);
@@ -1194,7 +1209,7 @@ partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std:
 partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1208,13 +1223,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(11, 7);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(31, 25);
@@ -1244,13 +1259,13 @@ static InstructionDefinition sh_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(11, 7);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(31, 25);
@@ -1268,7 +1283,7 @@ partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std:
 partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1282,13 +1297,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(11, 7);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(31, 25);
@@ -1318,13 +1333,13 @@ static InstructionDefinition sw_imm_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(11, 7);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(31, 25);
@@ -1342,7 +1357,7 @@ partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std:
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -1356,13 +1371,13 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(11, 7);
 imm += R_imm_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 static BitArrayRange R_imm_5(31, 25);
@@ -1392,13 +1407,13 @@ static InstructionDefinition addi_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1413,6 +1428,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1425,13 +1441,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1459,13 +1475,13 @@ static InstructionDefinition slti_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1480,6 +1496,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1492,13 +1509,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1526,13 +1543,13 @@ static InstructionDefinition sltiu_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1547,6 +1564,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ")) ? (1U) : (0U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1559,13 +1577,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1593,13 +1611,13 @@ static InstructionDefinition xori_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1614,6 +1632,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1626,13 +1645,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1660,13 +1679,13 @@ static InstructionDefinition ori_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1681,6 +1700,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1693,13 +1713,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1727,13 +1747,13 @@ static InstructionDefinition andi_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1748,6 +1768,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1760,13 +1781,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -1794,13 +1815,13 @@ static InstructionDefinition slli_rd_rs1_shamt (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 shamt = 0;
+etiss_uint8 shamt = 0;
 static BitArrayRange R_shamt_0(24, 20);
 shamt += R_shamt_0.read(ba) << 0;
 
@@ -1815,6 +1836,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(shamt) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1827,13 +1849,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 shamt = 0;
+etiss_uint8 shamt = 0;
 static BitArrayRange R_shamt_0(24, 20);
 shamt += R_shamt_0.read(ba) << 0;
 
@@ -1861,13 +1883,13 @@ static InstructionDefinition srli_rd_rs1_shamt (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 shamt = 0;
+etiss_uint8 shamt = 0;
 static BitArrayRange R_shamt_0(24, 20);
 shamt += R_shamt_0.read(ba) << 0;
 
@@ -1882,6 +1904,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> " + std::to_string(shamt) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1894,13 +1917,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 shamt = 0;
+etiss_uint8 shamt = 0;
 static BitArrayRange R_shamt_0(24, 20);
 shamt += R_shamt_0.read(ba) << 0;
 
@@ -1928,13 +1951,13 @@ static InstructionDefinition srai_rd_rs1_shamt (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 shamt = 0;
+etiss_uint8 shamt = 0;
 static BitArrayRange R_shamt_0(24, 20);
 shamt += R_shamt_0.read(ba) << 0;
 
@@ -1949,6 +1972,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> " + std::to_string(shamt) + ";\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1961,13 +1985,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 shamt = 0;
+etiss_uint8 shamt = 0;
 static BitArrayRange R_shamt_0(24, 20);
 shamt += R_shamt_0.read(ba) << 0;
 
@@ -1995,13 +2019,13 @@ static InstructionDefinition add_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2016,6 +2040,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2029,13 +2054,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2063,13 +2088,13 @@ static InstructionDefinition sub_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2084,6 +2109,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2097,13 +2123,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2131,13 +2157,13 @@ static InstructionDefinition sll_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2152,6 +2178,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2165,13 +2192,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2199,13 +2226,13 @@ static InstructionDefinition slt_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2220,6 +2247,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2233,13 +2261,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2267,13 +2295,13 @@ static InstructionDefinition sltu_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2288,6 +2316,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2301,13 +2330,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2335,13 +2364,13 @@ static InstructionDefinition xor_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2356,6 +2385,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2369,13 +2399,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2403,13 +2433,13 @@ static InstructionDefinition srl_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2424,6 +2454,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2437,13 +2468,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2471,13 +2502,13 @@ static InstructionDefinition sra_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2492,6 +2523,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2505,13 +2537,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2539,13 +2571,13 @@ static InstructionDefinition or_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2560,6 +2592,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2573,13 +2606,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2607,13 +2640,13 @@ static InstructionDefinition and_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2628,6 +2661,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -2641,13 +2675,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *(
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -2675,19 +2709,19 @@ static InstructionDefinition fence_rd_rs1_succ_pred_fm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 succ = 0;
+etiss_uint8 succ = 0;
 static BitArrayRange R_succ_0(23, 20);
 succ += R_succ_0.read(ba) << 0;
-etiss_uint32 pred = 0;
+etiss_uint8 pred = 0;
 static BitArrayRange R_pred_0(27, 24);
 pred += R_pred_0.read(ba) << 0;
-etiss_uint32 fm = 0;
+etiss_uint8 fm = 0;
 static BitArrayRange R_fm_0(31, 28);
 fm += R_fm_0.read(ba) << 0;
 
@@ -2700,6 +2734,7 @@ fm += R_fm_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(0) + "] = " + std::to_string(pred << 4U | succ) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -2710,19 +2745,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(0) + "] = " + s
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 succ = 0;
+etiss_uint8 succ = 0;
 static BitArrayRange R_succ_0(23, 20);
 succ += R_succ_0.read(ba) << 0;
-etiss_uint32 pred = 0;
+etiss_uint8 pred = 0;
 static BitArrayRange R_pred_0(27, 24);
 pred += R_pred_0.read(ba) << 0;
-etiss_uint32 fm = 0;
+etiss_uint8 fm = 0;
 static BitArrayRange R_fm_0(31, 28);
 fm += R_fm_0.read(ba) << 0;
 
@@ -2760,6 +2795,7 @@ static InstructionDefinition ecall_ (
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -2806,6 +2842,7 @@ static InstructionDefinition ebreak_ (
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -2852,6 +2889,7 @@ static InstructionDefinition wfi_ (
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "cpu->exception = ETISS_RETURNCODE_CPUFINISHED;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index a3f8ede992..27afcb250a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 19:26:52 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
@@ -28,13 +28,13 @@ static InstructionDefinition mul_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -50,6 +50,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -63,13 +64,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -97,13 +98,13 @@ static InstructionDefinition mulh_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -119,6 +120,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -132,13 +134,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -166,13 +168,13 @@ static InstructionDefinition mulhsu_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -188,6 +190,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -201,13 +204,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -235,13 +238,13 @@ static InstructionDefinition mulhu_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -257,6 +260,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -270,13 +274,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -304,13 +308,13 @@ static InstructionDefinition div_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -336,6 +340,7 @@ partInit.code() += " else {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1;\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -349,13 +354,13 @@ partInit.code() += "}\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -383,13 +388,13 @@ static InstructionDefinition divu_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -409,6 +414,7 @@ partInit.code() += " else {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1;\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -422,13 +428,13 @@ partInit.code() += "}\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -456,13 +462,13 @@ static InstructionDefinition rem_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -488,6 +494,7 @@ partInit.code() += " else {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -501,13 +508,13 @@ partInit.code() += "}\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -535,13 +542,13 @@ static InstructionDefinition remu_rd_rs1_rs2 (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
@@ -561,6 +568,7 @@ partInit.code() += " else {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -574,13 +582,13 @@ partInit.code() += "}\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index 0d49e2c9c6..eaf6234b81 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
@@ -28,13 +28,13 @@ static InstructionDefinition fence_i_rd_rs1_imm (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
@@ -48,6 +48,7 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(1) + "] = " + std::to_string(imm) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -59,13 +60,13 @@ partInit.code() += "return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 imm = 0;
+etiss_uint16 imm = 0;
 static BitArrayRange R_imm_0(31, 20);
 imm += R_imm_0.read(ba) << 0;
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index eb766fa976..52cdf6c3de 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
@@ -28,13 +28,13 @@ static InstructionDefinition csrrw_rd_rs1_csr (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -54,6 +54,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr
 } else {
 partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -66,13 +67,13 @@ partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(c
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -100,13 +101,13 @@ static InstructionDefinition csrrs_rd_rs1_csr (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -126,6 +127,7 @@ partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(c
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -138,13 +140,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -172,13 +174,13 @@ static InstructionDefinition csrrc_rd_rs1_csr (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -198,6 +200,7 @@ partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(c
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -210,13 +213,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -244,13 +247,13 @@ static InstructionDefinition csrrwi_rd_zimm_csr (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 zimm = 0;
+etiss_uint8 zimm = 0;
 static BitArrayRange R_zimm_0(19, 15);
 zimm += R_zimm_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -267,6 +270,7 @@ partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(c
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -278,13 +282,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 zimm = 0;
+etiss_uint8 zimm = 0;
 static BitArrayRange R_zimm_0(19, 15);
 zimm += R_zimm_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -312,13 +316,13 @@ static InstructionDefinition csrrsi_rd_zimm_csr (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 zimm = 0;
+etiss_uint8 zimm = 0;
 static BitArrayRange R_zimm_0(19, 15);
 zimm += R_zimm_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -337,6 +341,7 @@ partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(c
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -348,13 +353,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 zimm = 0;
+etiss_uint8 zimm = 0;
 static BitArrayRange R_zimm_0(19, 15);
 zimm += R_zimm_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -382,13 +387,13 @@ static InstructionDefinition csrrci_rd_zimm_csr (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 zimm = 0;
+etiss_uint8 zimm = 0;
 static BitArrayRange R_zimm_0(19, 15);
 zimm += R_zimm_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
@@ -407,6 +412,7 @@ partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(c
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -418,13 +424,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 zimm = 0;
+etiss_uint8 zimm = 0;
 static BitArrayRange R_zimm_0(19, 15);
 zimm += R_zimm_0.read(ba) << 0;
-etiss_uint32 csr = 0;
+etiss_uint16 csr = 0;
 static BitArrayRange R_csr_0(31, 20);
 csr += R_csr_0.read(ba) << 0;
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index b87430c1f0..6aecf336cc 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 18 Jul 2022 21:37:38 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
@@ -37,12 +37,13 @@ static InstructionDefinition mret_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[768U] & 6144U) >> 11U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[768U] ^ (*((RV32IMACFD*)cpu)->CSR[768U] & 6144U);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[768U] ^ ((*((RV32IMACFD*)cpu)->CSR[768U] & 128U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[768U] & 8U);\n";
-partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[768U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[768U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[768] & 6144U) >> 11U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768] = *((RV32IMACFD*)cpu)->CSR[768] ^ (*((RV32IMACFD*)cpu)->CSR[768] & 6144U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768] = *((RV32IMACFD*)cpu)->CSR[768] ^ ((*((RV32IMACFD*)cpu)->CSR[768] & 128U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[768] & 8U);\n";
+partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[768];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256) + "] = *((RV32IMACFD*)cpu)->CSR[768];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -91,8 +92,9 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = 0U;\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[0U] ^ ((*((RV32IMACFD*)cpu)->CSR[0U] & 16U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[0U] & 1U);\n";
 partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[65U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768) + "] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256) + "] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -138,12 +140,13 @@ static InstructionDefinition sret_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[256U] & 256U) >> 8U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[256U] ^ (*((RV32IMACFD*)cpu)->CSR[256U] & 256U);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256U] = *((RV32IMACFD*)cpu)->CSR[256U] ^ ((*((RV32IMACFD*)cpu)->CSR[256U] & 32U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[256U] & 2U);\n";
-partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768U] = *((RV32IMACFD*)cpu)->CSR[256U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[256U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[256] & 256U) >> 8U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256] = *((RV32IMACFD*)cpu)->CSR[256] ^ (*((RV32IMACFD*)cpu)->CSR[256] & 256U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256] = *((RV32IMACFD*)cpu)->CSR[256] ^ ((*((RV32IMACFD*)cpu)->CSR[256] & 32U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[256] & 2U);\n";
+partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768) + "] = *((RV32IMACFD*)cpu)->CSR[256];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[256];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 7a805fa5d1..328da999cf 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -28,16 +28,16 @@ static InstructionDefinition lrw_rd_rs1_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -58,6 +58,7 @@ partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";
 if (rd) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 }
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -71,16 +72,16 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -108,19 +109,19 @@ static InstructionDefinition scw_rd_rs1_rs2_rl_aq (
 // -----------------------------------------------------------------------------
 
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
@@ -137,12 +138,12 @@ partInit.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) {\n";
 partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-
 partInit.code() += "}\n";
 if (rd) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
 }
 partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
@@ -157,19 +158,19 @@ partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 	[] (BitArray & ba, Instruction & instr)
 	{
 // -----------------------------------------------------------------------------
-etiss_uint32 rd = 0;
+etiss_uint8 rd = 0;
 static BitArrayRange R_rd_0(11, 7);
 rd += R_rd_0.read(ba) << 0;
-etiss_uint32 rs1 = 0;
+etiss_uint8 rs1 = 0;
 static BitArrayRange R_rs1_0(19, 15);
 rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint32 rs2 = 0;
+etiss_uint8 rs2 = 0;
 static BitArrayRange R_rs2_0(24, 20);
 rs2 += R_rs2_0.read(ba) << 0;
-etiss_uint32 rl = 0;
+etiss_uint8 rl = 0;
 static BitArrayRange R_rl_0(25, 25);
 rl += R_rl_0.read(ba) << 0;
-etiss_uint32 aq = 0;
+etiss_uint8 aq = 0;
 static BitArrayRange R_aq_0(26, 26);
 aq += R_aq_0.read(ba) << 0;
 
diff --git a/src/CPUCore.cpp b/src/CPUCore.cpp
index 3d86f00199..fd8746e4ea 100644
--- a/src/CPUCore.cpp
+++ b/src/CPUCore.cpp
@@ -789,7 +789,6 @@ etiss::int32 CPUCore::execute(ETISS_System &_system)
                     // In the generated code these plugin handles are named "plugin_pointers" and can be used to access
                     // a variable of the plugin
                     exception = (*(blptr->execBlock))(cpu_, system, plugins_handle_);
-                    cpu_->instructionPointer = cpu_->nextPc;
 
                     // exit simulator when a loop to self instruction is encountered
                     if (!exception &&

From 765e56a9907b368fefa78f46703def0589082879 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 4 Nov 2022 11:04:59 +0100
Subject: [PATCH 12/44] add 128 bit int types

---
 include_c/etiss/jit/types.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include_c/etiss/jit/types.h b/include_c/etiss/jit/types.h
index ec21d48a95..59993c7ef9 100644
--- a/include_c/etiss/jit/types.h
+++ b/include_c/etiss/jit/types.h
@@ -98,6 +98,11 @@ extern "C"
     typedef etiss_int64 etiss_intMax;
     typedef etiss_uint64 etiss_uintMax;
 
+#ifdef __GNUC__
+    typedef __int128_t etiss_int128;
+    typedef __uint128_t etiss_uint128;
+#endif
+
 #ifdef __cplusplus
 }
 #endif
@@ -121,6 +126,11 @@ typedef etiss_uint64 uint64;
 typedef etiss_intMax intMax;
 typedef etiss_uintMax uintMax;
 
+#ifdef __GNUC__
+typedef __int128_t etiss_int128;
+typedef __uint128_t etiss_uint128;
+#endif
+
 } // namespace etiss
 #endif
 

From 4e6f779b2ae3bbaee6be1be0243baba8e69a3997 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 4 Nov 2022 11:05:46 +0100
Subject: [PATCH 13/44] add decoding exceptions

---
 src/Translation.cpp | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/Translation.cpp b/src/Translation.cpp
index 2a630d2712..fa3f93c8fb 100644
--- a/src/Translation.cpp
+++ b/src/Translation.cpp
@@ -473,18 +473,19 @@ etiss::int32 Translation::translateBlock(CodeBlock &cb)
         context.is_not_default_width_ = false;
         context.instr_width_ = vis_->width_;
 
+        etiss::instr::BitArray errba(32, 0);
+
         // read instruction
         etiss::int32 ret = (*system_.dbg_read)(system_.handle, cb.endaddress_, (etiss_uint8 *)mainba.internalBuffer(),
                                                mainba.byteCount()); // read instruction
-        if (ret == etiss::RETURNCODE::IBUS_READ_ERROR)
+        if (ret == etiss::RETURNCODE::IBUS_READ_ERROR || ret == etiss::RETURNCODE::DBUS_READ_ERROR)
         {
             std::cout << "Instruction bus read error while translating!" << std::endl;
-            CodeBlock::Line &line = cb.append(cb.endaddress_); // allocate codeSet for Instruction
-            line.getCodeSet().append(CodePart::PREINITIALDEBUGRETURNING).code() =
-                std::string("cpu->cpuTime_ps += "
-                            "cpu->cpuCycleTime_ps;cpu->instructionPointer += ") +
-                std::to_string(mainba.byteCount()) + std::string(";return ETISS_RETURNCODE_IBUS_READ_ERROR;");
+            errba = etiss::RETURNCODE::IBUS_READ_ERROR;
             // std::cout << "mainba.byteCount = " << mainba.byteCount() << std::endl;
+            auto instr = &vis_->getMain()->getInvalid();
+            CodeBlock::Line &line = cb.append(cb.endaddress_); // allocate codeset for instruction
+            bool ok = instr->translate(errba, line.getCodeSet(), context);
             cb.endaddress_ += mainba.byteCount(); // update end address
             return etiss::RETURNCODE::NOERROR;
         }
@@ -537,6 +538,7 @@ etiss::int32 Translation::translateBlock(CodeBlock &cb)
             etiss::instr::InstructionSet *instrSet = vis_->get(secba->width());
             if (unlikely(!instrSet))
             {
+                errba = etiss::RETURNCODE::ILLEGALINSTRUCTION;
                 instr = &vis_->getMain()->getInvalid();
             }
             else
@@ -544,11 +546,12 @@ etiss::int32 Translation::translateBlock(CodeBlock &cb)
                 instr = instrSet->resolve(*secba);
                 if (unlikely(!instr))
                 {
+                    errba = etiss::RETURNCODE::ILLEGALINSTRUCTION;
                     instr = &instrSet->getInvalid();
                 }
             }
             CodeBlock::Line &line = cb.append(cb.endaddress_); // allocate codeset for instruction
-            bool ok = instr->translate(*secba, line.getCodeSet(), context);
+            bool ok = instr->translate(errba != etiss::instr::BitArray(32, 0) ? errba : *secba, line.getCodeSet(), context);
             if (unlikely(!ok))
             {
                 delete secba;
@@ -563,10 +566,11 @@ etiss::int32 Translation::translateBlock(CodeBlock &cb)
             etiss::instr::Instruction *instr = instrSet->resolve(mainba);
             if (unlikely(instr == 0))
             {
+                errba = etiss::RETURNCODE::ILLEGALINSTRUCTION;
                 instr = &instrSet->getInvalid();
             }
             CodeBlock::Line &line = cb.append(cb.endaddress_); // allocate codeset for instruction
-            bool ok = instr->translate(mainba, line.getCodeSet(), context);
+            bool ok = instr->translate(errba != etiss::instr::BitArray(32, 0) ? errba : mainba, line.getCodeSet(), context);
             if (unlikely(!ok))
             {
                 return etiss::RETURNCODE::GENERALERROR;

From 64879f6215560c35d2dd0c78157fe852e5dc595a Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 4 Nov 2022 11:06:13 +0100
Subject: [PATCH 14/44] add new arch files

---
 ArchImpl/RV32IMACFD/CMakeLists.txt            |   7 +-
 .../RV32IMACFD/RV32IMACFDArchSpecificImp.cpp  | 325 ++++--------------
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         |  68 ++--
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp |  10 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp |   6 +-
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     |  33 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp |  50 +--
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    | 120 +------
 8 files changed, 161 insertions(+), 458 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index 3b84fca035..85e34659ad 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -23,7 +23,12 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFD_tum_rvaInstr.cpp
 )
 
-FILE(COPY "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}")
+add_custom_command(
+	TARGET ${PROJECT_NAME} POST_BUILD
+	COMMAND ${CMAKE_COMMAND} -E copy
+		"${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h"
+		"${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}"
+)
 INSTALL(FILES "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "include/jit/Arch/${PROJECT_NAME}")
 
 ETISSPluginArch(${PROJECT_NAME})
\ No newline at end of file
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
index 507e197bca..442e9d7eac 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -12,7 +12,7 @@
 
 #include "RV32IMACFDArch.h"
 #include "RV32IMACFDArchSpecificImp.h"
-#include "Encoding.h"
+
 /**
 	@brief This function will be called automatically in order to handling exceptions such as interrupt, system call, illegal instructions
 
@@ -29,259 +29,8 @@
 */
 etiss::int32 RV32IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu)
 {
-	etiss_uint32 handledCause = cause;
-
-    std::function<void()> disableItr = [cpu]() {
-        if (likely((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MIE))
-        {
-            // Push MIE, SIE, UIE to MPIE, SPIE, UPIE
-            etiss_uint32 irq_enable = ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MIE) |
-                                      ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_UIE) |
-                                      ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_SIE);
-            (*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) = (irq_enable << 4) | ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & 0xffffff00);
-        }
-    };
-
-    std::function<etiss_uint32(etiss_uint32, etiss_uint32)> handle = [cpu, cause](etiss_uint32 causeCode,
-                                                                                  etiss_uint32 addr) {
-        std::stringstream msg;
-
-        msg << "Exception is captured with cause code: 0x" << std::hex << causeCode;
-        msg << "  Exception message: " << etiss::RETURNCODE::getErrorMessages()[cause] << std::endl;
-
-        switch (causeCode & 0x80000000)
-        {
-
-        // Exception
-        case 0x0:
-            // Check exception delegation
-            if (*((RV32IMACFD *)cpu)->CSR[CSR_MEDELEG] & (1 << (causeCode & 0x1f)))
-            {
-                // Pop MPIE to MIE
-                etiss::log(etiss::VERBOSE, "Exception is delegated to supervisor mode");
-                (*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) ^=
-                    (((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MPIE) >> 4) ^ ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MIE);
-                *((RV32IMACFD *)cpu)->CSR[CSR_SCAUSE] = causeCode;
-                // Redo the instruction encoutered exception after handling
-                *((RV32IMACFD *)cpu)->CSR[CSR_SEPC] = static_cast<etiss_uint32>(cpu->instructionPointer - 4);
-                *((RV32IMACFD *)cpu)->CSR[CSR_SSTATUS] ^= (*((RV32IMACFD *)cpu)->CSR[3088] << 8) ^ (*((RV32IMACFD *)cpu)->CSR[CSR_SSTATUS & MSTATUS_SPP]);
-                *((RV32IMACFD *)cpu)->CSR[3088] = PRV_S;
-                cpu->instructionPointer = *((RV32IMACFD *)cpu)->CSR[CSR_STVEC] & ~0x3;
-            }
-            else
-            {
-                *((RV32IMACFD *)cpu)->CSR[CSR_MCAUSE] = causeCode;
-                // Redo the instruction encoutered exception after handling
-                *((RV32IMACFD *)cpu)->CSR[CSR_MEPC] = static_cast<etiss_uint32>(cpu->instructionPointer - 4);
-                (*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) ^=
-                    (*((RV32IMACFD *)cpu)->CSR[3088] << 11) ^ ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MPP);
-                *((RV32IMACFD *)cpu)->CSR[3088] = PRV_M;
-                // Customized handler address other than specified in RISC-V ISA manual
-                if (addr)
-                {
-                    cpu->instructionPointer = addr;
-                    break;
-                }
-                cpu->instructionPointer = *((RV32IMACFD *)cpu)->CSR[CSR_MTVEC] & ~0x3;
-            }
-            break;
-
-        // Interrupt
-        case 0x80000000:
-            // Check exception delegation
-            if (*((RV32IMACFD *)cpu)->CSR[CSR_MIDELEG] & (1 << (causeCode & 0x1f)))
-            {
-                // Pop MPIE to MIE
-                etiss::log(etiss::VERBOSE, "Interrupt is delegated to supervisor mode");
-                (*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) ^=
-                    (((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MPIE) >> 4) ^ ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MIE);
-                *((RV32IMACFD *)cpu)->CSR[CSR_SCAUSE] = causeCode;
-                // Return to instruction next interrupted one
-                *((RV32IMACFD *)cpu)->CSR[CSR_SEPC] = static_cast<etiss_uint32>(cpu->instructionPointer);
-                *((RV32IMACFD *)cpu)->CSR[CSR_SSTATUS] ^= (*((RV32IMACFD *)cpu)->CSR[3088] << 8) ^ (*((RV32IMACFD *)cpu)->CSR[CSR_SSTATUS] & MSTATUS_SPP);
-                *((RV32IMACFD *)cpu)->CSR[3088] = PRV_S;
-                if (*((RV32IMACFD *)cpu)->CSR[CSR_STVEC] & 0x1)
-                    cpu->instructionPointer = (*((RV32IMACFD *)cpu)->CSR[CSR_STVEC] & ~0x3) + causeCode * 4;
-                else
-                    cpu->instructionPointer = *((RV32IMACFD *)cpu)->CSR[CSR_STVEC] & ~0x3;
-            }
-            else
-            {
-                *((RV32IMACFD *)cpu)->CSR[CSR_MCAUSE] = causeCode;
-                // Return to instruction next interrupted one
-                *((RV32IMACFD *)cpu)->CSR[CSR_MEPC] = static_cast<etiss_uint32>(cpu->instructionPointer);
-                (*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) ^=
-                    (*((RV32IMACFD *)cpu)->CSR[3088] << 11) ^ ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MPP);
-                *((RV32IMACFD *)cpu)->CSR[3088] = PRV_M;
-                // Customized handler address other than specified in RISC-V ISA manual
-                if (addr)
-                {
-                    cpu->instructionPointer = addr;
-                    break;
-                }
-                if (*((RV32IMACFD *)cpu)->CSR[CSR_MTVEC] & 0x1)
-                    cpu->instructionPointer = (*((RV32IMACFD *)cpu)->CSR[CSR_MTVEC] & ~0x3) + causeCode * 4;
-                else
-                    cpu->instructionPointer = *((RV32IMACFD *)cpu)->CSR[CSR_MTVEC] & ~0x3;
-            }
-            break;
-        }
-
-        msg << "Program is redirected to address: 0x" << std::hex << cpu->instructionPointer << std::endl;
-        etiss::log(etiss::VERBOSE, msg.str());
-        return etiss::RETURNCODE::NOERROR;
-    };
-
-    switch (cause)
-    {
-
-    case etiss::RETURNCODE::INTERRUPT:
-        if (!((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MIE))
-        {
-            std::stringstream msg;
-            msg << "Interrupt handling is globally disabled. Interrupt line is still pending." << std::endl;
-            etiss::log(etiss::INFO, msg.str());
-            handledCause = etiss::RETURNCODE::NOERROR;
-            break;
-        }
-        {
-            etiss_uint32 mip_tmp = (*(((RV32IMACFD *)cpu))->CSR[CSR_MIP]);
-            if (0 == mip_tmp)
-            {
-                handledCause = etiss::RETURNCODE::NOERROR;
-                break;
-            }
-            etiss_uint32 irqLine = 0;
-            for (size_t i = 0; i < sizeof(mip_tmp) * 8; ++i)
-            {
-                // Highest interrupt line with highest priority
-                if (unlikely((mip_tmp >> i) & 0x1))
-                    irqLine = i;
-            }
-
-            if (!((*(((RV32IMACFD *)cpu))->CSR[CSR_MIE]) & (1 << irqLine)))
-            {
-                std::stringstream msg;
-                handledCause = etiss::RETURNCODE::NOERROR;
-                msg << "Interrupt line: " << irqLine << " is disabled. Interrupt is still pending." << std::endl;
-                etiss::log(etiss::INFO, msg.str());
-                break;
-            }
-
-            disableItr();
-
-            handledCause = handle(irqLine | 0x80000000, 0);
-        }
-        break;
-
-    case etiss::RETURNCODE::RESET:
-        handledCause = handle(0, etiss::cfg().get<uint64_t>("vp.entry_point", 0));
-        break;
-
-    case etiss::RETURNCODE::INSTR_PAGEFAULT:
-        disableItr();
-        handledCause = handle(CAUSE_FETCH_PAGE_FAULT, 0);
-        break;
-
-    case etiss::RETURNCODE::LOAD_PAGEFAULT:
-
-        disableItr();
-        handledCause = handle(CAUSE_LOAD_PAGE_FAULT, 0);
-        break;
-
-    case etiss::RETURNCODE::STORE_PAGEFAULT:
-
-        disableItr();
-        handledCause = handle(CAUSE_STORE_PAGE_FAULT, 0);
-        break;
-
-    case etiss::RETURNCODE::ILLEGALINSTRUCTION:
-    {
-        disableItr();
-        std::stringstream msg;
-        msg << "Illegal instruction at address: 0x" << std::hex << cpu->instructionPointer << std::endl;
-        *((RV32IMACFD *)cpu)->CSR[CSR_MTVAL] = static_cast<etiss_uint32>(cpu->instructionPointer);
-        // Point to next instruction
-        cpu->instructionPointer += 4;
-        etiss::log(etiss::WARNING, msg.str());
-        handledCause = handle(CAUSE_ILLEGAL_INSTRUCTION, 0);
-        break;
-    }
-
-    case etiss::RETURNCODE::DBUS_READ_ERROR:
-
-        disableItr();
-        handledCause = handle(CAUSE_LOAD_ACCESS, 0);
-        break;
-
-    case etiss::RETURNCODE::DBUS_WRITE_ERROR:
-
-        disableItr();
-        handledCause = handle(CAUSE_STORE_ACCESS, 0);
-        break;
-
-    case etiss::RETURNCODE::IBUS_READ_ERROR:
-
-        disableItr();
-        handledCause = handle(CAUSE_FETCH_ACCESS, 0);
-        break;
-
-    case etiss::RETURNCODE::IBUS_WRITE_ERROR:
-
-        disableItr();
-        handledCause = handle(CAUSE_STORE_ACCESS, 0);
-        break;
-
-    case etiss::RETURNCODE::BREAKPOINT:
-
-        disableItr();
-        handledCause = handle(CAUSE_BREAKPOINT, 0);
-        break;
-
-    case etiss::RETURNCODE::SYSCALL:
-
-        disableItr();
-        switch (*((RV32IMACFD *)cpu)->CSR[3088])
-        {
-        case PRV_U:
-            handledCause = handle(CAUSE_USER_ECALL, 0);
-            break;
-        case PRV_S:
-            handledCause = handle(CAUSE_SUPERVISOR_ECALL, 0);
-            break;
-        case PRV_M:
-            handledCause = handle(CAUSE_MACHINE_ECALL, 0);
-            break;
-        default:
-            etiss::log(etiss::ERROR, "System call type not supported for current architecture.");
-        }
-
-        break;
-
-    case etiss::RETURNCODE::ILLEGALJUMP:
-    {
-        disableItr();
-        std::stringstream msg;
-        msg << "Illegal instruction access at address: 0x" << std::hex << cpu->instructionPointer << std::endl;
-        *((RV32IMACFD *)cpu)->CSR[CSR_MTVAL] = static_cast<etiss_uint32>(cpu->instructionPointer);
-        // Point to next instruction
-        cpu->instructionPointer += 4;
-        etiss::log(etiss::WARNING, msg.str());
-        handledCause = handle(CAUSE_FETCH_ACCESS, 0);
-        break;
-    }
-
-    default:
-    {
-        std::stringstream msg;
-        msg << "Exception is not handled by architecture. Exception message: ";
-        msg << etiss::RETURNCODE::getErrorMessages()[cause] << std::endl;
-        etiss::log(etiss::INFO, msg.str());
-    }
-        handledCause = cause;
-        break;
-    }
-	return handledCause;
+    etiss::log(etiss::WARNING, "in old exception handler");
+    return cause;
 }
 
 /**
@@ -343,8 +92,76 @@ void RV32IMACFDArch::initInstrSet(etiss::instr::ModedInstructionSet & mis) const
 		etiss::log(etiss::FATALERROR,"Failed to add instructions for RV32IMACFDISA");
 
     etiss::instr::VariableInstructionSet *vis = mis.get(1);
+
     using namespace etiss;
     using namespace etiss::instr;
+
+    	vis->get(32)->getInvalid().addCallback(
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 error_code = 0;
+static BitArrayRange R_error_code_0(31, 0);
+error_code += R_error_code_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//trap_entry 32\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + ");\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0
+	);
+
+	vis->get(16)->getInvalid().addCallback(
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 error_code = 0;
+static BitArrayRange R_error_code_0(31, 0);
+error_code += R_error_code_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//trap_entry 16\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + ");\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0
+	);
+
     vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) {
         std::function<void(InstructionContext & ic, etiss_uint32 opRd)> updateRV32IMACFDInstrLength =
             [](InstructionContext &ic, etiss_uint32 opRd) {
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index 87a078b9f0..909def9296 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 15 Jul 2022 16:36:47 +0200.
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -16,45 +16,6 @@
 
 
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_int32 raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
-{
-cpu->return_pending = 1;
-if (irq != 0U) {
-return -9;
-} else {
-if (mcause == 0 || mcause == 1) {
-return -7;
-}
-if (mcause == 2) {
-return -11;
-}
-if (mcause == 3) {
-return 2147483648;
-}
-if (mcause == 4 || mcause == 5) {
-return -5;
-}
-if (mcause == 6 || mcause == 7) {
-return -6;
-}
-if (mcause == 8 || mcause == 9 || mcause == 10 || mcause == 11) {
-return -17;
-}
-if (mcause == 12 || mcause == 20) {
-return -13;
-}
-if (mcause == 13 || mcause == 21) {
-return -14;
-}
-if (mcause == 15 || mcause == 23) {
-return -15;
-}
-return -11;
-}
-}
-#endif
-
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline void leave(etiss_int32 priv_lvl);
 #endif
@@ -230,6 +191,31 @@ if (csr == 1) {
 }
 }
 #endif
+static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
+{
+return (reg & mask) / (mask & ~((mask << 1UL)));
+}
+static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
+{
+return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1UL)))) & mask));
+}
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
+{
+cpu->return_pending = 1;
+etiss_uint32 epc = cpu->instructionPointer;
+cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773] & -2);
+*((RV32IMACFD*)cpu)->CSR[833] = epc;
+*((RV32IMACFD*)cpu)->CSR[834] = mcause;
+etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[768];
+s = set_field(s, 128, get_field(s, 8));
+s = set_field(s, 6144, ((RV32IMACFD*)cpu)->PRIV);
+s = set_field(s, 8, 0U);
+*((RV32IMACFD*)cpu)->CSR[768] = s;
+((RV32IMACFD*)cpu)->PRIV = (3) & 0x7;
+}
+#endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
@@ -246,7 +232,7 @@ code = 15;
 } else {
 code = 2;
 }
-cpu->exception = raise(cpu, system, plugin_pointers, 0U, code);
+raise(cpu, system, plugin_pointers, 0U, code);
 }
 #endif
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index 1d6c9d56e3..f198c4c102 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Wed, 12 Oct 2022 12:21:19 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -1596,7 +1596,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_int64 res = 0U;\n";
+partInit.code() += "etiss_int32 res = 0U;\n";
 partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 0U, " + std::to_string(rm) + ");\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
@@ -1667,10 +1667,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 0U, " + std::to_string(rm) + ");\n";
+partInit.code() += "etiss_uint32 res = 0U;\n";
+partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 1U, " + std::to_string(rm) + ");\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(res));\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 08e0c5622a..09e9d2c23e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Wed, 12 Oct 2022 12:21:19 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -1295,7 +1295,7 @@ partInit.code() += "etiss_uint32 res = 0U;\n";
 partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
 partInit.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + ");\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((etiss_int32)(res));\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
@@ -1775,7 +1775,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index 10499827b0..e80cf6a739 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -52,10 +52,9 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if (imm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + ";\n";
 } else {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -549,13 +548,12 @@ imm += R_imm_17.read(ba) << 17;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (imm == 0U) {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -623,10 +621,9 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if (nzimm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[2U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
 } else {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -687,9 +684,8 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1476,21 +1472,19 @@ uimm += R_uimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
+if (rd % 32U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ", (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res = mem_val_0;\n";
-if (rd % 32U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 } else {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
-		partInit.getRegisterDependencies().add(reg_name[2U], 32);
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
 
@@ -1612,7 +1606,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if (rs1) {
 partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2;\n";
 } else {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
@@ -1664,9 +1658,8 @@ static InstructionDefinition __reserved_cmv_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1831,7 +1824,7 @@ static InstructionDefinition cebreak_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 3U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1946,7 +1939,7 @@ static InstructionDefinition dii_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 6664102cdb..2d4bff9aa3 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -44,7 +44,7 @@ imm += R_imm_12.read(ba) << 12;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string((etiss_int32)(imm)) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string((etiss_uint32)(((etiss_int32)(imm)))) + ";\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -172,7 +172,7 @@ imm += R_imm_20.read(ba) << 20;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n";
@@ -249,7 +249,7 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
 partInit.code() += "if (new_pc % 2U) {\n";
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
 if ((rd % 32U) != 0U) {
@@ -331,13 +331,13 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -416,13 +416,13 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -501,13 +501,13 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -586,13 +586,13 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -671,13 +671,13 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -756,13 +756,13 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -839,7 +839,7 @@ partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, lo
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
@@ -913,7 +913,7 @@ partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, lo
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
@@ -987,7 +987,7 @@ partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, lo
 partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
@@ -1630,7 +1630,7 @@ imm += R_imm_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1698,7 +1698,7 @@ imm += R_imm_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1766,7 +1766,7 @@ imm += R_imm_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -2314,7 +2314,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (1U) : (0U);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -2794,7 +2794,7 @@ static InstructionDefinition ecall_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 11U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -2841,7 +2841,7 @@ static InstructionDefinition ebreak_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "cpu->exception = raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 3U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 6aecf336cc..cccbefbde1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Wed, 12 Oct 2022 12:21:19 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
@@ -37,12 +37,17 @@ static InstructionDefinition mret_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[768] & 6144U) >> 11U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768] = *((RV32IMACFD*)cpu)->CSR[768] ^ (*((RV32IMACFD*)cpu)->CSR[768] & 6144U);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[768] = *((RV32IMACFD*)cpu)->CSR[768] ^ ((*((RV32IMACFD*)cpu)->CSR[768] & 128U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[768] & 8U);\n";
 partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[768];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256) + "] = *((RV32IMACFD*)cpu)->CSR[768];\n";
+partInit.code() += "etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[768];\n";
+partInit.code() += "etiss_uint32 prev_prv = get_field(s, " + std::to_string(6144) + ");\n";
+partInit.code() += "if (prev_prv != 3) {\n";
+partInit.code() += "s = set_field(s, " + std::to_string(131072) + ", 0U);\n";
+partInit.code() += "}\n";
+partInit.code() += "s = set_field(s, " + std::to_string(8) + ", get_field(s, " + std::to_string(128) + "));\n";
+partInit.code() += "s = set_field(s, " + std::to_string(128) + ", 1U);\n";
+partInit.code() += "s = set_field(s, " + std::to_string(6144) + ", " + std::to_string(3) + ");\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768) + "] = s;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -65,106 +70,3 @@ ss << "mret" << " # " << ba << (" []");
 		return ss.str();
 	}
 );
-
-// URET ------------------------------------------------------------------------
-static InstructionDefinition uret_ (
-	ISA32_RV32IMACFD,
-	"uret",
-	(uint32_t) 0x200073,
-	(uint32_t) 0xffffffff,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
-
-		partInit.code() = std::string("//URET\n");
-
-// -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = 0U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[0U] ^ ((*((RV32IMACFD*)cpu)->CSR[0U] & 16U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[0U] & 1U);\n";
-partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[65U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768) + "] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256) + "] = *((RV32IMACFD*)cpu)->CSR[0U];\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "uret" << " # " << ba << (" []");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
-// SRET ------------------------------------------------------------------------
-static InstructionDefinition sret_ (
-	ISA32_RV32IMACFD,
-	"sret",
-	(uint32_t) 0x10200073,
-	(uint32_t) 0xffffffff,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
-
-		partInit.code() = std::string("//SRET\n");
-
-// -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[3088U] = (*((RV32IMACFD*)cpu)->CSR[256] & 256U) >> 8U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256] = *((RV32IMACFD*)cpu)->CSR[256] ^ (*((RV32IMACFD*)cpu)->CSR[256] & 256U);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[256] = *((RV32IMACFD*)cpu)->CSR[256] ^ ((*((RV32IMACFD*)cpu)->CSR[256] & 32U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[256] & 2U);\n";
-partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768) + "] = *((RV32IMACFD*)cpu)->CSR[256];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[0U] = *((RV32IMACFD*)cpu)->CSR[256];\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "sret" << " # " << ba << (" []");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);

From a12fba40922969d1f8e814d8e91dc84c466c934d Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 4 Nov 2022 11:06:29 +0100
Subject: [PATCH 15/44] add rv64 arch

---
 ArchImpl/CMakeLists.txt                       |    1 +
 ArchImpl/RV64IMACFD/CMakeLists.txt            |   40 +
 ArchImpl/RV64IMACFD/Encoding.h                |  203 ++
 ArchImpl/RV64IMACFD/RV64IMACFD.h              |   68 +
 ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp        |  262 ++
 ArchImpl/RV64IMACFD/RV64IMACFDArch.h          |  105 +
 ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp     |   48 +
 .../RV64IMACFD/RV64IMACFDArchSpecificImp.cpp  |  336 ++
 .../RV64IMACFD/RV64IMACFDArchSpecificImp.h    |   82 +
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h         |  240 ++
 ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h       |   70 +
 ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp       |   15 +
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp |  832 +++++
 .../RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp     |  303 ++
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp | 1839 +++++++++++
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp | 1866 +++++++++++
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     | 1881 +++++++++++
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp | 2913 +++++++++++++++++
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp |  603 ++++
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp |  832 +++++
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp |  399 +++
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp |  287 ++
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     |  695 ++++
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp | 1070 ++++++
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp |  392 +++
 .../RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp   |   81 +
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    |  445 +++
 .../RV64IMACFD/RV64IMACFD_tum_retInstr.cpp    |   72 +
 .../RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp  |  185 ++
 .../RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp    |  185 ++
 30 files changed, 16350 insertions(+)
 create mode 100644 ArchImpl/RV64IMACFD/CMakeLists.txt
 create mode 100644 ArchImpl/RV64IMACFD/Encoding.h
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD.h
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFDArch.h
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp

diff --git a/ArchImpl/CMakeLists.txt b/ArchImpl/CMakeLists.txt
index c7ea595fab..0d2c701f2b 100644
--- a/ArchImpl/CMakeLists.txt
+++ b/ArchImpl/CMakeLists.txt
@@ -39,3 +39,4 @@ ADD_SUBDIRECTORY(OR1K)
 ADD_SUBDIRECTORY(RISCV)
 ADD_SUBDIRECTORY(RISCV64)
 ADD_SUBDIRECTORY(RV32IMACFD)
+ADD_SUBDIRECTORY(RV64IMACFD)
diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt
new file mode 100644
index 0000000000..17af8c3370
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/CMakeLists.txt
@@ -0,0 +1,40 @@
+# Generated on Thu, 03 Nov 2022 14:26:19 +0100.
+#
+# This file contains the CMake build info for the RV64IMACFD core architecture.
+
+PROJECT(RV64IMACFD)
+
+ADD_LIBRARY(${PROJECT_NAME} SHARED
+	RV64IMACFDArch.cpp
+	RV64IMACFDArchLib.cpp
+	RV64IMACFDArchSpecificImp.cpp
+	RV64IMACFDInstr.cpp
+	RV64IMACFD_RV32IInstr.cpp
+	RV64IMACFD_RV64IInstr.cpp
+	RV64IMACFD_RV32ICInstr.cpp
+	RV64IMACFD_RV64ICInstr.cpp
+	RV64IMACFD_RV32MInstr.cpp
+	RV64IMACFD_RV64MInstr.cpp
+	RV64IMACFD_RV32FInstr.cpp
+	RV64IMACFD_RV64FInstr.cpp
+	RV64IMACFD_RV32DInstr.cpp
+	RV64IMACFD_RV64DInstr.cpp
+	RV64IMACFD_RV32DCInstr.cpp
+	RV64IMACFD_RV32AInstr.cpp
+	RV64IMACFD_RV64AInstr.cpp
+	RV64IMACFD_ZifenceiInstr.cpp
+	RV64IMACFD_tum_csrInstr.cpp
+	RV64IMACFD_tum_retInstr.cpp
+	RV64IMACFD_tum_rvaInstr.cpp
+	RV64IMACFD_tum_rva64Instr.cpp
+)
+
+add_custom_command(
+	TARGET ${PROJECT_NAME} POST_BUILD
+	COMMAND ${CMAKE_COMMAND} -E copy
+		"${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h"
+		"${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}"
+)
+INSTALL(FILES "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "include/jit/Arch/${PROJECT_NAME}")
+
+ETISSPluginArch(${PROJECT_NAME})
\ No newline at end of file
diff --git a/ArchImpl/RV64IMACFD/Encoding.h b/ArchImpl/RV64IMACFD/Encoding.h
new file mode 100644
index 0000000000..d551ed5626
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/Encoding.h
@@ -0,0 +1,203 @@
+/*
+
+        @copyright
+
+        <pre>
+
+        Copyright 2018 Chair of Electronic Design Automation, TUM
+
+        This file is part of ETISS tool, see <https://github.com/tum-ei-eda/etiss>.
+
+        The initial version of this software has been created with the funding support by the German Federal
+        Ministry of Education and Research (BMBF) in the project EffektiV under grant 01IS13022.
+
+        Redistribution and use in source and binary forms, with or without modification, are permitted
+        provided that the following conditions are met:
+
+        1. Redistributions of source code must retain the above copyright notice, this list of conditions and
+        the following disclaimer.
+
+        2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions
+        and the following disclaimer in the documentation and/or other materials provided with the distribution.
+
+        3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse
+        or promote products derived from this software without specific prior written permission.
+
+        THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+        WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+        PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+        DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+        PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+        HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+        NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+        POSSIBILITY OF SUCH DAMAGE.
+
+        </pre>
+
+        @author Chair of Electronic Design Automation, TUM
+
+        @version 0.1
+
+*/
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE 0x00000001
+#define MSTATUS_SIE 0x00000002
+#define MSTATUS_HIE 0x00000004
+#define MSTATUS_MIE 0x00000008
+#define MSTATUS_UPIE 0x00000010
+#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_MPIE 0x00000080
+#define MSTATUS_SPP 0x00000100
+#define MSTATUS_HPP 0x00000600
+#define MSTATUS_MPP 0x00001800
+#define MSTATUS_FS 0x00006000
+#define MSTATUS_XS 0x00018000
+#define MSTATUS_MPRV 0x00020000
+#define MSTATUS_SUM 0x00040000
+#define MSTATUS_MXR 0x00080000
+#define MSTATUS_TVM 0x00100000
+#define MSTATUS_TW 0x00200000
+#define MSTATUS_TSR 0x00400000
+#define MSTATUS32_SD 0x80000000
+#define MSTATUS_UXL 0x0000000300000000
+#define MSTATUS_SXL 0x0000000C00000000
+#define MSTATUS64_SD 0x8000000000000000
+
+#define SSTATUS_UIE 0x00000001
+#define SSTATUS_SIE 0x00000002
+#define SSTATUS_UPIE 0x00000010
+#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_SPP 0x00000100
+#define SSTATUS_FS 0x00006000
+#define SSTATUS_XS 0x00018000
+#define SSTATUS_SUM 0x00040000
+#define SSTATUS_MXR 0x00080000
+#define SSTATUS32_SD 0x80000000
+#define SSTATUS_UXL 0x0000000300000000
+#define SSTATUS64_SD 0x8000000000000000
+
+#define MIP_SSIP (1 << IRQ_S_SOFT)
+#define MIP_HSIP (1 << IRQ_H_SOFT)
+#define MIP_MSIP (1 << IRQ_M_SOFT)
+#define MIP_STIP (1 << IRQ_S_TIMER)
+#define MIP_HTIP (1 << IRQ_H_TIMER)
+#define MIP_MTIP (1 << IRQ_M_TIMER)
+#define MIP_SEIP (1 << IRQ_S_EXT)
+#define MIP_HEIP (1 << IRQ_H_EXT)
+#define MIP_MEIP (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define PAGE_OFFSET 12
+#define OFFSET_MASK ((1 << PAGE_OFFSET) - 1)
+#define PAGE_SIZE 1 << PAGE_OFFSET
+#define LEVELS 3
+#define VPN_OFFSET 9
+#define PTESIZE 8
+#define SATP_PPN_MASK ((0x1ULL << 44ULL) - 1ULL)
+
+#define SATP32_MODE 0x80000000
+#define SATP32_ASID 0x7FC00000
+#define SATP32_PPN 0x003FFFFF
+#define SATP64_MODE 0xF000000000000000
+#define SATP64_ASID 0x0FFFF00000000000
+#define SATP64_PPN 0x00000FFFFFFFFFFF
+
+#define SATP_MODE_OFF 0
+#define SATP_MODE_SV32 1
+#define SATP_MODE_SV39 8
+#define SATP_MODE_SV48 9
+#define SATP_MODE_SV57 10
+#define SATP_MODE_SV64 11
+
+#define PMP_R 0x01
+#define PMP_W 0x02
+#define PMP_X 0x04
+#define PMP_A 0x18
+#define PMP_L 0x80
+#define PMP_SHIFT 2
+
+#define PMP_TOR 0x08
+#define PMP_NA4 0x10
+#define PMP_NAPOT 0x18
+
+#define IRQ_S_SOFT 1
+#define IRQ_H_SOFT 2
+#define IRQ_M_SOFT 3
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT 9
+#define IRQ_H_EXT 10
+#define IRQ_M_EXT 11
+#define IRQ_COP 12
+#define IRQ_HOST 13
+
+#define DEFAULT_RSTVEC 0x00001000
+#define CLINT_BASE 0x02000000
+#define CLINT_SIZE 0x000c0000
+#define EXT_IO_BASE 0x40000000
+#define DRAM_BASE 0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V 0x001    // Valid
+#define PTE_R 0x002    // Read
+#define PTE_W 0x004    // Write
+#define PTE_X 0x008    // Execute
+#define PTE_U 0x010    // User
+#define PTE_G 0x020    // Global
+#define PTE_A 0x040    // Accessed
+#define PTE_D 0x080    // Dirty
+#define PTE_SOFT 0x300 // Reserved for Software
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SCOUNTEREN 0x106
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_STVAL 0x143
+#define CSR_SIP 0x144
+#define CSR_SATP 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MTVAL 0x343
+#define CSR_MIP 0x344
+
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FETCH_ACCESS 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_STORE_ACCESS 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#define CAUSE_FETCH_PAGE_FAULT 0xc
+#define CAUSE_LOAD_PAGE_FAULT 0xd
+#define CAUSE_STORE_PAGE_FAULT 0xf
+#endif
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD.h b/ArchImpl/RV64IMACFD/RV64IMACFD.h
new file mode 100644
index 0000000000..46e160dd3a
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD.h
@@ -0,0 +1,68 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the registers for the RV64IMACFD core architecture.
+ */
+
+#ifndef ETISS_RV64IMACFDArch_RV64IMACFD_H_
+#define ETISS_RV64IMACFDArch_RV64IMACFD_H_
+#include <stdio.h>
+#include "etiss/jit/CPU.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#pragma pack(push, 1)
+struct RV64IMACFD {
+	ETISS_CPU cpu; // original cpu struct must be defined as the first field of the new structure. this allows to cast X * to ETISS_CPU * and vice vers
+	etiss_uint64 ZERO;
+	etiss_uint64 RA;
+	etiss_uint64 SP;
+	etiss_uint64 GP;
+	etiss_uint64 TP;
+	etiss_uint64 T0;
+	etiss_uint64 T1;
+	etiss_uint64 T2;
+	etiss_uint64 S0;
+	etiss_uint64 S1;
+	etiss_uint64 A0;
+	etiss_uint64 A1;
+	etiss_uint64 A2;
+	etiss_uint64 A3;
+	etiss_uint64 A4;
+	etiss_uint64 A5;
+	etiss_uint64 A6;
+	etiss_uint64 A7;
+	etiss_uint64 S2;
+	etiss_uint64 S3;
+	etiss_uint64 S4;
+	etiss_uint64 S5;
+	etiss_uint64 S6;
+	etiss_uint64 S7;
+	etiss_uint64 S8;
+	etiss_uint64 S9;
+	etiss_uint64 S10;
+	etiss_uint64 S11;
+	etiss_uint64 T3;
+	etiss_uint64 T4;
+	etiss_uint64 T5;
+	etiss_uint64 T6;
+	etiss_uint64 *X[32];
+	etiss_uint64 ins_X[32];
+	etiss_uint64 FENCE[8];
+	etiss_uint8 RES[8];
+	etiss_uint8 PRIV;
+	etiss_uint64 DPC;
+	etiss_uint64 FCSR;
+	etiss_uint64 *CSR[4096];
+	etiss_uint64 ins_CSR[4096];
+	etiss_uint64 F[32];
+	etiss_uint64 RES_ADDR;
+};
+
+#pragma pack(pop) // undo changes
+typedef struct RV64IMACFD RV64IMACFD; // convenient use of X instead of struct X in generated C code
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
new file mode 100644
index 0000000000..f5fc2d6905
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
@@ -0,0 +1,262 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the architecture class for the RV64IMACFD core architecture.
+ */
+
+/*********************************************************************************************************************************
+
+* Modification guidelines:
+
+	 1. The initial value of SP register should be initialized by ctr0.S/board.S. If not, it could be initialized
+		 through utility class etiss::VirtualStruct::Field.
+
+	 2. Debug mode print out all assignment results. GDB in 8 is prefered.
+
+	 3. Manually copy the content in bracket ["return ETISS_RETURNCODE_CPUFINISHED; \n"] to terminating instruction,
+		 otherwise the emulation can not be ended.
+
+	 4. If subset of encoding error occurs, it means the format of the encoding in the input model was not appropriate
+
+	 5. If the PC register points to wrong address, please notice that some assembly may cause branch operation
+		 implicitly such as "MOV Rd Rn" in ARMv6-M
+
+	 6. If a variable is the result of dynamic slicing such as, var_1 = var_2<Hshift-1..Lshift-2>, the size would be
+		 calculated during process (if possible), otherwise it is assumed to be the register size. Problems may occur when
+		 var_1 encounters bit manipulation such as "~" due to bit expansion. To change the nml model with explicit slicing
+		 e.g var_1 = val_2<3..0> or avoid bit manipulation for dynamic sliced variable. Otherwise, you have to manually
+		 correct it.
+
+	 7. Implementation dependent functionalities such as exception handling should be manully added. Corresponding interfaces
+		 are provided in RV64IMACFDArchSpecificImp.h
+
+	 8. RV64IMACFDGDBCore.h provides the GDBCore class to support gdb flavor debugging feature, modify iy if in need.
+
+ *********************************************************************************************************************************/
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+#define RV64IMACFD_DEBUG_CALL 0
+using namespace etiss ;
+using namespace etiss::instr ;
+
+RV64IMACFDArch::RV64IMACFDArch():CPUArch("RV64IMACFD")
+{
+	headers_.insert("Arch/RV64IMACFD/RV64IMACFD.h");
+}
+
+const std::set<std::string> & RV64IMACFDArch::getListenerSupportedRegisters()
+{
+	return listenerSupportedRegisters_;
+}
+
+ETISS_CPU * RV64IMACFDArch::newCPU()
+{
+	ETISS_CPU * ret = (ETISS_CPU *) new RV64IMACFD() ;
+	resetCPU (ret, 0);
+	return ret;
+}
+
+void RV64IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
+{
+	memset (cpu, 0, sizeof(RV64IMACFD));
+	RV64IMACFD * rv64imacfdcpu = (RV64IMACFD *) cpu;
+
+	if (startpointer) cpu->instructionPointer = *startpointer & ~((etiss::uint64)0x1);
+	else cpu->instructionPointer = 0x0;   //  reference to manual
+	cpu->nextPc = cpu->instructionPointer;
+	cpu->mode = 1;
+	cpu->cpuTime_ps = 0;
+	cpu->cpuCycleTime_ps = 31250;
+
+
+	for (int i = 0; i < 32; ++i) {
+		rv64imacfdcpu->ins_X[i] = 0;
+		rv64imacfdcpu->X[i] = &rv64imacfdcpu->ins_X[i];
+	}
+	for (int i = 0; i < 4096; ++i) {
+		rv64imacfdcpu->ins_CSR[i] = 0;
+		rv64imacfdcpu->CSR[i] = &rv64imacfdcpu->ins_CSR[i];
+	}
+
+	rv64imacfdcpu->ZERO = 0;
+	rv64imacfdcpu->RA = 0;
+	rv64imacfdcpu->SP = 0;
+	rv64imacfdcpu->GP = 0;
+	rv64imacfdcpu->TP = 0;
+	rv64imacfdcpu->T0 = 0;
+	rv64imacfdcpu->T1 = 0;
+	rv64imacfdcpu->T2 = 0;
+	rv64imacfdcpu->S0 = 0;
+	rv64imacfdcpu->S1 = 0;
+	rv64imacfdcpu->A0 = 0;
+	rv64imacfdcpu->A1 = 0;
+	rv64imacfdcpu->A2 = 0;
+	rv64imacfdcpu->A3 = 0;
+	rv64imacfdcpu->A4 = 0;
+	rv64imacfdcpu->A5 = 0;
+	rv64imacfdcpu->A6 = 0;
+	rv64imacfdcpu->A7 = 0;
+	rv64imacfdcpu->S2 = 0;
+	rv64imacfdcpu->S3 = 0;
+	rv64imacfdcpu->S4 = 0;
+	rv64imacfdcpu->S5 = 0;
+	rv64imacfdcpu->S6 = 0;
+	rv64imacfdcpu->S7 = 0;
+	rv64imacfdcpu->S8 = 0;
+	rv64imacfdcpu->S9 = 0;
+	rv64imacfdcpu->S10 = 0;
+	rv64imacfdcpu->S11 = 0;
+	rv64imacfdcpu->T3 = 0;
+	rv64imacfdcpu->T4 = 0;
+	rv64imacfdcpu->T5 = 0;
+	rv64imacfdcpu->T6 = 0;
+	for (int i = 0; i < 8; ++i) {
+		rv64imacfdcpu->FENCE[i] = 0;
+	}
+	for (int i = 0; i < 8; ++i) {
+		rv64imacfdcpu->RES[i] = 0;
+	}
+	rv64imacfdcpu->PRIV = 0;
+	rv64imacfdcpu->DPC = 0;
+	rv64imacfdcpu->FCSR = 0;
+	for (int i = 0; i < 32; ++i) {
+		rv64imacfdcpu->F[i] = 0;
+	}
+	rv64imacfdcpu->RES_ADDR = 0;
+
+ 	rv64imacfdcpu->X[0] = &rv64imacfdcpu->ZERO;
+ 	rv64imacfdcpu->X[1] = &rv64imacfdcpu->RA;
+ 	rv64imacfdcpu->X[2] = &rv64imacfdcpu->SP;
+ 	rv64imacfdcpu->X[3] = &rv64imacfdcpu->GP;
+ 	rv64imacfdcpu->X[4] = &rv64imacfdcpu->TP;
+ 	rv64imacfdcpu->X[5] = &rv64imacfdcpu->T0;
+ 	rv64imacfdcpu->X[6] = &rv64imacfdcpu->T1;
+ 	rv64imacfdcpu->X[7] = &rv64imacfdcpu->T2;
+ 	rv64imacfdcpu->X[8] = &rv64imacfdcpu->S0;
+ 	rv64imacfdcpu->X[9] = &rv64imacfdcpu->S1;
+ 	rv64imacfdcpu->X[10] = &rv64imacfdcpu->A0;
+ 	rv64imacfdcpu->X[11] = &rv64imacfdcpu->A1;
+ 	rv64imacfdcpu->X[12] = &rv64imacfdcpu->A2;
+ 	rv64imacfdcpu->X[13] = &rv64imacfdcpu->A3;
+ 	rv64imacfdcpu->X[14] = &rv64imacfdcpu->A4;
+ 	rv64imacfdcpu->X[15] = &rv64imacfdcpu->A5;
+ 	rv64imacfdcpu->X[16] = &rv64imacfdcpu->A6;
+ 	rv64imacfdcpu->X[17] = &rv64imacfdcpu->A7;
+ 	rv64imacfdcpu->X[18] = &rv64imacfdcpu->S2;
+ 	rv64imacfdcpu->X[19] = &rv64imacfdcpu->S3;
+ 	rv64imacfdcpu->X[20] = &rv64imacfdcpu->S4;
+ 	rv64imacfdcpu->X[21] = &rv64imacfdcpu->S5;
+ 	rv64imacfdcpu->X[22] = &rv64imacfdcpu->S6;
+ 	rv64imacfdcpu->X[23] = &rv64imacfdcpu->S7;
+ 	rv64imacfdcpu->X[24] = &rv64imacfdcpu->S8;
+ 	rv64imacfdcpu->X[25] = &rv64imacfdcpu->S9;
+ 	rv64imacfdcpu->X[26] = &rv64imacfdcpu->S10;
+ 	rv64imacfdcpu->X[27] = &rv64imacfdcpu->S11;
+ 	rv64imacfdcpu->X[28] = &rv64imacfdcpu->T3;
+ 	rv64imacfdcpu->X[29] = &rv64imacfdcpu->T4;
+ 	rv64imacfdcpu->X[30] = &rv64imacfdcpu->T5;
+ 	rv64imacfdcpu->X[31] = &rv64imacfdcpu->T6;
+ 	rv64imacfdcpu->CSR[3] = &rv64imacfdcpu->FCSR;
+
+ 	rv64imacfdcpu->PRIV = 3;
+ 	rv64imacfdcpu->DPC = 0;
+ 	*rv64imacfdcpu->CSR[0] = 11;
+	*rv64imacfdcpu->CSR[256] = 11;
+	*rv64imacfdcpu->CSR[768] = 11;
+	*rv64imacfdcpu->CSR[769] = 9223372036856090925;
+	*rv64imacfdcpu->CSR[3088] = 3;
+	*rv64imacfdcpu->CSR[772] = 4294966203;
+	*rv64imacfdcpu->CSR[260] = 4294964019;
+	*rv64imacfdcpu->CSR[4] = 4294963473;
+ 	rv64imacfdcpu->RES_ADDR = -1;
+}
+
+void RV64IMACFDArch::deleteCPU(ETISS_CPU *cpu)
+{
+	delete (RV64IMACFD *) cpu ;
+}
+
+/**
+	@return 8 (jump instruction + instruction of delay slot)
+*/
+unsigned RV64IMACFDArch::getMaximumInstructionSizeInBytes()
+{
+	return 8;
+}
+
+/**
+	@return 2
+*/
+unsigned RV64IMACFDArch::getInstructionSizeInBytes()
+{
+	return 2;
+}
+
+/**
+	@brief required headers (RV64IMACFD.h)
+*/
+const std::set<std::string> & RV64IMACFDArch::getHeaders() const
+{
+	return headers_ ;
+}
+
+void RV64IMACFDArch::initCodeBlock(etiss::CodeBlock & cb) const
+{
+	cb.fileglobalCode().insert("#include \"Arch/RV64IMACFD/RV64IMACFD.h\"\n");
+	cb.fileglobalCode().insert("#include \"Arch/RV64IMACFD/RV64IMACFDFuncs.h\"\n");
+	cb.functionglobalCode().insert("cpu->exception = 0;\n");
+	cb.functionglobalCode().insert("cpu->return_pending = 0;\n");
+	cb.functionglobalCode().insert("etiss_uint32 mem_ret_code = 0;\n");
+}
+
+etiss::plugin::gdb::GDBCore & RV64IMACFDArch::getGDBCore()
+{
+	return gdbcore_;
+}
+
+const char * const reg_name[] =
+{
+	"X0",
+	"X1",
+	"X2",
+	"X3",
+	"X4",
+	"X5",
+	"X6",
+	"X7",
+	"X8",
+	"X9",
+	"X10",
+	"X11",
+	"X12",
+	"X13",
+	"X14",
+	"X15",
+	"X16",
+	"X17",
+	"X18",
+	"X19",
+	"X20",
+	"X21",
+	"X22",
+	"X23",
+	"X24",
+	"X25",
+	"X26",
+	"X27",
+	"X28",
+	"X29",
+	"X30",
+	"X31",
+};
+
+etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16);
+etiss::instr::InstructionClass ISA16_RV64IMACFDClass(1, "ISA16_RV64IMACFD", 16, ISA16_RV64IMACFD);
+etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32);
+etiss::instr::InstructionClass ISA32_RV64IMACFDClass(1, "ISA32_RV64IMACFD", 32, ISA32_RV64IMACFD);
+
+etiss::instr::InstructionCollection RV64IMACFDISA("RV64IMACFDISA", ISA16_RV64IMACFDClass, ISA32_RV64IMACFDClass);
\ No newline at end of file
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
new file mode 100644
index 0000000000..f8d7b5f674
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
@@ -0,0 +1,105 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the architecture class for the RV64IMACFD core architecture.
+ */
+
+#ifndef ETISS_RV64IMACFDArch_RV64IMACFDArch_H_
+#define ETISS_RV64IMACFDArch_RV64IMACFDArch_H_
+
+#include "etiss/CPUArch.h"
+#include "etiss/Instruction.h"
+#include "etiss/InterruptVector.h"
+#include "RV64IMACFD.h"
+#include "RV64IMACFDGDBCore.h"
+
+#include <map>
+
+extern const char * const reg_name[];
+
+extern etiss::instr::InstructionGroup ISA16_RV64IMACFD;
+extern etiss::instr::InstructionClass ISA16_RV64IMACFDClass;
+extern etiss::instr::InstructionGroup ISA32_RV64IMACFD;
+extern etiss::instr::InstructionClass ISA32_RV64IMACFDClass;
+
+extern etiss::instr::InstructionCollection RV64IMACFDISA;
+
+class RV64IMACFDArch : public etiss::CPUArch {
+
+public:
+	RV64IMACFDArch();
+
+	virtual const std::set<std::string> & getListenerSupportedRegisters();
+
+
+	virtual ETISS_CPU * newCPU();
+	virtual void resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer);
+	virtual void deleteCPU(ETISS_CPU *);
+
+	/**
+		@brief get the VirtualStruct of the core to mitigate register access
+
+		@see RV64IMACFDArchSpecificImp.h
+	*/
+	virtual std::shared_ptr<etiss::VirtualStruct> getVirtualStruct(ETISS_CPU * cpu);
+
+	/**
+		@return 8 (jump instruction + instruction of delay slot)
+	*/
+	virtual unsigned getMaximumInstructionSizeInBytes();
+
+	/**
+		@return 2
+	*/
+	virtual unsigned getInstructionSizeInBytes();
+
+	/**
+		@brief required headers (RV64IMACFD.h)
+	*/
+	virtual const std::set<std::string> & getHeaders() const;
+
+	/**
+		@brief This function will be called automatically in order to handling architecure dependent exceptions such
+			   as interrupt, system call, illegal instructions
+
+		@see RV64IMACFDArchSpecificImp.h
+	*/
+	virtual etiss::int32 handleException(etiss::int32 code, ETISS_CPU * cpu);
+
+	/**
+		@brief This function is called during CPUArch initialization
+
+		@see RV64IMACFDArchSpecificImp.h
+	*/
+	virtual void initInstrSet(etiss::instr::ModedInstructionSet & ) const;
+	virtual void initCodeBlock(etiss::CodeBlock & cb) const;
+
+	/**
+		@brief Target architecture may have inconsistent endianess. Data read from memory is buffered, and this function
+			   is called to alter sequence of buffered data so that the inconsistent endianess is compensated.
+
+		@see RV64IMACFDArchSpecificImp.h
+	*/
+	virtual void compensateEndianess(ETISS_CPU * cpu, etiss::instr::BitArray & ba) const ;
+
+	/**
+		@brief If interrupt handling is expected, vector table could be provided to support interrupt triggering
+
+		@see RV64IMACFDArchSpecificImp.h
+	*/
+	virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU * cpu);
+	virtual void deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu);
+
+	/**
+		@brief get the GDBcore for RV64IMACFD architecture
+
+		@see RV64IMACFDGDBCore.h for implementation of GDBcore
+	*/
+	virtual etiss::plugin::gdb::GDBCore & getGDBCore();
+
+private:
+	std::set<std::string> listenerSupportedRegisters_;
+	std::set<std::string> headers_;
+	RV64IMACFDGDBCore gdbcore_;
+};
+#endif
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
new file mode 100644
index 0000000000..3a7e52fc2e
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
@@ -0,0 +1,48 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the library interface for the RV64IMACFD core architecture.
+ */
+
+// define a name for this library. this will be used to avoid name clashes with other libraries. in this example the library is named "X".
+// IMPORTANT this name MUST match the library name: e.g. X -> libX.so
+
+#define ETISS_LIBNAME RV64IMACFD
+#include "etiss/helper/CPUArchLibrary.h" // defines the following functions
+#include "RV64IMACFDArch.h"
+extern "C" {
+
+	ETISS_LIBRARYIF_VERSION_FUNC_IMPL
+
+	ETISS_PLUGIN_EXPORT unsigned RV64IMACFD_countCPUArch()
+	{
+//TODO
+		return 1; // number of cpu architectures provided
+	}
+	ETISS_PLUGIN_EXPORT const char * RV64IMACFD_nameCPUArch(unsigned index)
+	{
+//TODO
+		switch (index)
+		{
+		case 0:
+			return "RV64IMACFD";
+		default:
+			return "";
+		}
+	}
+	ETISS_PLUGIN_EXPORT etiss::CPUArch* RV64IMACFD_createCPUArch(unsigned index,std::map<std::string,std::string> options)
+	{
+//TODO
+		switch (index)
+		{
+		case 0:
+			return new RV64IMACFDArch();
+		default:
+			return 0;
+		}
+	}
+	ETISS_PLUGIN_EXPORT void RV64IMACFD_deleteCPUArch(etiss::CPUArch* arch)
+	{
+		delete arch;
+	}
+}
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
new file mode 100644
index 0000000000..83d236a357
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -0,0 +1,336 @@
+/**
+ * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ *
+ * This file contains the architecture specific implementation for the RV64IMACFD
+ * core architecture.
+ *
+ * WARNING: This file contains user-added code, be mindful when overwriting this with
+ * generated code!
+ */
+
+#include <vector>
+
+#include "RV64IMACFDArch.h"
+#include "RV64IMACFDArchSpecificImp.h"
+
+/**
+	@brief This function will be called automatically in order to handling exceptions such as interrupt, system call, illegal instructions
+
+	@details Exception handling mechanism is implementation dependent for each cpu variant. Please add it to the following block if exception
+				handling is demanded.
+				Pesudo example:
+				switch(cause){
+						case etiss::RETURNCODE::INTERRUPT:
+							.
+							.
+							.
+						break;
+
+*/
+etiss::int32 RV64IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu)
+{
+	etiss_uint32 handledCause = cause;
+
+	/**************************************************************************
+	*		 Exception handling machanism should be implemented here		  *
+	***************************************************************************/
+
+	return handledCause;
+}
+
+/**
+	@brief This function is called during CPUArch initialization
+
+	@details Function pointer length_updater_ has to be replaced if multiple length instruction execution is supported. This
+				function enables dynamic instruction length update in order to guarantee correct binary translation
+				Pesudo example:
+				vis->length_updater_ = [](VariableInstructionSet & ,InstructionContext & ic, BitArray & ba)
+				{
+					switch(ba.byteCount()){
+						case 4:
+							if ( INSTRUCTION_LENTH_NOT_EQUAL(4)){
+								updateInstrLength(ic, ba);
+								ic.is_not_default_width_ = true;
+									.
+									.
+									.
+							}
+							break;
+					}
+				};
+
+*/
+void RV64IMACFDArch::initInstrSet(etiss::instr::ModedInstructionSet & mis) const
+{
+
+    {
+     /* Set default JIT Extensions. Read Parameters set from ETISS configuration and append with architecturally needed */
+     std::string cfgPar = "";
+     cfgPar = etiss::cfg().get<std::string>("jit.external_headers", ";");
+     etiss::cfg().set<std::string>("jit.external_headers", cfgPar + "etiss/jit/libsoftfloat.h");
+
+     cfgPar = etiss::cfg().get<std::string>("jit.external_libs", ";");
+     etiss::cfg().set<std::string>("jit.external_libs", cfgPar + "softfloat");
+
+     cfgPar = etiss::cfg().get<std::string>("jit.external_header_paths", ";");
+     etiss::cfg().set<std::string>("jit.external_header_paths", cfgPar + "/etiss/jit");
+
+     cfgPar = etiss::cfg().get<std::string>("jit.external_lib_paths", ";");
+     etiss::cfg().set<std::string>("jit.external_lib_paths", cfgPar + "/etiss/jit");
+
+    }
+
+    if (false) {
+        // Pre-compilation of instruction set to view instruction tree. Could be disabled.
+        etiss::instr::ModedInstructionSet iset("RV64IMACFDISA");
+		bool ok = true;
+		RV64IMACFDISA.addTo(iset,ok);
+
+		iset.compile();
+
+		std::cout << iset.print() << std::endl;
+	}
+
+	bool ok = true;
+	RV64IMACFDISA.addTo(mis,ok);
+	if (!ok)
+		etiss::log(etiss::FATALERROR,"Failed to add instructions for RV64IMACFDISA");
+
+	etiss::instr::VariableInstructionSet *vis = mis.get(1);
+
+	using namespace etiss;
+	using namespace etiss::instr;
+
+	vis->get(32)->getInvalid().addCallback(
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 error_code = 0;
+static BitArrayRange R_error_code_0(31, 0);
+error_code += R_error_code_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//trap_entry 32\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + ");\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0
+	);
+
+	vis->get(16)->getInvalid().addCallback(
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 error_code = 0;
+static BitArrayRange R_error_code_0(31, 0);
+error_code += R_error_code_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//trap_entry 16\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + ");\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0
+	);
+
+    vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) {
+        std::function<void(InstructionContext & ic, etiss_uint32 opRd)> updateRV64IMACFDInstrLength =
+            [](InstructionContext &ic, etiss_uint32 opRd) {
+                ic.instr_width_fully_evaluated_ = true;
+                ic.is_not_default_width_ = true;
+                if (opRd == 0x3f)
+                    ic.instr_width_ = 64;
+                else if ((opRd & 0x3f) == 0x1f)
+                    ic.instr_width_ = 48;
+                else if (((opRd & 0x1f) >= 0x3) && ((opRd & 0x1f) < 0x1f))
+                    ic.instr_width_ = 32;
+                else if(opRd == 0x7f) /* P-Extension instructions */
+                    ic.instr_width_ = 32;
+                else if ((opRd & 0x3) != 0x3)
+                    ic.instr_width_ = 16;
+                else
+                    // This might happen when code is followed by data.
+                    ic.is_not_default_width_ = false;
+            };
+
+        BitArrayRange op(6, 0);
+        etiss_uint32 opRd = op.read(ba);
+
+        /*BitArrayRange fullOp(ba.byteCount()*8-1,0);
+        etiss_uint32 fullOpRd = fullOp.read(ba);
+
+        std::stringstream ss;
+        ss << "Byte count: " << ba.byteCount()<< std::endl;
+        ss << "opcode: 0x" <<std::hex<< fullOpRd << std::endl;
+        ss << "Current PC: 0x" <<std::hex<< ic.current_address_ << std::endl;
+        std::cout << ss.str() << std::endl;*/
+
+        switch (ba.byteCount())
+        {
+        case 2:
+            if (((opRd & 0x3) != 0x3) || (opRd == 0))
+            {
+                ic.is_not_default_width_ = false;
+                break;
+            }
+            else
+            {
+                updateRV64IMACFDInstrLength(ic, opRd);
+                break;
+            }
+        case 4:
+            if ((((opRd & 0x1f) >= 0x3) || ((opRd & 0x1f) < 0x1f)) || (opRd == 0))
+            {
+                ic.is_not_default_width_ = false;
+                break;
+            }
+            else if(opRd == 0x7f) /* P-Extension instructions */
+            {
+                updateRV64IMACFDInstrLength(ic, opRd);
+                break;
+            }
+            else
+            {
+                updateRV64IMACFDInstrLength(ic, opRd);
+                break;
+            }
+        case 6:
+            if (((opRd & 0x3f) == 0x1f) || (opRd == 0))
+            {
+                ic.is_not_default_width_ = false;
+                break;
+            }
+            else
+            {
+                updateRV64IMACFDInstrLength(ic, opRd);
+                break;
+            }
+        case 8:
+            if ((opRd == 0x3f) || (opRd == 0))
+            {
+                ic.is_not_default_width_ = false;
+                break;
+            }
+            else
+            {
+                updateRV64IMACFDInstrLength(ic, opRd);
+                break;
+            }
+        default:
+            // This might happen when code is followed by data.
+            ic.is_not_default_width_ = false;
+        }
+    };
+
+}
+
+/**
+	@brief This function is called whenever a data is read from memory
+
+	@details Target architecture may have inconsistent endianess. Data read from memory is buffered, and this function
+				is called to alter sequence of buffered data so that the inconsistent endianess is compensated.
+				Example for ARMv6M:
+				void * ptr = ba.internalBuffer();
+				if (ba.byteCount() == 2)
+				{
+					*((uint32_t*)ptr) = ((uint16_t)(*((uint8_t*)ptr))) | ((uint16_t)(*(((uint8_t*)ptr)+1)) << 8);
+				}
+				else if (ba.byteCount() == 4)
+				{
+					*((uint32_t*)ptr) = ((((uint32_t)(*((uint8_t*)ptr))) | ((uint32_t)(*(((uint8_t*)ptr)+1)) << 8)) << 16) | ((uint32_t)(*(((uint8_t*)ptr)+2)) ) | ((uint32_t)(*(((uint8_t*)ptr)+3)) << 8);
+				}
+				else
+				{
+					etiss::log(etiss::FATALERROR,"Endianess cannot be handled",ba.byteCount());
+				}
+
+	@attention Default endianess: little-endian
+
+*/
+void RV64IMACFDArch::compensateEndianess(ETISS_CPU * cpu, etiss::instr::BitArray & ba) const
+{
+	/**************************************************************************
+	*		                Endianess compensation	                    	  *
+	***************************************************************************/
+}
+
+std::shared_ptr<etiss::VirtualStruct> RV64IMACFDArch::getVirtualStruct(ETISS_CPU * cpu)
+{
+	auto ret = etiss::VirtualStruct::allocate(
+		cpu,
+		[] (etiss::VirtualStruct::Field*f) {
+			delete f;
+		}
+	);
+
+	for (uint32_t i = 0; i < 32; ++i){
+		ret->addField(new RegField_RV64IMACFD(*ret,i));
+	}
+
+	ret->addField(new pcField_RV64IMACFD(*ret));
+	return ret;
+}
+
+/**
+	@brief If interrupt handling is expected, vector table could be provided to support interrupt triggering
+
+	@details Interrupt vector table is used to inform the core whenever an edge/level triggered interrupt
+				incoming. The content of interrupt vector could be a special register or standalone interrupt
+				lines.
+*/
+etiss::InterruptVector * RV64IMACFDArch::createInterruptVector(ETISS_CPU * cpu)
+{
+	if (cpu == 0)
+		return 0;
+
+	/**************************************************************************
+	*		            Implementation of interrupt vector              	  *
+	***************************************************************************/
+
+	// This is a default vector, implemented to avoid segfaults. Replace
+	// with actual implementation if necessary.
+
+	std::vector<etiss::uint32 *> vec;
+	std::vector<etiss::uint32 *> mask;
+
+	return new etiss::MappedInterruptVector<etiss::uint32>(vec, mask);
+}
+
+void RV64IMACFDArch::deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu)
+{
+	delete vec;
+}
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
new file mode 100644
index 0000000000..dda86f3a55
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
@@ -0,0 +1,82 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the architecture specific header for the RV64IMACFD
+ * core architecture.
+ *
+ * WARNING: This file contains user-added code, be mindful when overwriting this with
+ * generated code!
+ */
+
+#ifndef ETISS_RV64IMACFDArch_RV64IMACFDARCHSPECIFICIMP_H_
+#define ETISS_RV64IMACFDArch_RV64IMACFDARCHSPECIFICIMP_H_
+
+/**
+	@brief VirtualStruct for RV64IMACFD architecture to faciliate register acess
+
+	@details VirtualStruct enables user to access certain register via their name without knowning ETISS hierarchy of a core.
+				Further fiels might be needed to enable gdbserver etc.
+
+*/
+class RegField_RV64IMACFD : public etiss::VirtualStruct::Field{
+private:
+	const unsigned gprid_;
+public:
+	RegField_RV64IMACFD(etiss::VirtualStruct & parent,unsigned gprid)
+		: Field(parent,
+			std::string("X")+etiss::toString(gprid),
+			std::string("X")+etiss::toString(gprid),
+			R|W,
+			8
+		),
+		gprid_(gprid)
+	{}
+
+	RegField_RV64IMACFD(etiss::VirtualStruct & parent, std::string name, unsigned gprid)
+		: Field(parent,
+			name,
+			name,
+			R|W,
+			8
+		),
+		gprid_(gprid)
+	{}
+
+	virtual ~RegField_RV64IMACFD(){}
+
+protected:
+	virtual uint64_t _read() const {
+		return (uint64_t) *((RV64IMACFD*)parent_.structure_)->X[gprid_];
+	}
+
+	virtual void _write(uint64_t val) {
+		etiss::log(etiss::VERBOSE, "write to ETISS cpu state", name_, val);
+		*((RV64IMACFD*)parent_.structure_)->X[gprid_] = (etiss_uint64) val;
+	}
+};
+
+class pcField_RV64IMACFD : public etiss::VirtualStruct::Field{
+public:
+	pcField_RV64IMACFD(etiss::VirtualStruct & parent)
+		: Field(parent,
+			"instructionPointer",
+			"instructionPointer",
+			R|W,
+			8
+		)
+	{}
+
+	virtual ~pcField_RV64IMACFD(){}
+
+protected:
+	virtual uint64_t _read() const {
+		return (uint64_t) ((ETISS_CPU *)parent_.structure_)->instructionPointer;
+	}
+
+	virtual void _write(uint64_t val) {
+		etiss::log(etiss::VERBOSE, "write to ETISS cpu state", name_, val);
+		((ETISS_CPU *)parent_.structure_)->instructionPointer = (etiss_uint64) val;
+	}
+};
+
+#endif
\ No newline at end of file
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
new file mode 100644
index 0000000000..0c17d2790f
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -0,0 +1,240 @@
+/**
+ * Generated on Thu, 03 Nov 2022 15:55:27 +0100.
+ *
+ * This file contains the function macros for the RV64IMACFD core architecture.
+ */
+
+#ifndef __RV64IMACFD_FUNCS_H
+#define __RV64IMACFD_FUNCS_H
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+#include "Arch/RV64IMACFD/RV64IMACFD.h"
+#include "etiss/jit/CPU.h"
+#include "etiss/jit/System.h"
+#include "etiss/jit/ReturnCode.h"
+#endif
+
+
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void leave(etiss_int32 priv_lvl);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void wait(etiss_int32 flag);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 unbox_s(etiss_uint64);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fclass_s(etiss_uint32);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fget_flags();
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 unbox_d(etiss_uint64);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 fclass_d(etiss_uint64);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 etiss_get_time();
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint64 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
+{
+if (csr == 1) {
+return *((RV64IMACFD*)cpu)->CSR[3] & 31UL;
+}
+if (csr == 2) {
+return (*((RV64IMACFD*)cpu)->CSR[3] >> 5UL) & 7U;
+}
+if (csr == 3072) {
+return etiss_get_cycles(cpu, system, plugin_pointers);
+}
+if (csr == 3200) {
+return etiss_get_cycles(cpu, system, plugin_pointers) >> 32U;
+}
+if (csr == 3073) {
+return etiss_get_time();
+}
+if (csr == 3201) {
+return etiss_get_time() >> 32U;
+}
+if (csr == 3074) {
+return etiss_get_instret(cpu, system, plugin_pointers);
+}
+if (csr == 3202) {
+return etiss_get_instret(cpu, system, plugin_pointers) >> 32U;
+}
+return *((RV64IMACFD*)cpu)->CSR[csr];
+}
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val)
+{
+if (csr == 1) {
+*((RV64IMACFD*)cpu)->CSR[3] = (*((RV64IMACFD*)cpu)->CSR[3] & 224UL) | (val & 31UL);
+} else if (csr == 2) {
+*((RV64IMACFD*)cpu)->CSR[3] = ((val & 7UL) << 5U) | (*((RV64IMACFD*)cpu)->CSR[3] & 31UL);
+} else if (csr == 3) {
+*((RV64IMACFD*)cpu)->CSR[3] = val & 255UL;
+} else if (csr == 768) {
+*((RV64IMACFD*)cpu)->CSR[768] = val & 136UL;
+} else {
+*((RV64IMACFD*)cpu)->CSR[csr] = val;
+}
+}
+#endif
+static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
+{
+return (reg & mask) / (mask & ~((mask << 1UL)));
+}
+static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
+{
+return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1UL)))) & mask));
+}
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
+{
+cpu->return_pending = 1;
+etiss_uint64 epc = cpu->instructionPointer;
+cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773] & -2L);
+*((RV64IMACFD*)cpu)->CSR[833] = epc;
+*((RV64IMACFD*)cpu)->CSR[834] = mcause;
+etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[768];
+s = set_field(s, 128, get_field(s, 8));
+s = set_field(s, 6144, ((RV64IMACFD*)cpu)->PRIV);
+s = set_field(s, 8, 0U);
+*((RV64IMACFD*)cpu)->CSR[768] = s;
+((RV64IMACFD*)cpu)->PRIV = (3) & 0x7;
+}
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
+{
+etiss_int32 code = 0U;
+if (cause == -5) {
+code = 5;
+} else if (cause == -14) {
+code = 13;
+} else if (cause == -6) {
+code = 7;
+} else if (cause == -15) {
+code = 15;
+} else if (cause == -7) {
+code = 1;
+} else {
+code = 2;
+}
+cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
new file mode 100644
index 0000000000..1bc725ec32
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
@@ -0,0 +1,70 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the GDBCore adapter for the RV64IMACFD core architecture.
+ *
+ * WARNING: This file contains user-added code, be mindful when overwriting this with
+ * generated code!
+ */
+
+#ifndef ETISS_RV64IMACFDArch_RV64IMACFDGDBCORE_H_
+#define ETISS_RV64IMACFDArch_RV64IMACFDGDBCORE_H_
+
+#include "etiss/IntegratedLibrary/gdb/GDBCore.h"
+#include <sstream>
+
+/**
+	@brief This class is the brige between RV64IMACFD architecture and gdbserver
+
+	@details Gdbserver integrated in ETISS calls GDBCore to read/write registers via virtualStrruct
+				The index in mapRegister() should strictly follow the RV64IMACFD gdb tool defined register
+				order. Because gdbserver will send raw register data sequentially in strict order over
+				RSP ->TCP/IP ->RSP protocal
+
+				Check the order with gdb command:
+				$(gdb) info all-registers
+				which lists all registers supported and its order.
+
+				By default only general purpose register and instruction pointer are supported. Further
+				Special Function Register/Control and Status Register could be added manually. Meanwhile
+				virtualStruct in RV64IMACFDArch.cpp should be modified as well as well
+
+*/
+class RV64IMACFDGDBCore : public etiss::plugin::gdb::GDBCore {
+public:
+	std::string mapRegister(unsigned index){
+		if (index < 32){
+			std::stringstream ss;
+			ss << "X" << index;
+			return ss.str();
+		}
+		switch (index){
+		case 32:
+			return "instructionPointer";
+		/**************************************************************************
+		*   Further register should be added here to send data over gdbserver	  *
+		***************************************************************************/
+		}
+		return "";
+	}
+
+	unsigned mapRegister(std::string name){
+		return INVALIDMAPPING;
+	}
+
+	unsigned mappedRegisterCount(){
+		// Modify according to sent register number
+		return 33;
+	}
+
+	etiss::uint64 getInstructionPointer(ETISS_CPU * cpu){
+		return cpu->instructionPointer;
+	}
+
+	bool isLittleEndian(){
+		// Modify according to RV64IMACFD manual
+		return true;
+	}
+};
+
+#endif
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
new file mode 100644
index 0000000000..56293d9d22
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
@@ -0,0 +1,15 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the default
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
new file mode 100644
index 0000000000..fd282e815a
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -0,0 +1,832 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the RV32A
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// AMOSWAPW --------------------------------------------------------------------
+static InstructionDefinition amoswapw_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amoswapw",
+	(uint32_t) 0x800202f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOSWAPW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
+}
+partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amoswapw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOADDW ---------------------------------------------------------------------
+static InstructionDefinition amoaddw_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amoaddw",
+	(uint32_t) 0x00202f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOADDW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+}
+partInit.code() += "etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amoaddw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOXORW ---------------------------------------------------------------------
+static InstructionDefinition amoxorw_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amoxorw",
+	(uint32_t) 0x2000202f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOXORW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+}
+partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amoxorw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOANDW ---------------------------------------------------------------------
+static InstructionDefinition amoandw_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amoandw",
+	(uint32_t) 0x6000202f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOANDW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+}
+partInit.code() += "etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amoandw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOORW ----------------------------------------------------------------------
+static InstructionDefinition amoorw_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amoorw",
+	(uint32_t) 0x4000202f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOORW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+}
+partInit.code() += "etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amoorw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOMINW ---------------------------------------------------------------------
+static InstructionDefinition amominw_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amominw",
+	(uint32_t) 0x8000202f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOMINW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+}
+partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amominw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOMAXW ---------------------------------------------------------------------
+static InstructionDefinition amomaxw_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amomaxw",
+	(uint32_t) 0xa000202f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOMAXW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+}
+partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amomaxw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOMINUW --------------------------------------------------------------------
+static InstructionDefinition amominuw_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amominuw",
+	(uint32_t) 0xc000202f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOMINUW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n";
+}
+partInit.code() += "etiss_uint32 res2 = (res1 > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amominuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOMAXUW --------------------------------------------------------------------
+static InstructionDefinition amomaxuw_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amomaxuw",
+	(uint32_t) 0xe000202f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOMAXUW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n";
+}
+partInit.code() += "etiss_uint32 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amomaxuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
new file mode 100644
index 0000000000..5daa8d428e
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -0,0 +1,303 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the RV32DC
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// CFLD ------------------------------------------------------------------------
+static InstructionDefinition cfld_rd_uimm_rs1 (
+	ISA16_RV64IMACFD,
+	"cfld",
+	(uint16_t) 0x2000,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(4, 2);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(6, 5);
+uimm += R_uimm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CFLD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(4, 2);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(6, 5);
+uimm += R_uimm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cfld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CFSD ------------------------------------------------------------------------
+static InstructionDefinition cfsd_rs2_uimm_rs1 (
+	ISA16_RV64IMACFD,
+	"cfsd",
+	(uint16_t) 0xa000,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(6, 5);
+uimm += R_uimm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CFSD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(6, 5);
+uimm += R_uimm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cfsd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CFLDSP ----------------------------------------------------------------------
+static InstructionDefinition cfldsp_uimm_rd (
+	ISA16_RV64IMACFD,
+	"cfldsp",
+	(uint16_t) 0x2002,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 uimm = 0;
+static BitArrayRange R_uimm_6(4, 2);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_3(6, 5);
+uimm += R_uimm_3.read(ba) << 3;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+static BitArrayRange R_uimm_5(12, 12);
+uimm += R_uimm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CFLDSP\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[2U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 uimm = 0;
+static BitArrayRange R_uimm_6(4, 2);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_3(6, 5);
+uimm += R_uimm_3.read(ba) << 3;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+static BitArrayRange R_uimm_5(12, 12);
+uimm += R_uimm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cfldsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CFSDSP ----------------------------------------------------------------------
+static InstructionDefinition cfsdsp_rs2_uimm (
+	ISA16_RV64IMACFD,
+	"cfsdsp",
+	(uint16_t) 0xa002,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(6, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint16 uimm = 0;
+static BitArrayRange R_uimm_6(9, 7);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CFSDSP\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[2U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(6, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint16 uimm = 0;
+static BitArrayRange R_uimm_6(9, 7);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cfsdsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
new file mode 100644
index 0000000000..90e5a5a4ca
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -0,0 +1,1839 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the RV32D
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// FLD -------------------------------------------------------------------------
+static InstructionDefinition fld_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"fld",
+	(uint32_t) 0x003007,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FLD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSD -------------------------------------------------------------------------
+static InstructionDefinition fsd_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fsd",
+	(uint32_t) 0x003027,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsd" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMADD_D ---------------------------------------------------------------------
+static InstructionDefinition fmadd_d_rd_rm_rs1_rs2_rs3 (
+	ISA32_RV64IMACFD,
+	"fmadd_d",
+	(uint32_t) 0x2000043,
+	(uint32_t) 0x600007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMADD_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMSUB_D ---------------------------------------------------------------------
+static InstructionDefinition fmsub_d_rd_rm_rs1_rs2_rs3 (
+	ISA32_RV64IMACFD,
+	"fmsub_d",
+	(uint32_t) 0x2000047,
+	(uint32_t) 0x600007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMSUB_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FNMADD_D --------------------------------------------------------------------
+static InstructionDefinition fnmadd_d_rd_rm_rs1_rs2_rs3 (
+	ISA32_RV64IMACFD,
+	"fnmadd_d",
+	(uint32_t) 0x200004f,
+	(uint32_t) 0x600007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FNMADD_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fnmadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FNMSUB_D --------------------------------------------------------------------
+static InstructionDefinition fnmsub_d_rd_rm_rs1_rs2_rs3 (
+	ISA32_RV64IMACFD,
+	"fnmsub_d",
+	(uint32_t) 0x200004b,
+	(uint32_t) 0x600007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FNMSUB_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fnmsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FADD_D ----------------------------------------------------------------------
+static InstructionDefinition fadd_d_rd_rm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fadd_d",
+	(uint32_t) 0x2000053,
+	(uint32_t) 0xfe00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FADD_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSUB_D ----------------------------------------------------------------------
+static InstructionDefinition fsub_d_rd_rm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fsub_d",
+	(uint32_t) 0xa000053,
+	(uint32_t) 0xfe00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSUB_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMUL_D ----------------------------------------------------------------------
+static InstructionDefinition fmul_d_rd_rm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fmul_d",
+	(uint32_t) 0x12000053,
+	(uint32_t) 0xfe00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMUL_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmul_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FDIV_D ----------------------------------------------------------------------
+static InstructionDefinition fdiv_d_rd_rm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fdiv_d",
+	(uint32_t) 0x1a000053,
+	(uint32_t) 0xfe00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FDIV_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fdiv_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSQRT_D ---------------------------------------------------------------------
+static InstructionDefinition fsqrt_d_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fsqrt_d",
+	(uint32_t) 0x5a000053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSQRT_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsqrt_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSGNJ_D ---------------------------------------------------------------------
+static InstructionDefinition fsgnj_d_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fsgnj_d",
+	(uint32_t) 0x22000053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSGNJ_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1)) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsgnj_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSGNJN_D --------------------------------------------------------------------
+static InstructionDefinition fsgnjn_d_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fsgnjn_d",
+	(uint32_t) 0x22001053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSGNJN_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1))) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsgnjn_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSGNJX_D --------------------------------------------------------------------
+static InstructionDefinition fsgnjx_d_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fsgnjx_d",
+	(uint32_t) 0x22002053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSGNJX_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) & 9223372036854775808UL);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsgnjx_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMIN_D ----------------------------------------------------------------------
+static InstructionDefinition fmin_d_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fmin_d",
+	(uint32_t) 0x2a000053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMIN_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 0U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmin_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMAX_D ----------------------------------------------------------------------
+static InstructionDefinition fmax_d_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fmax_d",
+	(uint32_t) 0x2a001053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMAX_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 1U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmax_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_S_D --------------------------------------------------------------------
+static InstructionDefinition fcvt_s_d_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_s_d",
+	(uint32_t) 0x40100053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_S_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], " + std::to_string(rm) + ");\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L + res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_s_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_D_S --------------------------------------------------------------------
+static InstructionDefinition fcvt_d_s_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_d_s",
+	(uint32_t) 0x42000053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_D_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), " + std::to_string(rm) + ");\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_d_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FEQ_D -----------------------------------------------------------------------
+static InstructionDefinition feq_d_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"feq_d",
+	(uint32_t) 0xa2002053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FEQ_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = 0U;\n";
+partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 0U);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "feq_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FLT_D -----------------------------------------------------------------------
+static InstructionDefinition flt_d_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"flt_d",
+	(uint32_t) 0xa2001053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FLT_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = 0U;\n";
+partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 2U);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "flt_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FLE_D -----------------------------------------------------------------------
+static InstructionDefinition fle_d_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fle_d",
+	(uint32_t) 0xa2000053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FLE_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = 0U;\n";
+partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 1U);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fle_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCLASS_D --------------------------------------------------------------------
+static InstructionDefinition fclass_d_rd_rs1 (
+	ISA32_RV64IMACFD,
+	"fclass_d",
+	(uint32_t) 0xe2001053,
+	(uint32_t) 0xfff0707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCLASS_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fclass_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_W_D --------------------------------------------------------------------
+static InstructionDefinition fcvt_w_d_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_w_d",
+	(uint32_t) 0xc2000053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_W_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_int32 res = 0U;\n";
+partInit.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 0U, " + std::to_string(rm) + ");\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_w_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_WU_D -------------------------------------------------------------------
+static InstructionDefinition fcvt_wu_d_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_wu_d",
+	(uint32_t) 0xc2100053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_WU_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = 0U;\n";
+partInit.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 1U, " + std::to_string(rm) + ");\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(res));\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_wu_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_D_W --------------------------------------------------------------------
+static InstructionDefinition fcvt_d_w_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_d_w",
+	(uint32_t) 0xd2000053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_D_W\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_d_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_D_WU -------------------------------------------------------------------
+static InstructionDefinition fcvt_d_wu_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_d_wu",
+	(uint32_t) 0xd2100053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_D_WU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_d_wu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
new file mode 100644
index 0000000000..084e6b9a01
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -0,0 +1,1866 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the RV32F
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// FLW -------------------------------------------------------------------------
+static InstructionDefinition flw_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"flw",
+	(uint32_t) 0x002007,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FLW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "flw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSW -------------------------------------------------------------------------
+static InstructionDefinition fsw_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fsw",
+	(uint32_t) 0x002027,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMADD_S ---------------------------------------------------------------------
+static InstructionDefinition fmadd_s_rd_rm_rs1_rs2_rs3 (
+	ISA32_RV64IMACFD,
+	"fmadd_s",
+	(uint32_t) 0x000043,
+	(uint32_t) 0x600007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMADD_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMSUB_S ---------------------------------------------------------------------
+static InstructionDefinition fmsub_s_rd_rm_rs1_rs2_rs3 (
+	ISA32_RV64IMACFD,
+	"fmsub_s",
+	(uint32_t) 0x000047,
+	(uint32_t) 0x600007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMSUB_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FNMADD_S --------------------------------------------------------------------
+static InstructionDefinition fnmadd_s_rd_rm_rs1_rs2_rs3 (
+	ISA32_RV64IMACFD,
+	"fnmadd_s",
+	(uint32_t) 0x00004f,
+	(uint32_t) 0x600007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FNMADD_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fnmadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FNMSUB_S --------------------------------------------------------------------
+static InstructionDefinition fnmsub_s_rd_rm_rs1_rs2_rs3 (
+	ISA32_RV64IMACFD,
+	"fnmsub_s",
+	(uint32_t) 0x00004b,
+	(uint32_t) 0x600007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FNMSUB_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rs3 = 0;
+static BitArrayRange R_rs3_0(31, 27);
+rs3 += R_rs3_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fnmsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FADD_S ----------------------------------------------------------------------
+static InstructionDefinition fadd_s_rd_rm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fadd_s",
+	(uint32_t) 0x000053,
+	(uint32_t) 0xfe00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FADD_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSUB_S ----------------------------------------------------------------------
+static InstructionDefinition fsub_s_rd_rm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fsub_s",
+	(uint32_t) 0x8000053,
+	(uint32_t) 0xfe00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSUB_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMUL_S ----------------------------------------------------------------------
+static InstructionDefinition fmul_s_rd_rm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fmul_s",
+	(uint32_t) 0x10000053,
+	(uint32_t) 0xfe00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMUL_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmul_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FDIV_S ----------------------------------------------------------------------
+static InstructionDefinition fdiv_s_rd_rm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fdiv_s",
+	(uint32_t) 0x18000053,
+	(uint32_t) 0xfe00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FDIV_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fdiv_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSQRT_S ---------------------------------------------------------------------
+static InstructionDefinition fsqrt_s_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fsqrt_s",
+	(uint32_t) 0x58000053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSQRT_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsqrt_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSGNJ_S ---------------------------------------------------------------------
+static InstructionDefinition fsgnj_s_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fsgnj_s",
+	(uint32_t) 0x20000053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSGNJ_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsgnj_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSGNJN_S --------------------------------------------------------------------
+static InstructionDefinition fsgnjn_s_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fsgnjn_s",
+	(uint32_t) 0x20001053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSGNJN_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsgnjn_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FSGNJX_S --------------------------------------------------------------------
+static InstructionDefinition fsgnjx_s_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fsgnjx_s",
+	(uint32_t) 0x20002053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FSGNJX_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fsgnjx_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMIN_S ----------------------------------------------------------------------
+static InstructionDefinition fmin_s_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fmin_s",
+	(uint32_t) 0x28000053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMIN_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmin_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMAX_S ----------------------------------------------------------------------
+static InstructionDefinition fmax_s_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fmax_s",
+	(uint32_t) 0x28001053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMAX_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmax_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_W_S --------------------------------------------------------------------
+static InstructionDefinition fcvt_w_s_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_w_s",
+	(uint32_t) 0xc0000053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_W_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_int32 res = 0U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + ");\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_w_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_WU_S -------------------------------------------------------------------
+static InstructionDefinition fcvt_wu_s_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_wu_s",
+	(uint32_t) 0xc0100053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_WU_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = 0U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + ");\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(res));\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_wu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FEQ_S -----------------------------------------------------------------------
+static InstructionDefinition feq_s_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"feq_s",
+	(uint32_t) 0xa0002053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FEQ_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = 0U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "res = fcmp_s(frs1, frs2, 0U);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "feq_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FLT_S -----------------------------------------------------------------------
+static InstructionDefinition flt_s_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"flt_s",
+	(uint32_t) 0xa0001053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FLT_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = 0U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "res = fcmp_s(frs1, frs2, 2U);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "flt_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FLE_S -----------------------------------------------------------------------
+static InstructionDefinition fle_s_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"fle_s",
+	(uint32_t) 0xa0000053,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FLE_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = 0U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "res = fcmp_s(frs1, frs2, 1U);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fle_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCLASS_S --------------------------------------------------------------------
+static InstructionDefinition fclass_s_rd_rs1 (
+	ISA32_RV64IMACFD,
+	"fclass_s",
+	(uint32_t) 0xe0001053,
+	(uint32_t) 0xfff0707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCLASS_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = 0U;\n";
+partInit.code() += "res = fclass_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fclass_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_S_W --------------------------------------------------------------------
+static InstructionDefinition fcvt_s_w_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_s_w",
+	(uint32_t) 0xd0000053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_S_W\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_s_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_S_WU -------------------------------------------------------------------
+static InstructionDefinition fcvt_s_wu_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_s_wu",
+	(uint32_t) 0xd0100053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_S_WU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_s_wu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMV_X_W ---------------------------------------------------------------------
+static InstructionDefinition fmv_x_w_rd_rs1 (
+	ISA32_RV64IMACFD,
+	"fmv_x_w",
+	(uint32_t) 0xe0000053,
+	(uint32_t) 0xfff0707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMV_X_W\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmv_x_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMV_W_X ---------------------------------------------------------------------
+static InstructionDefinition fmv_w_x_rd_rs1 (
+	ISA32_RV64IMACFD,
+	"fmv_w_x",
+	(uint32_t) 0xf0000053,
+	(uint32_t) 0xfff0707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMV_W_X\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmv_w_x" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
new file mode 100644
index 0000000000..79d88627d4
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -0,0 +1,1881 @@
+/**
+ * Generated on Thu, 03 Nov 2022 15:55:27 +0100.
+ *
+ * This file contains the instruction behavior models of the RV32IC
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// CADDI4SPN -------------------------------------------------------------------
+static InstructionDefinition caddi4spn_rd_imm (
+	ISA16_RV64IMACFD,
+	"caddi4spn",
+	(uint16_t) 0x00,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(4, 2);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_3(5, 5);
+imm += R_imm_3.read(ba) << 3;
+static BitArrayRange R_imm_2(6, 6);
+imm += R_imm_2.read(ba) << 2;
+static BitArrayRange R_imm_6(10, 7);
+imm += R_imm_6.read(ba) << 6;
+static BitArrayRange R_imm_4(12, 11);
+imm += R_imm_4.read(ba) << 4;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CADDI4SPN\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if (imm) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + ";\n";
+} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[2U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(4, 2);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_3(5, 5);
+imm += R_imm_3.read(ba) << 3;
+static BitArrayRange R_imm_2(6, 6);
+imm += R_imm_2.read(ba) << 2;
+static BitArrayRange R_imm_6(10, 7);
+imm += R_imm_6.read(ba) << 6;
+static BitArrayRange R_imm_4(12, 11);
+imm += R_imm_4.read(ba) << 4;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "caddi4spn" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CLW -------------------------------------------------------------------------
+static InstructionDefinition clw_rd_uimm_rs1 (
+	ISA16_RV64IMACFD,
+	"clw",
+	(uint16_t) 0x4000,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(4, 2);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(5, 5);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_2(6, 6);
+uimm += R_uimm_2.read(ba) << 2;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CLW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_int32)(mem_val_0);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(4, 2);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(5, 5);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_2(6, 6);
+uimm += R_uimm_2.read(ba) << 2;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "clw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSW -------------------------------------------------------------------------
+static InstructionDefinition csw_rs2_uimm_rs1 (
+	ISA16_RV64IMACFD,
+	"csw",
+	(uint16_t) 0xc000,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(5, 5);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_2(6, 6);
+uimm += R_uimm_2.read(ba) << 2;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(5, 5);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_2(6, 6);
+uimm += R_uimm_2.read(ba) << 2;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CADDI -----------------------------------------------------------------------
+static InstructionDefinition caddi_imm_rs1 (
+	ISA16_RV64IMACFD,
+	"caddi",
+	(uint16_t) 0x01,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 imm = 0;
+static BitArrayRange R_imm_0(6, 2);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_imm_5(12, 12);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CADDI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if ((rs1 % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rs1 % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 imm = 0;
+static BitArrayRange R_imm_0(6, 2);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_imm_5(12, 12);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "caddi" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CNOP ------------------------------------------------------------------------
+static InstructionDefinition cnop_nzimm (
+	ISA16_RV64IMACFD,
+	"cnop",
+	(uint16_t) 0x01,
+	(uint16_t) 0xef83,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 nzimm = 0;
+static BitArrayRange R_nzimm_0(6, 2);
+nzimm += R_nzimm_0.read(ba) << 0;
+static BitArrayRange R_nzimm_5(12, 12);
+nzimm += R_nzimm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CNOP\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 nzimm = 0;
+static BitArrayRange R_nzimm_0(6, 2);
+nzimm += R_nzimm_0.read(ba) << 0;
+static BitArrayRange R_nzimm_5(12, 12);
+nzimm += R_nzimm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cnop" << " # " << ba << (" [nzimm=" + std::to_string(nzimm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CLI -------------------------------------------------------------------------
+static InstructionDefinition cli_imm_rd (
+	ISA16_RV64IMACFD,
+	"cli",
+	(uint16_t) 0x4001,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 imm = 0;
+static BitArrayRange R_imm_0(6, 2);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+static BitArrayRange R_imm_5(12, 12);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 imm = 0;
+static BitArrayRange R_imm_0(6, 2);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+static BitArrayRange R_imm_5(12, 12);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cli" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CLUI ------------------------------------------------------------------------
+static InstructionDefinition clui_imm_rd (
+	ISA16_RV64IMACFD,
+	"clui",
+	(uint16_t) 0x6001,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(6, 2);
+imm += R_imm_12.read(ba) << 12;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+static BitArrayRange R_imm_17(12, 12);
+imm += R_imm_17.read(ba) << 17;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CLUI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if (imm == 0U) {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+}
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(6, 2);
+imm += R_imm_12.read(ba) << 12;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+static BitArrayRange R_imm_17(12, 12);
+imm += R_imm_17.read(ba) << 17;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "clui" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CADDI16SP -------------------------------------------------------------------
+static InstructionDefinition caddi16sp_nzimm (
+	ISA16_RV64IMACFD,
+	"caddi16sp",
+	(uint16_t) 0x6101,
+	(uint16_t) 0xef83,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 nzimm = 0;
+static BitArrayRange R_nzimm_5(2, 2);
+nzimm += R_nzimm_5.read(ba) << 5;
+static BitArrayRange R_nzimm_7(4, 3);
+nzimm += R_nzimm_7.read(ba) << 7;
+static BitArrayRange R_nzimm_6(5, 5);
+nzimm += R_nzimm_6.read(ba) << 6;
+static BitArrayRange R_nzimm_4(6, 6);
+nzimm += R_nzimm_4.read(ba) << 4;
+static BitArrayRange R_nzimm_9(12, 12);
+nzimm += R_nzimm_9.read(ba) << 9;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CADDI16SP\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if (nzimm) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[2U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
+} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[2U], 64);
+		partInit.getAffectedRegisters().add(reg_name[2U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 nzimm = 0;
+static BitArrayRange R_nzimm_5(2, 2);
+nzimm += R_nzimm_5.read(ba) << 5;
+static BitArrayRange R_nzimm_7(4, 3);
+nzimm += R_nzimm_7.read(ba) << 7;
+static BitArrayRange R_nzimm_6(5, 5);
+nzimm += R_nzimm_6.read(ba) << 6;
+static BitArrayRange R_nzimm_4(6, 6);
+nzimm += R_nzimm_4.read(ba) << 4;
+static BitArrayRange R_nzimm_9(12, 12);
+nzimm += R_nzimm_9.read(ba) << 9;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "caddi16sp" << " # " << ba << (" [nzimm=" + std::to_string(nzimm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// __reserved_clui -------------------------------------------------------------
+static InstructionDefinition __reserved_clui_rd (
+	ISA16_RV64IMACFD,
+	"__reserved_clui",
+	(uint16_t) 0x6001,
+	(uint16_t) 0xf07f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//__reserved_clui\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "__reserved_clui" << " # " << ba << (" [rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSRLI -----------------------------------------------------------------------
+static InstructionDefinition csrli_shamt_rs1 (
+	ISA16_RV64IMACFD,
+	"csrli",
+	(uint16_t) 0x8001,
+	(uint16_t) 0xfc03,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(6, 2);
+shamt += R_shamt_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSRLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(6, 2);
+shamt += R_shamt_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csrli" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSRAI -----------------------------------------------------------------------
+static InstructionDefinition csrai_shamt_rs1 (
+	ISA16_RV64IMACFD,
+	"csrai",
+	(uint16_t) 0x8401,
+	(uint16_t) 0xfc03,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(6, 2);
+shamt += R_shamt_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSRAI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if (shamt) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> " + std::to_string(shamt) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(6, 2);
+shamt += R_shamt_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csrai" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CANDI -----------------------------------------------------------------------
+static InstructionDefinition candi_imm_rs1 (
+	ISA16_RV64IMACFD,
+	"candi",
+	(uint16_t) 0x8801,
+	(uint16_t) 0xec03,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 imm = 0;
+static BitArrayRange R_imm_0(6, 2);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_imm_5(12, 12);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CANDI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 imm = 0;
+static BitArrayRange R_imm_0(6, 2);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_imm_5(12, 12);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "candi" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSUB ------------------------------------------------------------------------
+static InstructionDefinition csub_rs2_rd (
+	ISA16_RV64IMACFD,
+	"csub",
+	(uint16_t) 0x8c01,
+	(uint16_t) 0xfc63,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSUB\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csub" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CXOR ------------------------------------------------------------------------
+static InstructionDefinition cxor_rs2_rd (
+	ISA16_RV64IMACFD,
+	"cxor",
+	(uint16_t) 0x8c21,
+	(uint16_t) 0xfc63,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CXOR\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cxor" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// COR -------------------------------------------------------------------------
+static InstructionDefinition cor_rs2_rd (
+	ISA16_RV64IMACFD,
+	"cor",
+	(uint16_t) 0x8c41,
+	(uint16_t) 0xfc63,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//COR\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cor" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CAND ------------------------------------------------------------------------
+static InstructionDefinition cand_rs2_rd (
+	ISA16_RV64IMACFD,
+	"cand",
+	(uint16_t) 0x8c61,
+	(uint16_t) 0xfc63,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CAND\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cand" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CJ --------------------------------------------------------------------------
+static InstructionDefinition cj_imm (
+	ISA16_RV64IMACFD,
+	"cj",
+	(uint16_t) 0xa001,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_5(2, 2);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_1(5, 3);
+imm += R_imm_1.read(ba) << 1;
+static BitArrayRange R_imm_7(6, 6);
+imm += R_imm_7.read(ba) << 7;
+static BitArrayRange R_imm_6(7, 7);
+imm += R_imm_6.read(ba) << 6;
+static BitArrayRange R_imm_10(8, 8);
+imm += R_imm_10.read(ba) << 10;
+static BitArrayRange R_imm_8(10, 9);
+imm += R_imm_8.read(ba) << 8;
+static BitArrayRange R_imm_4(11, 11);
+imm += R_imm_4.read(ba) << 4;
+static BitArrayRange R_imm_11(12, 12);
+imm += R_imm_11.read(ba) << 11;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CJ\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_5(2, 2);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_1(5, 3);
+imm += R_imm_1.read(ba) << 1;
+static BitArrayRange R_imm_7(6, 6);
+imm += R_imm_7.read(ba) << 7;
+static BitArrayRange R_imm_6(7, 7);
+imm += R_imm_6.read(ba) << 6;
+static BitArrayRange R_imm_10(8, 8);
+imm += R_imm_10.read(ba) << 10;
+static BitArrayRange R_imm_8(10, 9);
+imm += R_imm_8.read(ba) << 8;
+static BitArrayRange R_imm_4(11, 11);
+imm += R_imm_4.read(ba) << 4;
+static BitArrayRange R_imm_11(12, 12);
+imm += R_imm_11.read(ba) << 11;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cj" << " # " << ba << (" [imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CBEQZ -----------------------------------------------------------------------
+static InstructionDefinition cbeqz_imm_rs1 (
+	ISA16_RV64IMACFD,
+	"cbeqz",
+	(uint16_t) 0xc001,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_5(2, 2);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_1(4, 3);
+imm += R_imm_1.read(ba) << 1;
+static BitArrayRange R_imm_6(6, 5);
+imm += R_imm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_imm_3(11, 10);
+imm += R_imm_3.read(ba) << 3;
+static BitArrayRange R_imm_8(12, 12);
+imm += R_imm_8.read(ba) << 8;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CBEQZ\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] == 0UL) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_5(2, 2);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_1(4, 3);
+imm += R_imm_1.read(ba) << 1;
+static BitArrayRange R_imm_6(6, 5);
+imm += R_imm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_imm_3(11, 10);
+imm += R_imm_3.read(ba) << 3;
+static BitArrayRange R_imm_8(12, 12);
+imm += R_imm_8.read(ba) << 8;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cbeqz" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CBNEZ -----------------------------------------------------------------------
+static InstructionDefinition cbnez_imm_rs1 (
+	ISA16_RV64IMACFD,
+	"cbnez",
+	(uint16_t) 0xe001,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_5(2, 2);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_1(4, 3);
+imm += R_imm_1.read(ba) << 1;
+static BitArrayRange R_imm_6(6, 5);
+imm += R_imm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_imm_3(11, 10);
+imm += R_imm_3.read(ba) << 3;
+static BitArrayRange R_imm_8(12, 12);
+imm += R_imm_8.read(ba) << 8;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CBNEZ\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] != 0UL) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_5(2, 2);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_1(4, 3);
+imm += R_imm_1.read(ba) << 1;
+static BitArrayRange R_imm_6(6, 5);
+imm += R_imm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_imm_3(11, 10);
+imm += R_imm_3.read(ba) << 3;
+static BitArrayRange R_imm_8(12, 12);
+imm += R_imm_8.read(ba) << 8;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cbnez" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSLLI -----------------------------------------------------------------------
+static InstructionDefinition cslli_nzuimm_rs1 (
+	ISA16_RV64IMACFD,
+	"cslli",
+	(uint16_t) 0x02,
+	(uint16_t) 0xf003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 nzuimm = 0;
+static BitArrayRange R_nzuimm_0(6, 2);
+nzuimm += R_nzuimm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSLLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if (nzuimm) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(nzuimm) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rs1 % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 nzuimm = 0;
+static BitArrayRange R_nzuimm_0(6, 2);
+nzuimm += R_nzuimm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cslli" << " # " << ba << (" [nzuimm=" + std::to_string(nzuimm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CLWSP -----------------------------------------------------------------------
+static InstructionDefinition clwsp_uimm_rd (
+	ISA16_RV64IMACFD,
+	"clwsp",
+	(uint16_t) 0x4002,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(3, 2);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_2(6, 4);
+uimm += R_uimm_2.read(ba) << 2;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+static BitArrayRange R_uimm_5(12, 12);
+uimm += R_uimm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CLWSP\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if (rd % 32U) {
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ", (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int32 res = mem_val_0;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(3, 2);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_2(6, 4);
+uimm += R_uimm_2.read(ba) << 2;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+static BitArrayRange R_uimm_5(12, 12);
+uimm += R_uimm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "clwsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CMV -------------------------------------------------------------------------
+static InstructionDefinition cmv_rs2_rd (
+	ISA16_RV64IMACFD,
+	"cmv",
+	(uint16_t) 0x8002,
+	(uint16_t) 0xf003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(6, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CMV\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(6, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cmv" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CJR -------------------------------------------------------------------------
+static InstructionDefinition cjr_rs1 (
+	ISA16_RV64IMACFD,
+	"cjr",
+	(uint16_t) 0x8002,
+	(uint16_t) 0xf07f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CJR\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if (rs1) {
+partInit.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2L;\n";
+} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cjr" << " # " << ba << (" [rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// __reserved_cmv --------------------------------------------------------------
+static InstructionDefinition __reserved_cmv_ (
+	ISA16_RV64IMACFD,
+	"__reserved_cmv",
+	(uint16_t) 0x8002,
+	(uint16_t) 0xffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//__reserved_cmv\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "__reserved_cmv" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CADD ------------------------------------------------------------------------
+static InstructionDefinition cadd_rs2_rd (
+	ISA16_RV64IMACFD,
+	"cadd",
+	(uint16_t) 0x9002,
+	(uint16_t) 0xf003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(6, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CADD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rd % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(6, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cadd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CJALR -----------------------------------------------------------------------
+static InstructionDefinition cjalr_rs1 (
+	ISA16_RV64IMACFD,
+	"cjalr",
+	(uint16_t) 0x9002,
+	(uint16_t) 0xf07f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CJALR\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = new_pc & -2L;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[1U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cjalr" << " # " << ba << (" [rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CEBREAK ---------------------------------------------------------------------
+static InstructionDefinition cebreak_ (
+	ISA16_RV64IMACFD,
+	"cebreak",
+	(uint16_t) 0x9002,
+	(uint16_t) 0xffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CEBREAK\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cebreak" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSWSP -----------------------------------------------------------------------
+static InstructionDefinition cswsp_rs2_uimm (
+	ISA16_RV64IMACFD,
+	"cswsp",
+	(uint16_t) 0xc002,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(6, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(8, 7);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_2(12, 9);
+uimm += R_uimm_2.read(ba) << 2;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSWSP\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[2U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(6, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(8, 7);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_2(12, 9);
+uimm += R_uimm_2.read(ba) << 2;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cswsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// DII -------------------------------------------------------------------------
+static InstructionDefinition dii_ (
+	ISA16_RV64IMACFD,
+	"dii",
+	(uint16_t) 0x00,
+	(uint16_t) 0xffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//DII\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "dii" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
new file mode 100644
index 0000000000..391efc90c7
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -0,0 +1,2913 @@
+/**
+ * Generated on Thu, 03 Nov 2022 15:55:27 +0100.
+ *
+ * This file contains the instruction behavior models of the RV32I
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// LUI -------------------------------------------------------------------------
+static InstructionDefinition lui_rd_imm (
+	ISA32_RV64IMACFD,
+	"lui",
+	(uint32_t) 0x000037,
+	(uint32_t) 0x00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(31, 12);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LUI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(31, 12);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lui" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AUIPC -----------------------------------------------------------------------
+static InstructionDefinition auipc_rd_imm (
+	ISA32_RV64IMACFD,
+	"auipc",
+	(uint32_t) 0x000017,
+	(uint32_t) 0x00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(31, 12);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AUIPC\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(31, 12);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "auipc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// JAL -------------------------------------------------------------------------
+static InstructionDefinition jal_rd_imm (
+	ISA32_RV64IMACFD,
+	"jal",
+	(uint32_t) 0x00006f,
+	(uint32_t) 0x00007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(19, 12);
+imm += R_imm_12.read(ba) << 12;
+static BitArrayRange R_imm_11(20, 20);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(30, 21);
+imm += R_imm_1.read(ba) << 1;
+static BitArrayRange R_imm_20(31, 31);
+imm += R_imm_20.read(ba) << 20;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//JAL\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+}
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint32 imm = 0;
+static BitArrayRange R_imm_12(19, 12);
+imm += R_imm_12.read(ba) << 12;
+static BitArrayRange R_imm_11(20, 20);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(30, 21);
+imm += R_imm_1.read(ba) << 1;
+static BitArrayRange R_imm_20(31, 31);
+imm += R_imm_20.read(ba) << 20;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "jal" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// JALR ------------------------------------------------------------------------
+static InstructionDefinition jalr_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"jalr",
+	(uint32_t) 0x000067,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//JALR\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
+partInit.code() += "if (new_pc % 2UL) {\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+}
+partInit.code() += "cpu->nextPc = new_pc & -2L;\n";
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "jalr" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BEQ -------------------------------------------------------------------------
+static InstructionDefinition beq_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"beq",
+	(uint32_t) 0x000063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BEQ\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "beq" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BNE -------------------------------------------------------------------------
+static InstructionDefinition bne_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"bne",
+	(uint32_t) 0x001063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BNE\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "bne" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BLT -------------------------------------------------------------------------
+static InstructionDefinition blt_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"blt",
+	(uint32_t) 0x004063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BLT\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "blt" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BGE -------------------------------------------------------------------------
+static InstructionDefinition bge_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"bge",
+	(uint32_t) 0x005063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BGE\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "bge" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BLTU ------------------------------------------------------------------------
+static InstructionDefinition bltu_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"bltu",
+	(uint32_t) 0x006063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BLTU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "bltu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// BGEU ------------------------------------------------------------------------
+static InstructionDefinition bgeu_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"bgeu",
+	(uint32_t) 0x007063,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//BGEU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+if (imm % 2U) {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+} else {
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+}
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_11(7, 7);
+imm += R_imm_11.read(ba) << 11;
+static BitArrayRange R_imm_1(11, 8);
+imm += R_imm_1.read(ba) << 1;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(30, 25);
+imm += R_imm_5.read(ba) << 5;
+static BitArrayRange R_imm_12(31, 31);
+imm += R_imm_12.read(ba) << 12;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "bgeu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LB --------------------------------------------------------------------------
+static InstructionDefinition lb_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"lb",
+	(uint32_t) 0x000003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LB\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint8 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lb" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LH --------------------------------------------------------------------------
+static InstructionDefinition lh_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"lh",
+	(uint32_t) 0x001003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LH\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint16 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LW --------------------------------------------------------------------------
+static InstructionDefinition lw_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"lw",
+	(uint32_t) 0x002003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LBU -------------------------------------------------------------------------
+static InstructionDefinition lbu_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"lbu",
+	(uint32_t) 0x004003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LBU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint8 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lbu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LHU -------------------------------------------------------------------------
+static InstructionDefinition lhu_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"lhu",
+	(uint32_t) 0x005003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LHU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint16 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SB --------------------------------------------------------------------------
+static InstructionDefinition sb_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sb",
+	(uint32_t) 0x000023,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SB\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sb" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SH --------------------------------------------------------------------------
+static InstructionDefinition sh_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sh",
+	(uint32_t) 0x001023,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SH\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sh" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SW --------------------------------------------------------------------------
+static InstructionDefinition sw_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sw",
+	(uint32_t) 0x002023,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ADDI ------------------------------------------------------------------------
+static InstructionDefinition addi_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"addi",
+	(uint32_t) 0x000013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ADDI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "addi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLTI ------------------------------------------------------------------------
+static InstructionDefinition slti_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"slti",
+	(uint32_t) 0x002013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLTI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "slti" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLTIU -----------------------------------------------------------------------
+static InstructionDefinition sltiu_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"sltiu",
+	(uint32_t) 0x003013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLTIU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + ")) ? (1U) : (0U);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sltiu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// XORI ------------------------------------------------------------------------
+static InstructionDefinition xori_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"xori",
+	(uint32_t) 0x004013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//XORI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "xori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ORI -------------------------------------------------------------------------
+static InstructionDefinition ori_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"ori",
+	(uint32_t) 0x006013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ORI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ANDI ------------------------------------------------------------------------
+static InstructionDefinition andi_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"andi",
+	(uint32_t) 0x007013,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ANDI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "andi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLLI ------------------------------------------------------------------------
+static InstructionDefinition slli_rd_rs1_shamt (
+	ISA32_RV64IMACFD,
+	"slli",
+	(uint32_t) 0x001013,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(shamt) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRLI ------------------------------------------------------------------------
+static InstructionDefinition srli_rd_rs1_shamt (
+	ISA32_RV64IMACFD,
+	"srli",
+	(uint32_t) 0x005013,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> " + std::to_string(shamt) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRAI ------------------------------------------------------------------------
+static InstructionDefinition srai_rd_rs1_shamt (
+	ISA32_RV64IMACFD,
+	"srai",
+	(uint32_t) 0x40005013,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRAI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> " + std::to_string(shamt) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ADD -------------------------------------------------------------------------
+static InstructionDefinition add_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"add",
+	(uint32_t) 0x000033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ADD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "add" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SUB -------------------------------------------------------------------------
+static InstructionDefinition sub_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sub",
+	(uint32_t) 0x40000033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SUB\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sub" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLL -------------------------------------------------------------------------
+static InstructionDefinition sll_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sll",
+	(uint32_t) 0x001033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLL\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 63UL);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sll" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLT -------------------------------------------------------------------------
+static InstructionDefinition slt_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"slt",
+	(uint32_t) 0x002033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLT\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "slt" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLTU ------------------------------------------------------------------------
+static InstructionDefinition sltu_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sltu",
+	(uint32_t) 0x003033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLTU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (1U) : (0U);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sltu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// XOR -------------------------------------------------------------------------
+static InstructionDefinition xor_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"xor",
+	(uint32_t) 0x004033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//XOR\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "xor" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRL -------------------------------------------------------------------------
+static InstructionDefinition srl_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"srl",
+	(uint32_t) 0x005033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRL\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 63UL);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "srl" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRA -------------------------------------------------------------------------
+static InstructionDefinition sra_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sra",
+	(uint32_t) 0x40005033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRA\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 63UL);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sra" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// OR --------------------------------------------------------------------------
+static InstructionDefinition or_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"or",
+	(uint32_t) 0x006033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//OR\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "or" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AND -------------------------------------------------------------------------
+static InstructionDefinition and_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"and",
+	(uint32_t) 0x007033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AND\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "and" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FENCE -----------------------------------------------------------------------
+static InstructionDefinition fence_rd_rs1_succ_pred_fm (
+	ISA32_RV64IMACFD,
+	"fence",
+	(uint32_t) 0x00000f,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 succ = 0;
+static BitArrayRange R_succ_0(23, 20);
+succ += R_succ_0.read(ba) << 0;
+etiss_uint8 pred = 0;
+static BitArrayRange R_pred_0(27, 24);
+pred += R_pred_0.read(ba) << 0;
+etiss_uint8 fm = 0;
+static BitArrayRange R_fm_0(31, 28);
+fm += R_fm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FENCE\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FENCE[" + std::to_string(0) + "] = " + std::to_string(pred << 4U | succ) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 succ = 0;
+static BitArrayRange R_succ_0(23, 20);
+succ += R_succ_0.read(ba) << 0;
+etiss_uint8 pred = 0;
+static BitArrayRange R_pred_0(27, 24);
+pred += R_pred_0.read(ba) << 0;
+etiss_uint8 fm = 0;
+static BitArrayRange R_fm_0(31, 28);
+fm += R_fm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fence" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | succ=" + std::to_string(succ) + " | pred=" + std::to_string(pred) + " | fm=" + std::to_string(fm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ECALL -----------------------------------------------------------------------
+static InstructionDefinition ecall_ (
+	ISA32_RV64IMACFD,
+	"ecall",
+	(uint32_t) 0x000073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ECALL\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ecall" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// EBREAK ----------------------------------------------------------------------
+static InstructionDefinition ebreak_ (
+	ISA32_RV64IMACFD,
+	"ebreak",
+	(uint32_t) 0x100073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//EBREAK\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ebreak" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// WFI -------------------------------------------------------------------------
+static InstructionDefinition wfi_ (
+	ISA32_RV64IMACFD,
+	"wfi",
+	(uint32_t) 0x10500073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//WFI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->exception = ETISS_RETURNCODE_CPUFINISHED;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "wfi" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
new file mode 100644
index 0000000000..f049adaab0
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -0,0 +1,603 @@
+/**
+ * Generated on Thu, 03 Nov 2022 14:26:19 +0100.
+ *
+ * This file contains the instruction behavior models of the RV32M
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// MUL -------------------------------------------------------------------------
+static InstructionDefinition mul_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mul",
+	(uint32_t) 0x2000033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//MUL\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// MULH ------------------------------------------------------------------------
+static InstructionDefinition mulh_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mulh",
+	(uint32_t) 0x2001033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//MULH\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((res >> 64UL));\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// MULHSU ----------------------------------------------------------------------
+static InstructionDefinition mulhsu_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mulhsu",
+	(uint32_t) 0x2002033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//MULHSU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((res >> 64UL));\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// MULHU -----------------------------------------------------------------------
+static InstructionDefinition mulhu_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mulhu",
+	(uint32_t) 0x2003033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//MULHU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_uint128 res = (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((res >> 64UL));\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// DIV -------------------------------------------------------------------------
+static InstructionDefinition div_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"div",
+	(uint32_t) 0x2004033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//DIV\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
+etiss_uint64 MMIN = 9223372036854775808UL;
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(MMIN) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "}\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1L;\n";
+partInit.code() += "}\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "div" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// DIVU ------------------------------------------------------------------------
+static InstructionDefinition divu_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"divu",
+	(uint32_t) 0x2005033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//DIVU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1L;\n";
+partInit.code() += "}\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "divu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// REM -------------------------------------------------------------------------
+static InstructionDefinition rem_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"rem",
+	(uint32_t) 0x2006033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//REM\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
+etiss_uint64 MMIN = 9223372036854775808UL;
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = 0UL;\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "}\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "}\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "rem" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// REMU ------------------------------------------------------------------------
+static InstructionDefinition remu_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"remu",
+	(uint32_t) 0x2007033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//REMU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "}\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "remu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
new file mode 100644
index 0000000000..c2608173f2
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -0,0 +1,832 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the RV64A
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// AMOSWAPD --------------------------------------------------------------------
+static InstructionDefinition amoswapd_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amoswapd",
+	(uint32_t) 0x800302f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOSWAPD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
+}
+partInit.code() += "etiss_uint64 mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amoswapd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOADDD ---------------------------------------------------------------------
+static InstructionDefinition amoaddd_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amoaddd",
+	(uint32_t) 0x00302f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOADDD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int64 res = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amoaddd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOXORD ---------------------------------------------------------------------
+static InstructionDefinition amoxord_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amoxord",
+	(uint32_t) 0x2000302f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOXORD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int64 res = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amoxord" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOANDD ---------------------------------------------------------------------
+static InstructionDefinition amoandd_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amoandd",
+	(uint32_t) 0x6000302f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOANDD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int64 res = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amoandd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOORD ----------------------------------------------------------------------
+static InstructionDefinition amoord_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amoord",
+	(uint32_t) 0x4000302f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOORD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int64 res = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint64 res2 = (((res) << 64) | (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
+partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amoord" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOMIND ---------------------------------------------------------------------
+static InstructionDefinition amomind_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amomind",
+	(uint32_t) 0x8000302f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOMIND\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int64 res1 = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+}
+partInit.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amomind" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOMAXD ---------------------------------------------------------------------
+static InstructionDefinition amomaxd_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amomaxd",
+	(uint32_t) 0xa000302f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOMAXD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int64 res = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res);\n";
+partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amomaxd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOMINUD --------------------------------------------------------------------
+static InstructionDefinition amominud_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amominud",
+	(uint32_t) 0xc000302f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOMINUD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint64 res = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+}
+partInit.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res);\n";
+partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amominud" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// AMOMAXUD --------------------------------------------------------------------
+static InstructionDefinition amomaxud_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"amomaxud",
+	(uint32_t) 0xe000302f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//AMOMAXUD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint64 res1 = mem_val_0;\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res1);\n";
+}
+partInit.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "amomaxud" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
new file mode 100644
index 0000000000..303955c7af
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -0,0 +1,399 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the RV64D
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// FCVT_L_D --------------------------------------------------------------------
+static InstructionDefinition fcvt_l_d_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_l_d",
+	(uint32_t) 0xc2200053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_L_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), 0U, " + std::to_string(rm) + ");\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_l_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_LU_D -------------------------------------------------------------------
+static InstructionDefinition fcvt_lu_d_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_lu_d",
+	(uint32_t) 0xc2300053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_LU_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), 1U, " + std::to_string(rm) + ");\n";
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_lu_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_D_L --------------------------------------------------------------------
+static InstructionDefinition fcvt_d_l_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_d_l",
+	(uint32_t) 0xd2200053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_D_L\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "], 2U, " + std::to_string(rm) + ");\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_d_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_D_LU -------------------------------------------------------------------
+static InstructionDefinition fcvt_d_lu_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_d_lu",
+	(uint32_t) 0xd2300053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_D_LU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "], 3U, " + std::to_string(rm) + ");\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_d_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMV_X_D ---------------------------------------------------------------------
+static InstructionDefinition fmv_x_d_rd_rs1 (
+	ISA32_RV64IMACFD,
+	"fmv_x_d",
+	(uint32_t) 0xe2000053,
+	(uint32_t) 0xfff0707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMV_X_D\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmv_x_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FMV_D_X ---------------------------------------------------------------------
+static InstructionDefinition fmv_d_x_rd_rs1 (
+	ISA32_RV64IMACFD,
+	"fmv_d_x",
+	(uint32_t) 0xf2000053,
+	(uint32_t) 0xfff0707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FMV_D_X\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fmv_d_x" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
new file mode 100644
index 0000000000..07f5801698
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -0,0 +1,287 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the RV64F
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// FCVT_L_S --------------------------------------------------------------------
+static InstructionDefinition fcvt_l_s_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_l_s",
+	(uint32_t) 0xc0200053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_L_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), 0U, " + std::to_string(rm) + ");\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_l_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_LU_S -------------------------------------------------------------------
+static InstructionDefinition fcvt_lu_s_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_lu_s",
+	(uint32_t) 0xc0300053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_LU_S\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), 1U, " + std::to_string(rm) + ");\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+}
+partInit.code() += "etiss_uint32 flags = fget_flags();\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_lu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_S_L --------------------------------------------------------------------
+static InstructionDefinition fcvt_s_l_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_s_l",
+	(uint32_t) 0xd0200053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_S_L\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "], 2U, " + std::to_string(rm) + ");\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_s_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// FCVT_S_LU -------------------------------------------------------------------
+static InstructionDefinition fcvt_s_lu_rd_rm_rs1 (
+	ISA32_RV64IMACFD,
+	"fcvt_s_lu",
+	(uint32_t) 0xd0300053,
+	(uint32_t) 0xfff0007f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FCVT_S_LU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "], 3U, " + std::to_string(rm) + ");\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rm = 0;
+static BitArrayRange R_rm_0(14, 12);
+rm += R_rm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fcvt_s_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
new file mode 100644
index 0000000000..32e22c7681
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -0,0 +1,695 @@
+/**
+ * Generated on Thu, 03 Nov 2022 15:55:27 +0100.
+ *
+ * This file contains the instruction behavior models of the RV64IC
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// CADDIW ----------------------------------------------------------------------
+static InstructionDefinition caddiw_imm_rs1 (
+	ISA16_RV64IMACFD,
+	"caddiw",
+	(uint16_t) 0x2001,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 imm = 0;
+static BitArrayRange R_imm_0(6, 2);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_imm_5(12, 12);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CADDIW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if ((rs1 % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rs1 % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 imm = 0;
+static BitArrayRange R_imm_0(6, 2);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_imm_5(12, 12);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "caddiw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSRLI -----------------------------------------------------------------------
+static InstructionDefinition csrli_nzuimm_rs1 (
+	ISA16_RV64IMACFD,
+	"csrli",
+	(uint16_t) 0x8001,
+	(uint16_t) 0xec03,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 nzuimm = 0;
+static BitArrayRange R_nzuimm_0(6, 2);
+nzuimm += R_nzuimm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_nzuimm_5(12, 12);
+nzuimm += R_nzuimm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSRLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] >> " + std::to_string(nzuimm) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 nzuimm = 0;
+static BitArrayRange R_nzuimm_0(6, 2);
+nzuimm += R_nzuimm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_nzuimm_5(12, 12);
+nzuimm += R_nzuimm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csrli" << " # " << ba << (" [nzuimm=" + std::to_string(nzuimm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSRAI -----------------------------------------------------------------------
+static InstructionDefinition csrai_shamt_rs1 (
+	ISA16_RV64IMACFD,
+	"csrai",
+	(uint16_t) 0x8401,
+	(uint16_t) 0xec03,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(6, 2);
+shamt += R_shamt_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_shamt_5(12, 12);
+shamt += R_shamt_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSRAI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(6, 2);
+shamt += R_shamt_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_shamt_5(12, 12);
+shamt += R_shamt_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csrai" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSLLI -----------------------------------------------------------------------
+static InstructionDefinition cslli_shamt_rs1 (
+	ISA16_RV64IMACFD,
+	"cslli",
+	(uint16_t) 0x02,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(6, 2);
+shamt += R_shamt_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_shamt_5(12, 12);
+shamt += R_shamt_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSLLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+if (rs1 == 0U) {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+}
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "] << " + std::to_string(shamt) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1], 64);
+		partInit.getAffectedRegisters().add(reg_name[rs1], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(6, 2);
+shamt += R_shamt_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(11, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_shamt_5(12, 12);
+shamt += R_shamt_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cslli" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CLD -------------------------------------------------------------------------
+static InstructionDefinition cld_rd_uimm_rs1 (
+	ISA16_RV64IMACFD,
+	"cld",
+	(uint16_t) 0x6000,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(4, 2);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(6, 5);
+uimm += R_uimm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CLD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_int64)(mem_val_0);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(4, 2);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(6, 5);
+uimm += R_uimm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSD -------------------------------------------------------------------------
+static InstructionDefinition csd_rs2_uimm_rs1 (
+	ISA16_RV64IMACFD,
+	"csd",
+	(uint16_t) 0xe000,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(6, 5);
+uimm += R_uimm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 uimm = 0;
+static BitArrayRange R_uimm_6(6, 5);
+uimm += R_uimm_6.read(ba) << 6;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(9, 7);
+rs1 += R_rs1_0.read(ba) << 0;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSUBW -----------------------------------------------------------------------
+static InstructionDefinition csubw_rs2_rd (
+	ISA16_RV64IMACFD,
+	"csubw",
+	(uint16_t) 0x9c01,
+	(uint16_t) 0xfc63,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSUBW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_uint64)((etiss_int32)(res));\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csubw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CADDW -----------------------------------------------------------------------
+static InstructionDefinition caddw_rs2_rd (
+	ISA16_RV64IMACFD,
+	"caddw",
+	(uint16_t) 0x9c21,
+	(uint16_t) 0xfc63,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CADDW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_uint64)((etiss_int32)(res));\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(4, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(9, 7);
+rd += R_rd_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "caddw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CLDSP -----------------------------------------------------------------------
+static InstructionDefinition cldsp_uimm_rd (
+	ISA16_RV64IMACFD,
+	"cldsp",
+	(uint16_t) 0x6002,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 uimm = 0;
+static BitArrayRange R_uimm_6(4, 2);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_3(6, 5);
+uimm += R_uimm_3.read(ba) << 3;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+static BitArrayRange R_uimm_5(12, 12);
+uimm += R_uimm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CLDSP\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int64 res = mem_val_0;\n";
+if (rd % 32U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[2U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 uimm = 0;
+static BitArrayRange R_uimm_6(4, 2);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_3(6, 5);
+uimm += R_uimm_3.read(ba) << 3;
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+static BitArrayRange R_uimm_5(12, 12);
+uimm += R_uimm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "cldsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSDSP -----------------------------------------------------------------------
+static InstructionDefinition csdsp_rs2_uimm (
+	ISA16_RV64IMACFD,
+	"csdsp",
+	(uint16_t) 0xe002,
+	(uint16_t) 0xe003,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(6, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint16 uimm = 0;
+static BitArrayRange R_uimm_6(9, 7);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSDSP\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[2U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(6, 2);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint16 uimm = 0;
+static BitArrayRange R_uimm_6(9, 7);
+uimm += R_uimm_6.read(ba) << 6;
+static BitArrayRange R_uimm_3(12, 10);
+uimm += R_uimm_3.read(ba) << 3;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csdsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
new file mode 100644
index 0000000000..2147fed13e
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -0,0 +1,1070 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the RV64I
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// LWU -------------------------------------------------------------------------
+static InstructionDefinition lwu_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"lwu",
+	(uint32_t) 0x006003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LWU\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lwu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// LD --------------------------------------------------------------------------
+static InstructionDefinition ld_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"ld",
+	(uint32_t) 0x003003,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SD --------------------------------------------------------------------------
+static InstructionDefinition sd_imm_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sd",
+	(uint32_t) 0x003023,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(11, 7);
+imm += R_imm_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+static BitArrayRange R_imm_5(31, 25);
+imm += R_imm_5.read(ba) << 5;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sd" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLLI ------------------------------------------------------------------------
+static InstructionDefinition slli_rd_rs1_shamt (
+	ISA32_RV64IMACFD,
+	"slli",
+	(uint32_t) 0x001013,
+	(uint32_t) 0xfc00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(25, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(shamt) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(25, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRLI ------------------------------------------------------------------------
+static InstructionDefinition srli_rd_rs1_shamt (
+	ISA32_RV64IMACFD,
+	"srli",
+	(uint32_t) 0x005013,
+	(uint32_t) 0xfc00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(25, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRLI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> " + std::to_string(shamt) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(25, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRAI ------------------------------------------------------------------------
+static InstructionDefinition srai_rd_rs1_shamt (
+	ISA32_RV64IMACFD,
+	"srai",
+	(uint32_t) 0x40005013,
+	(uint32_t) 0xfc00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(25, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRAI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) >> " + std::to_string(shamt) + ";\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(25, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ADDIW -----------------------------------------------------------------------
+static InstructionDefinition addiw_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"addiw",
+	(uint32_t) 0x00001b,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ADDIW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "addiw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLLIW -----------------------------------------------------------------------
+static InstructionDefinition slliw_rd_rs1_shamt (
+	ISA32_RV64IMACFD,
+	"slliw",
+	(uint32_t) 0x00101b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLLIW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) << " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "slliw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRLIW -----------------------------------------------------------------------
+static InstructionDefinition srliw_rd_rs1_shamt (
+	ISA32_RV64IMACFD,
+	"srliw",
+	(uint32_t) 0x00501b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRLIW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "srliw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRAIW -----------------------------------------------------------------------
+static InstructionDefinition sraiw_rd_rs1_shamt (
+	ISA32_RV64IMACFD,
+	"sraiw",
+	(uint32_t) 0x4000501b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRAIW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(sh_val);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 shamt = 0;
+static BitArrayRange R_shamt_0(24, 20);
+shamt += R_shamt_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sraiw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// ADDW ------------------------------------------------------------------------
+static InstructionDefinition addw_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"addw",
+	(uint32_t) 0x00003b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//ADDW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "addw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SUBW ------------------------------------------------------------------------
+static InstructionDefinition subw_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"subw",
+	(uint32_t) 0x4000003b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SUBW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "subw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SLLW ------------------------------------------------------------------------
+static InstructionDefinition sllw_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sllw",
+	(uint32_t) 0x00103b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SLLW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) & 31U;\n";
+partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) << count;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sllw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRLW ------------------------------------------------------------------------
+static InstructionDefinition srlw_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"srlw",
+	(uint32_t) 0x00503b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRLW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) & 31U;\n";
+partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) >> count;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "srlw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SRAW ------------------------------------------------------------------------
+static InstructionDefinition sraw_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sraw",
+	(uint32_t) 0x4000503b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SRAW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) & 31U;\n";
+partInit.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) >> count;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(sh_val);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sraw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
new file mode 100644
index 0000000000..d32b924b94
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -0,0 +1,392 @@
+/**
+ * Generated on Thu, 03 Nov 2022 14:46:05 +0100.
+ *
+ * This file contains the instruction behavior models of the RV64M
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// MULW ------------------------------------------------------------------------
+static InstructionDefinition mulw_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mulw",
+	(uint32_t) 0x200003b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//MULW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]))));\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mulw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// DIVW ------------------------------------------------------------------------
+static InstructionDefinition divw_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"divw",
+	(uint32_t) 0x200403b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//DIVW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
+etiss_int32 MMIN = 2147483648U;
+partInit.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -2147483648L;\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])));\n";
+partInit.code() += "}\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1L;\n";
+partInit.code() += "}\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "divw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// DIVUW -----------------------------------------------------------------------
+static InstructionDefinition divuw_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"divuw",
+	(uint32_t) 0x200503b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//DIVUW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) != 0U) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]))));\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1L;\n";
+partInit.code() += "}\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "divuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// REMW ------------------------------------------------------------------------
+static InstructionDefinition remw_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"remw",
+	(uint32_t) 0x200603b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//REMW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
+etiss_int32 MMIN = 2147483648U;
+partInit.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = 0UL;\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])));\n";
+partInit.code() += "}\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])));\n";
+partInit.code() += "}\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "remw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// REMUW -----------------------------------------------------------------------
+static InstructionDefinition remuw_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"remuw",
+	(uint32_t) 0x200703b,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//REMUW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) != 0U) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]))));\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])));\n";
+partInit.code() += "}\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "remuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
new file mode 100644
index 0000000000..e9cdecbabd
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -0,0 +1,81 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the Zifencei
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// FENCE_I ---------------------------------------------------------------------
+static InstructionDefinition fence_i_rd_rs1_imm (
+	ISA32_RV64IMACFD,
+	"fence_i",
+	(uint32_t) 0x00100f,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//FENCE_I\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FENCE[" + std::to_string(1) + "] = " + std::to_string(imm) + ";\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 imm = 0;
+static BitArrayRange R_imm_0(31, 20);
+imm += R_imm_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "fence_i" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
new file mode 100644
index 0000000000..7f26f154a7
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -0,0 +1,445 @@
+/**
+ * Generated on Thu, 03 Nov 2022 15:55:27 +0100.
+ *
+ * This file contains the instruction behavior models of the tum_csr
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// CSRRW -----------------------------------------------------------------------
+static InstructionDefinition csrrw_rd_rs1_csr (
+	ISA32_RV64IMACFD,
+	"csrrw",
+	(uint32_t) 0x001073,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSRRW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+} else {
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csrrw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSRRS -----------------------------------------------------------------------
+static InstructionDefinition csrrs_rd_rs1_csr (
+	ISA32_RV64IMACFD,
+	"csrrs",
+	(uint32_t) 0x002073,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSRRS\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
+partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+if (rs1 != 0U) {
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | xrs1);\n";
+}
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csrrs" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSRRC -----------------------------------------------------------------------
+static InstructionDefinition csrrc_rd_rs1_csr (
+	ISA32_RV64IMACFD,
+	"csrrc",
+	(uint32_t) 0x003073,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSRRC\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
+partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+if (rs1 != 0U) {
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & ~(xrs1));\n";
+}
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csrrc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSRRWI ----------------------------------------------------------------------
+static InstructionDefinition csrrwi_rd_zimm_csr (
+	ISA32_RV64IMACFD,
+	"csrrwi",
+	(uint32_t) 0x005073,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 zimm = 0;
+static BitArrayRange R_zimm_0(19, 15);
+zimm += R_zimm_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSRRWI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", " + std::to_string((etiss_uint64)(zimm)) + ");\n";
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 zimm = 0;
+static BitArrayRange R_zimm_0(19, 15);
+zimm += R_zimm_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csrrwi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSRRSI ----------------------------------------------------------------------
+static InstructionDefinition csrrsi_rd_zimm_csr (
+	ISA32_RV64IMACFD,
+	"csrrsi",
+	(uint32_t) 0x006073,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 zimm = 0;
+static BitArrayRange R_zimm_0(19, 15);
+zimm += R_zimm_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSRRSI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
+if (zimm != 0U) {
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | " + std::to_string((etiss_uint64)(zimm)) + ");\n";
+}
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 zimm = 0;
+static BitArrayRange R_zimm_0(19, 15);
+zimm += R_zimm_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csrrsi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// CSRRCI ----------------------------------------------------------------------
+static InstructionDefinition csrrci_rd_zimm_csr (
+	ISA32_RV64IMACFD,
+	"csrrci",
+	(uint32_t) 0x007073,
+	(uint32_t) 0x00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 zimm = 0;
+static BitArrayRange R_zimm_0(19, 15);
+zimm += R_zimm_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//CSRRCI\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
+if (zimm != 0U) {
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + ");\n";
+}
+if ((rd % 32U) != 0U) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 zimm = 0;
+static BitArrayRange R_zimm_0(19, 15);
+zimm += R_zimm_0.read(ba) << 0;
+etiss_uint16 csr = 0;
+static BitArrayRange R_csr_0(31, 20);
+csr += R_csr_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "csrrci" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
new file mode 100644
index 0000000000..7ac35e7077
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -0,0 +1,72 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the tum_ret
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// MRET ------------------------------------------------------------------------
+static InstructionDefinition mret_ (
+	ISA32_RV64IMACFD,
+	"mret",
+	(uint32_t) 0x30200073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//MRET\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833];\n";
+partInit.code() += "etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[768];\n";
+partInit.code() += "etiss_uint64 prev_prv = get_field(s, " + std::to_string(6144) + ");\n";
+partInit.code() += "if (prev_prv != 3L) {\n";
+partInit.code() += "s = set_field(s, " + std::to_string(131072) + ", 0U);\n";
+partInit.code() += "}\n";
+partInit.code() += "s = set_field(s, " + std::to_string(8) + ", get_field(s, " + std::to_string(128) + "));\n";
+partInit.code() += "s = set_field(s, " + std::to_string(128) + ", 1U);\n";
+partInit.code() += "s = set_field(s, " + std::to_string(6144) + ", " + std::to_string(3) + ");\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->CSR[" + std::to_string(768) + "] = s;\n";
+partInit.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mret" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
new file mode 100644
index 0000000000..d4bb4d68c7
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -0,0 +1,185 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the tum_rva64
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// LRD -------------------------------------------------------------------------
+static InstructionDefinition lrd_rd_rs1_rl_aq (
+	ISA32_RV64IMACFD,
+	"lrd",
+	(uint32_t) 0x1000302f,
+	(uint32_t) 0xf9f0707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LRD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
+if (rd) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lrd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SCD -------------------------------------------------------------------------
+static InstructionDefinition scd_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"scd",
+	(uint32_t) 0x1800302f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SCD\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "}\n";
+if (rd) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
+}
+partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "scd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
new file mode 100644
index 0000000000..0b2836bd12
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -0,0 +1,185 @@
+/**
+ * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ *
+ * This file contains the instruction behavior models of the tum_rva
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// LRW -------------------------------------------------------------------------
+static InstructionDefinition lrw_rd_rs1_rl_aq (
+	ISA32_RV64IMACFD,
+	"lrw",
+	(uint32_t) 0x1000202f,
+	(uint32_t) 0xf9f0707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//LRW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
+if (rd) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+}
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "lrw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// SCW -------------------------------------------------------------------------
+static InstructionDefinition scw_rd_rs1_rs2_rl_aq (
+	ISA32_RV64IMACFD,
+	"scw",
+	(uint32_t) 0x1800202f,
+	(uint32_t) 0xf800707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//SCW\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "}\n";
+if (rd) {
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
+}
+partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+etiss_uint8 rl = 0;
+static BitArrayRange R_rl_0(25, 25);
+rl += R_rl_0.read(ba) << 0;
+etiss_uint8 aq = 0;
+static BitArrayRange R_aq_0(26, 26);
+aq += R_aq_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "scw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);

From ba6a20ca34c11e530831cfe21868ab468198075c Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Mon, 7 Nov 2022 21:48:40 +0100
Subject: [PATCH 16/44] update arch

---
 ArchImpl/RV32IMACFD/CMakeLists.txt            |  3 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         | 14 ++-
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 20 ++---
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 67 +++-----------
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    | 16 ++--
 .../RV32IMACFD_tum_semihostingInstr.cpp       | 89 +++++++++++++++++++
 ArchImpl/RV64IMACFD/CMakeLists.txt            |  3 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h         | 10 ++-
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp | 49 +---------
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    |  2 +-
 .../RV64IMACFD_tum_semihostingInstr.cpp       | 89 +++++++++++++++++++
 13 files changed, 235 insertions(+), 131 deletions(-)
 create mode 100644 ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp

diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index 85e34659ad..5f99bac347 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Mon, 11 Jul 2022 15:43:25 +0200.
+# Generated on Fri, 04 Nov 2022 23:33:07 +0100.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
@@ -21,6 +21,7 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFD_tum_retInstr.cpp
 	RV32IMACFD_RV32AInstr.cpp
 	RV32IMACFD_tum_rvaInstr.cpp
+	RV32IMACFD_tum_semihostingInstr.cpp
 )
 
 add_custom_command(
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index 909def9296..3f01f4914b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -229,10 +229,20 @@ code = 13;
 code = 7;
 } else if (cause == -15) {
 code = 15;
+} else if (cause == -7) {
+code = 1;
 } else {
 code = 2;
 }
-raise(cpu, system, plugin_pointers, 0U, code);
+cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
 }
 #endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint8 etiss_semihost_enabled();
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
+#endif
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index e80cf6a739..df9c8e162d 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -52,7 +52,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if (imm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + ";\n";
 } else {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -548,7 +548,7 @@ imm += R_imm_17.read(ba) << 17;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
 if (imm == 0U) {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
@@ -621,7 +621,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if (nzimm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[2U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
 } else {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -684,7 +684,7 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1479,7 +1479,7 @@ partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_p
 partInit.code() += "etiss_int32 res = mem_val_0;\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
 } else {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
@@ -1606,7 +1606,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) +
 if (rs1) {
 partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2;\n";
 } else {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
@@ -1658,7 +1658,7 @@ static InstructionDefinition __reserved_cmv_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1824,7 +1824,7 @@ static InstructionDefinition cebreak_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1939,7 +1939,7 @@ static InstructionDefinition dii_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 2d4bff9aa3..bf49bc7371 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -172,7 +172,7 @@ imm += R_imm_20.read(ba) << 20;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 if (imm % 2U) {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n";
@@ -249,7 +249,7 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
 partInit.code() += "if (new_pc % 2U) {\n";
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
 if ((rd % 32U) != 0U) {
@@ -331,7 +331,7 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
@@ -416,7 +416,7 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
@@ -501,7 +501,7 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
 if (imm % 2U) {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
@@ -586,7 +586,7 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
 if (imm % 2U) {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
@@ -671,7 +671,7 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
@@ -756,7 +756,7 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
 if (imm % 2U) {
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
@@ -2794,7 +2794,7 @@ static InstructionDefinition ecall_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -2818,53 +2818,6 @@ ss << "ecall" << " # " << ba << (" []");
 	}
 );
 
-// EBREAK ----------------------------------------------------------------------
-static InstructionDefinition ebreak_ (
-	ISA32_RV32IMACFD,
-	"ebreak",
-	(uint32_t) 0x100073,
-	(uint32_t) 0xffffffff,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
-
-		partInit.code() = std::string("//EBREAK\n");
-
-// -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "raise(cpu, system, plugin_pointers, 0U, 3U);\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "ebreak" << " # " << ba << (" []");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
 // WFI -------------------------------------------------------------------------
 static InstructionDefinition wfi_ (
 	ISA32_RV32IMACFD,
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index 52cdf6c3de..d721c311cc 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
@@ -49,10 +49,10 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
 } else {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
 }
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -122,7 +122,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if (rs1 != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | xrs1);\n";
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | xrs1);\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
@@ -195,7 +195,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) +
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
 if (rs1 != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & ~(xrs1));\n";
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & ~(xrs1));\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
@@ -266,7 +266,7 @@ csr += R_csr_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", " + std::to_string((etiss_uint32)(zimm)) + ");\n";
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", " + std::to_string((etiss_uint32)(zimm)) + ");\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
 }
@@ -336,7 +336,7 @@ csr += R_csr_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 if (zimm != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | " + std::to_string((etiss_uint32)(zimm)) + ");\n";
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | " + std::to_string((etiss_uint32)(zimm)) + ");\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
@@ -407,7 +407,7 @@ csr += R_csr_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
 if (zimm != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + ");\n";
+partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + ");\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
new file mode 100644
index 0000000000..cc21d90ea4
--- /dev/null
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -0,0 +1,89 @@
+/**
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ *
+ * This file contains the instruction behavior models of the tum_semihosting
+ * instruction set for the RV32IMACFD core architecture.
+ */
+
+#include "RV32IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV32IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// EBREAK ----------------------------------------------------------------------
+static InstructionDefinition ebreak_ (
+	ISA32_RV32IMACFD,
+	"ebreak",
+	(uint32_t) 0x100073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//EBREAK\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "if (etiss_semihost_enabled()) {\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4U) + ", (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0U) + ", (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
+partInit.code() += "etiss_uint32 mem_val_2;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4U) + ", (etiss_uint8*)&mem_val_2, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
+partInit.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
+partInit.code() += "etiss_uint32 operation = *((RV32IMACFD*)cpu)->X[10U];\n";
+partInit.code() += "etiss_uint32 parameter = *((RV32IMACFD*)cpu)->X[11U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[10U] = (etiss_int32)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(32) + ", operation, parameter));\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + ");\n";
+partInit.code() += "}\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + ");\n";
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[10U], 32);
+		partInit.getRegisterDependencies().add(reg_name[11U], 32);
+		partInit.getAffectedRegisters().add(reg_name[10U], 32);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ebreak" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt
index 17af8c3370..1fd468800d 100644
--- a/ArchImpl/RV64IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV64IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Thu, 03 Nov 2022 14:26:19 +0100.
+# Generated on Fri, 04 Nov 2022 23:37:47 +0100.
 #
 # This file contains the CMake build info for the RV64IMACFD core architecture.
 
@@ -27,6 +27,7 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV64IMACFD_tum_retInstr.cpp
 	RV64IMACFD_tum_rvaInstr.cpp
 	RV64IMACFD_tum_rva64Instr.cpp
+	RV64IMACFD_tum_semihostingInstr.cpp
 )
 
 add_custom_command(
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index 0c17d2790f..41309a5069 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 03 Nov 2022 15:55:27 +0100.
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
  *
  * This file contains the function macros for the RV64IMACFD core architecture.
  */
@@ -237,4 +237,12 @@ code = 2;
 cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
 }
 #endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_uint8 etiss_semihost_enabled();
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
+#endif
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index 79d88627d4..e64b444fbb 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 03 Nov 2022 15:55:27 +0100.
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index 391efc90c7..ab0e392b4f 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 03 Nov 2022 15:55:27 +0100.
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
@@ -2818,53 +2818,6 @@ ss << "ecall" << " # " << ba << (" []");
 	}
 );
 
-// EBREAK ----------------------------------------------------------------------
-static InstructionDefinition ebreak_ (
-	ISA32_RV64IMACFD,
-	"ebreak",
-	(uint32_t) 0x100073,
-	(uint32_t) 0xffffffff,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
-
-		partInit.code() = std::string("//EBREAK\n");
-
-// -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "ebreak" << " # " << ba << (" []");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
 // WFI -------------------------------------------------------------------------
 static InstructionDefinition wfi_ (
 	ISA32_RV64IMACFD,
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index 32e22c7681..203761484d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 03 Nov 2022 15:55:27 +0100.
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index 7f26f154a7..1dd9e8228d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 03 Nov 2022 15:55:27 +0100.
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
new file mode 100644
index 0000000000..031ef5022e
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -0,0 +1,89 @@
+/**
+ * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ *
+ * This file contains the instruction behavior models of the tum_semihosting
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// EBREAK ----------------------------------------------------------------------
+static InstructionDefinition ebreak_ (
+	ISA32_RV64IMACFD,
+	"ebreak",
+	(uint32_t) 0x100073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+
+		partInit.code() = std::string("//EBREAK\n");
+
+// -----------------------------------------------------------------------------
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "if (etiss_semihost_enabled()) {\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4UL) + ", (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0UL) + ", (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
+partInit.code() += "etiss_uint32 mem_val_2;\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4UL) + ", (etiss_uint8*)&mem_val_2, 4);\n";
+partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
+partInit.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
+partInit.code() += "etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10U];\n";
+partInit.code() += "etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11U];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[10U] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(64) + ", operation, parameter));\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + ");\n";
+partInit.code() += "}\n";
+partInit.code() += "}\n";
+partInit.code() += " else {\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + ");\n";
+partInit.code() += "}\n";
+partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+
+		partInit.getRegisterDependencies().add(reg_name[10U], 64);
+		partInit.getRegisterDependencies().add(reg_name[11U], 64);
+		partInit.getAffectedRegisters().add(reg_name[10U], 64);
+		partInit.getAffectedRegisters().add("instructionPointer", 32);
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ebreak" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);

From 4d408f5d12b71b078567dfc5e08ed9b30d328cf1 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Mon, 14 Nov 2022 18:46:48 +0100
Subject: [PATCH 17/44] update arch files

---
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         |  96 +++---
 ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h       |   2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp       |   2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp | 155 ++++++----
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     |  46 +--
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp | 190 +++++++-----
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     |  46 +--
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp | 238 ++++++++-------
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 187 +++++++-----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 278 +++++++++++-------
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp |  74 ++---
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |   7 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    |  64 ++--
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    |  17 +-
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |  26 +-
 .../RV32IMACFD_tum_semihostingInstr.cpp       |  29 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h         |  96 +++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp | 155 ++++++----
 .../RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp     |  46 +--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp | 190 +++++++-----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp | 238 ++++++++-------
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     | 182 +++++++-----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp | 278 +++++++++++-------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp |  74 ++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp | 155 ++++++----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp |  36 ++-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp |  30 +-
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     |  85 +++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp | 119 +++++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp |  51 ++--
 .../RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp   |   7 +-
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    |  64 ++--
 .../RV64IMACFD/RV64IMACFD_tum_retInstr.cpp    |  17 +-
 .../RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp  |  26 +-
 .../RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp    |  26 +-
 .../RV64IMACFD_tum_semihostingInstr.cpp       |  29 +-
 36 files changed, 1984 insertions(+), 1377 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index 3f01f4914b..47821e84ee 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -131,6 +131,52 @@ static inline etiss_uint64 unbox_d(etiss_uint64);
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint64 fclass_d(etiss_uint64);
 #endif
+static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
+{
+return (reg & mask) / (mask & ~((mask << 1UL)));
+}
+static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
+{
+return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1UL)))) & mask));
+}
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
+{
+cpu->return_pending = 1;
+etiss_uint32 epc = cpu->instructionPointer;
+cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773] & -2);
+*((RV32IMACFD*)cpu)->CSR[833] = epc;
+*((RV32IMACFD*)cpu)->CSR[834] = mcause;
+etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[768];
+s = set_field(s, 128, get_field(s, 8));
+s = set_field(s, 6144, ((RV32IMACFD*)cpu)->PRIV);
+s = set_field(s, 8, 0U);
+*((RV32IMACFD*)cpu)->CSR[768] = s;
+((RV32IMACFD*)cpu)->PRIV = (3) & 0x7;
+}
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
+{
+etiss_int32 code = 0U;
+if (cause == -5) {
+code = 5;
+} else if (cause == -14) {
+code = 13;
+} else if (cause == -6) {
+code = 7;
+} else if (cause == -15) {
+code = 15;
+} else if (cause == -7) {
+code = 1;
+} else {
+code = 2;
+}
+cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
+}
+#endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
@@ -186,57 +232,11 @@ if (csr == 1) {
 *((RV32IMACFD*)cpu)->CSR[3] = val & 255U;
 } else if (csr == 768) {
 *((RV32IMACFD*)cpu)->CSR[768] = val & 136U;
-} else {
+} else if (csr != 769) {
 *((RV32IMACFD*)cpu)->CSR[csr] = val;
 }
 }
 #endif
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
-{
-return (reg & mask) / (mask & ~((mask << 1UL)));
-}
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
-{
-return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1UL)))) & mask));
-}
-
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
-{
-cpu->return_pending = 1;
-etiss_uint32 epc = cpu->instructionPointer;
-cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773] & -2);
-*((RV32IMACFD*)cpu)->CSR[833] = epc;
-*((RV32IMACFD*)cpu)->CSR[834] = mcause;
-etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[768];
-s = set_field(s, 128, get_field(s, 8));
-s = set_field(s, 6144, ((RV32IMACFD*)cpu)->PRIV);
-s = set_field(s, 8, 0U);
-*((RV32IMACFD*)cpu)->CSR[768] = s;
-((RV32IMACFD*)cpu)->PRIV = (3) & 0x7;
-}
-#endif
-
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
-{
-etiss_int32 code = 0U;
-if (cause == -5) {
-code = 5;
-} else if (cause == -14) {
-code = 13;
-} else if (cause == -6) {
-code = 7;
-} else if (cause == -15) {
-code = 15;
-} else if (cause == -7) {
-code = 1;
-} else {
-code = 2;
-}
-cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
-}
-#endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint8 etiss_semihost_enabled();
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
index 833db0470a..08b9fd2ec1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the GDBCore adapter for the RV32IMACFD core architecture.
  *
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
index bd9f697eb8..45c17e16cf 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index e75161ef5a..3f94d6ddaa 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -51,17 +51,22 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOSWAPW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n";
 }
-partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -140,19 +145,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOADDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -231,19 +241,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOXORW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -322,19 +337,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOANDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -413,19 +433,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOORW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -504,19 +529,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMINW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -595,19 +625,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMAXW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -686,19 +721,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMINUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 > *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 res2 = (res1 > *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -777,19 +817,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMAXUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 res2 = (res1 < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index a5070252fd..aa7e86781e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -47,13 +47,16 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = res;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -122,11 +125,14 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -194,13 +200,16 @@ uimm += R_uimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CFLDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -265,11 +274,14 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFSDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index f198c4c102..93d9529ece 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:21:19 +0200.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -45,13 +45,16 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//FLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -118,11 +121,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//FSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -195,11 +201,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -274,11 +281,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -353,11 +361,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -432,11 +441,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -508,11 +518,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -581,11 +592,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -654,11 +666,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMUL_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -727,11 +740,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FDIV_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -797,11 +811,12 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FSQRT_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -864,9 +879,10 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJ_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -929,9 +945,10 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJN_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -994,9 +1011,10 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJX_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) & 9223372036854775808UL);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) & 9223372036854775808UL);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1059,11 +1077,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMIN_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 0U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 0U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1126,11 +1145,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMAX_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 1U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 1U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1193,9 +1213,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L + res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L + res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1258,9 +1279,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1323,14 +1345,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FEQ_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 0U);\n";
+partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 0U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1394,14 +1417,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLT_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 2U);\n";
+partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 2U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1465,14 +1489,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLE_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 1U);\n";
+partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 1U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1533,8 +1558,9 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCLASS_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1595,14 +1621,15 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_W_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_int32 res = 0U;\n";
-partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 0U, " + std::to_string(rm) + ");\n";
+partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 0U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1666,14 +1693,15 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_WU_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 1U, " + std::to_string(rm) + ");\n";
+partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 1U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(res));\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1737,9 +1765,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1803,9 +1832,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_WU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 61856fd673..ee0c988ea2 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -49,13 +49,16 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = -4294967296L | res;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = -4294967296L | res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -128,11 +131,14 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -202,13 +208,16 @@ uimm += R_uimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CFLWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | res;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -273,11 +282,14 @@ uimm += R_uimm_2.read(ba) << 2;
 		partInit.code() = std::string("//CFSWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 09e9d2c23e..921058209e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:21:19 +0200.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -45,13 +45,16 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//FLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -118,11 +121,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//FSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -195,11 +201,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -274,11 +281,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -353,14 +361,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -435,14 +444,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -514,13 +524,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -589,13 +600,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -664,13 +676,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMUL_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -739,13 +752,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FDIV_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -811,12 +825,13 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FSQRT_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -879,11 +894,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJ_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -946,11 +962,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJN_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1013,11 +1030,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJX_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1080,13 +1098,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMIN_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1149,13 +1168,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMAX_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1218,15 +1238,16 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_W_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_int32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + ");\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1290,15 +1311,16 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_WU_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + ");\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((etiss_int32)(res));\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)((etiss_int32)(res));\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1362,16 +1384,17 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FEQ_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "res = fcmp_s(frs1, frs2, 0U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1435,16 +1458,17 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLT_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "res = fcmp_s(frs1, frs2, 2U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1508,16 +1532,17 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLE_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "res = fcmp_s(frs1, frs2, 1U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1578,12 +1603,13 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCLASS_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
+partInit.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1644,9 +1670,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1710,9 +1737,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_WU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1773,10 +1801,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FMV_X_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1834,8 +1863,9 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FMV_W_X\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index df9c8e162d..f6745627ec 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -48,13 +48,15 @@ imm += R_imm_4.read(ba) << 4;
 		partInit.code() = std::string("//CADDI4SPN\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (imm) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + "U;\n";
 } else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -125,12 +127,15 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_int32)(mem_val_0);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -204,11 +209,14 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -277,10 +285,11 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//CADDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if ((rs1 % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -340,7 +349,8 @@ nzimm += R_nzimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CNOP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -407,9 +417,10 @@ imm += R_imm_11.read(ba) << 11;
 		partInit.code() = std::string("//CJAL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -481,10 +492,11 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//CLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -546,14 +558,16 @@ imm += R_imm_17.read(ba) << 17;
 		partInit.code() = std::string("//CLUI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (imm == 0U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -617,13 +631,15 @@ nzimm += R_nzimm_9.read(ba) << 9;
 		partInit.code() = std::string("//CADDI16SP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (nzimm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[2U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
 } else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -683,9 +699,11 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//__reserved_clui\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -738,8 +756,9 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(shamt) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -798,10 +817,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (shamt) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -862,8 +882,9 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//CANDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -924,8 +945,9 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CSUB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -985,8 +1007,9 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CXOR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1046,8 +1069,9 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//COR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1107,8 +1131,9 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CAND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1179,8 +1204,9 @@ imm += R_imm_11.read(ba) << 11;
 		partInit.code() = std::string("//CJ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1257,10 +1283,11 @@ imm += R_imm_8.read(ba) << 8;
 		partInit.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] == 0U) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] == 0U) {\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1335,10 +1362,11 @@ imm += R_imm_8.read(ba) << 8;
 		partInit.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] != 0U) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] != 0U) {\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1405,10 +1433,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (nzuimm) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(nzuimm) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(nzuimm) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1471,16 +1500,19 @@ uimm += R_uimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CLWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (rd % 32U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ", (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = mem_val_0;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res);\n";
 } else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1543,10 +1575,11 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CMV\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1602,12 +1635,13 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CJR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (rs1) {
-partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2;\n";
+partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & -2;\n";
 } else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1657,9 +1691,11 @@ static InstructionDefinition __reserved_cmv_ (
 		partInit.code() = std::string("//__reserved_cmv\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1709,10 +1745,11 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CADD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1769,10 +1806,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CJALR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 partInit.code() += "cpu->nextPc = new_pc & -2;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1823,8 +1861,9 @@ static InstructionDefinition cebreak_ (
 		partInit.code() = std::string("//CEBREAK\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1878,11 +1917,14 @@ uimm += R_uimm_2.read(ba) << 2;
 		partInit.code() = std::string("//CSWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1938,8 +1980,9 @@ static InstructionDefinition dii_ (
 		partInit.code() = std::string("//DII\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index bf49bc7371..81e4d9aa1a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -42,10 +42,11 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//LUI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string((etiss_uint32)(((etiss_int32)(imm)))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string((etiss_uint32)(((etiss_int32)(imm)))) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -103,10 +104,11 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//AUIPC\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -170,15 +172,16 @@ imm += R_imm_20.read(ba) << 20;
 		partInit.code() = std::string("//JAL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 }
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -246,17 +249,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//JALR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
 partInit.code() += "if (new_pc % 2U) {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 }
 partInit.code() += "cpu->nextPc = new_pc & -2;\n";
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -328,16 +332,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -413,16 +418,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -498,16 +504,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -583,16 +590,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -668,16 +676,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -753,16 +762,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -832,15 +842,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -906,15 +919,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -980,15 +996,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1054,15 +1073,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LBU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1128,15 +1150,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LHU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1204,11 +1229,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//SB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1278,11 +1306,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//SH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1352,11 +1383,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//SW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1424,10 +1458,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//ADDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1492,10 +1527,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//SLTI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1560,10 +1596,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//SLTIU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ")) ? (1U) : (0U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U)) ? (1U) : (0U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1628,10 +1665,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//XORI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1696,10 +1734,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//ORI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1764,10 +1803,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//ANDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1832,10 +1872,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1900,10 +1941,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1968,10 +2010,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2036,10 +2079,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//ADD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2105,10 +2149,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SUB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2174,10 +2219,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SLL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2243,10 +2289,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SLT\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (1U) : (0U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2312,10 +2359,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SLTU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (1U) : (0U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (1U) : (0U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2381,10 +2429,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//XOR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2450,10 +2499,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SRL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2519,10 +2569,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SRA\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2588,10 +2639,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//OR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2657,10 +2709,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//AND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2732,8 +2785,9 @@ fm += R_fm_0.read(ba) << 0;
 		partInit.code() = std::string("//FENCE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(0) + "] = " + std::to_string(pred << 4U | succ) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(0) + "U] = " + std::to_string(pred << 4U | succ) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2793,8 +2847,9 @@ static InstructionDefinition ecall_ (
 		partInit.code() = std::string("//ECALL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -2840,8 +2895,9 @@ static InstructionDefinition wfi_ (
 		partInit.code() = std::string("//WFI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "cpu->exception = ETISS_RETURNCODE_CPUFINISHED;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index 27afcb250a..bf99ab720a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 19:26:52 +0200.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
@@ -45,11 +45,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MUL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n";
+partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -115,11 +116,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MULH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n";
+partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)((res >> 32UL));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -185,11 +187,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MULHSU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n";
+partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)((res >> 32UL));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -255,11 +258,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MULHU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n";
+partInit.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)((res >> 32UL));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -325,21 +329,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//DIV\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
 etiss_uint32 MMIN = 2147483648U;
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(MMIN) + ";\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(MMIN) + "U;\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1;\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -405,15 +410,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//DIVU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1;\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -479,21 +485,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//REM\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
 etiss_uint32 MMIN = 2147483648U;
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = 0U;\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = 0U;\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -559,15 +566,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//REMU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index eaf6234b81..89ea4a1ab8 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
@@ -46,8 +46,9 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(1) + "] = " + std::to_string(imm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(1) + "U] = " + std::to_string(imm) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index d721c311cc..22821bc140 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
@@ -45,15 +45,16 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 } else {
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -118,15 +119,16 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRS\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if (rs1 != 0U) {
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | xrs1);\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | xrs1);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -191,15 +193,16 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRC\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if (rs1 != 0U) {
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & ~(xrs1));\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & ~(xrs1));\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -264,12 +267,13 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRWI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", " + std::to_string((etiss_uint32)(zimm)) + ");\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, " + std::to_string((etiss_uint32)(zimm)) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -333,14 +337,15 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRSI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
 if (zimm != 0U) {
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | " + std::to_string((etiss_uint32)(zimm)) + ");\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | " + std::to_string((etiss_uint32)(zimm)) + "U);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -404,14 +409,15 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRCI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
 if (zimm != 0U) {
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + ");\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "U);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index cccbefbde1..df141fbc4b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:21:19 +0200.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
@@ -36,18 +36,19 @@ static InstructionDefinition mret_ (
 		partInit.code() = std::string("//MRET\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833];\n";
 partInit.code() += "etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[768];\n";
-partInit.code() += "etiss_uint32 prev_prv = get_field(s, " + std::to_string(6144) + ");\n";
+partInit.code() += "etiss_uint32 prev_prv = get_field(s, " + std::to_string(6144) + "U);\n";
 partInit.code() += "if (prev_prv != 3) {\n";
-partInit.code() += "s = set_field(s, " + std::to_string(131072) + ", 0U);\n";
+partInit.code() += "s = set_field(s, " + std::to_string(131072) + "U, 0U);\n";
 partInit.code() += "}\n";
-partInit.code() += "s = set_field(s, " + std::to_string(8) + ", get_field(s, " + std::to_string(128) + "));\n";
-partInit.code() += "s = set_field(s, " + std::to_string(128) + ", 1U);\n";
-partInit.code() += "s = set_field(s, " + std::to_string(6144) + ", " + std::to_string(3) + ");\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768) + "] = s;\n";
+partInit.code() += "s = set_field(s, " + std::to_string(8) + "U, get_field(s, " + std::to_string(128) + "U));\n";
+partInit.code() += "s = set_field(s, " + std::to_string(128) + "U, 1U);\n";
+partInit.code() += "s = set_field(s, " + std::to_string(6144) + "U, " + std::to_string(3) + "U);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768) + "U] = s;\n";
 partInit.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 328da999cf..7ff52ecfc2 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 25 Aug 2022 14:20:44 +0200.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -48,16 +48,19 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//LRW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";
 if (rd) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -132,17 +135,20 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//SCW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) {\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "}\n";
 if (rd) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
 }
 partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index cc21d90ea4..dfb0e566be 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
@@ -36,32 +36,39 @@ static InstructionDefinition ebreak_ (
 		partInit.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "if (etiss_semihost_enabled()) {\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4U) + ", (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4U) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0U) + ", (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0U) + "U, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
 partInit.code() += "etiss_uint32 mem_val_2;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4U) + ", (etiss_uint8*)&mem_val_2, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4U) + "U, (etiss_uint8*)&mem_val_2, 4);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
 partInit.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
 partInit.code() += "etiss_uint32 operation = *((RV32IMACFD*)cpu)->X[10U];\n";
 partInit.code() += "etiss_uint32 parameter = *((RV32IMACFD*)cpu)->X[11U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[10U] = (etiss_int32)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(32) + ", operation, parameter));\n";
+partInit.code() += "*((RV32IMACFD*)cpu)->X[10U] = (etiss_int32)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(32) + "U, operation, parameter));\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + ");\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + ");\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index 41309a5069..504b1a6e88 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
  *
  * This file contains the function macros for the RV64IMACFD core architecture.
  */
@@ -131,6 +131,52 @@ static inline etiss_uint64 unbox_d(etiss_uint64);
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint64 fclass_d(etiss_uint64);
 #endif
+static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
+{
+return (reg & mask) / (mask & ~((mask << 1UL)));
+}
+static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
+{
+return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1UL)))) & mask));
+}
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
+{
+cpu->return_pending = 1;
+etiss_uint64 epc = cpu->instructionPointer;
+cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773] & -2L);
+*((RV64IMACFD*)cpu)->CSR[833] = epc;
+*((RV64IMACFD*)cpu)->CSR[834] = mcause;
+etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[768];
+s = set_field(s, 128, get_field(s, 8));
+s = set_field(s, 6144, ((RV64IMACFD*)cpu)->PRIV);
+s = set_field(s, 8, 0U);
+*((RV64IMACFD*)cpu)->CSR[768] = s;
+((RV64IMACFD*)cpu)->PRIV = (3) & 0x7;
+}
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
+{
+etiss_int32 code = 0U;
+if (cause == -5) {
+code = 5;
+} else if (cause == -14) {
+code = 13;
+} else if (cause == -6) {
+code = 7;
+} else if (cause == -15) {
+code = 15;
+} else if (cause == -7) {
+code = 1;
+} else {
+code = 2;
+}
+cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
+}
+#endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
@@ -186,57 +232,11 @@ if (csr == 1) {
 *((RV64IMACFD*)cpu)->CSR[3] = val & 255UL;
 } else if (csr == 768) {
 *((RV64IMACFD*)cpu)->CSR[768] = val & 136UL;
-} else {
+} else if (csr != 769) {
 *((RV64IMACFD*)cpu)->CSR[csr] = val;
 }
 }
 #endif
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
-{
-return (reg & mask) / (mask & ~((mask << 1UL)));
-}
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
-{
-return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1UL)))) & mask));
-}
-
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
-{
-cpu->return_pending = 1;
-etiss_uint64 epc = cpu->instructionPointer;
-cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773] & -2L);
-*((RV64IMACFD*)cpu)->CSR[833] = epc;
-*((RV64IMACFD*)cpu)->CSR[834] = mcause;
-etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[768];
-s = set_field(s, 128, get_field(s, 8));
-s = set_field(s, 6144, ((RV64IMACFD*)cpu)->PRIV);
-s = set_field(s, 8, 0U);
-*((RV64IMACFD*)cpu)->CSR[768] = s;
-((RV64IMACFD*)cpu)->PRIV = (3) & 0x7;
-}
-#endif
-
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
-{
-etiss_int32 code = 0U;
-if (cause == -5) {
-code = 5;
-} else if (cause == -14) {
-code = 13;
-} else if (cause == -6) {
-code = 7;
-} else if (cause == -15) {
-code = 15;
-} else if (cause == -7) {
-code = 1;
-} else {
-code = 2;
-}
-cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
-}
-#endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint8 etiss_semihost_enabled();
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index fd282e815a..2686737236 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
@@ -51,17 +51,22 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOSWAPW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
 }
-partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -140,19 +145,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOADDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -231,19 +241,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOXORW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -322,19 +337,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOANDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -413,19 +433,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOORW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -504,19 +529,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMINW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -595,19 +625,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMAXW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -686,19 +721,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMINUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 res2 = (res1 > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -777,19 +817,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMAXUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint32 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
 partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index 5daa8d428e..2c3100bd96 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
@@ -47,13 +47,16 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = res;\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -122,11 +125,14 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -194,13 +200,16 @@ uimm += R_uimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CFLDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -265,11 +274,14 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CFSDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index 90e5a5a4ca..0e751b3668 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
@@ -45,13 +45,16 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//FLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -118,11 +121,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//FSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -195,11 +201,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -274,11 +281,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -353,11 +361,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -432,11 +441,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -508,11 +518,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -581,11 +592,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -654,11 +666,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMUL_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -727,11 +740,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FDIV_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -797,11 +811,12 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FSQRT_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -864,9 +879,10 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJ_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1)) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1)) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -929,9 +945,10 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJN_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1))) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1))) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -994,9 +1011,10 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJX_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) & 9223372036854775808UL);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) & 9223372036854775808UL);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1059,11 +1077,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMIN_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 0U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 0U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1126,11 +1145,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMAX_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 1U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 1U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1193,9 +1213,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L + res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L + res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1258,9 +1279,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1323,14 +1345,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FEQ_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 0U);\n";
+partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 0U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1394,14 +1417,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLT_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 2U);\n";
+partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 2U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1465,14 +1489,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLE_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 1U);\n";
+partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 1U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1533,8 +1558,9 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCLASS_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1595,14 +1621,15 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_W_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_int32 res = 0U;\n";
-partInit.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 0U, " + std::to_string(rm) + ");\n";
+partInit.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 0U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1666,14 +1693,15 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_WU_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 1U, " + std::to_string(rm) + ");\n";
+partInit.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 1U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(res));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1737,9 +1765,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1803,9 +1832,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_WU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index 084e6b9a01..892a91fc0c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
@@ -45,13 +45,16 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//FLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -118,11 +121,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//FSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -195,11 +201,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -274,11 +281,12 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -353,14 +361,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -435,14 +444,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		partInit.code() = std::string("//FNMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -514,13 +524,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -589,13 +600,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -664,13 +676,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMUL_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -739,13 +752,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FDIV_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
-partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -811,12 +825,13 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FSQRT_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -879,11 +894,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJ_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -946,11 +962,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJN_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1013,11 +1030,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FSGNJX_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1080,13 +1098,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMIN_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1149,13 +1168,14 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FMAX_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1218,15 +1238,16 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_W_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_int32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + ");\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1290,15 +1311,16 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_WU_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + ");\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(res));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1362,16 +1384,17 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FEQ_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "res = fcmp_s(frs1, frs2, 0U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1435,16 +1458,17 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLT_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "res = fcmp_s(frs1, frs2, 2U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1508,16 +1532,17 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//FLE_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n";
+partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "res = fcmp_s(frs1, frs2, 1U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1578,12 +1603,13 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCLASS_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "res = fclass_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
+partInit.code() += "res = fclass_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1644,9 +1670,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1710,9 +1737,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_WU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1773,10 +1801,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FMV_X_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1834,8 +1863,9 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FMV_W_X\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index e64b444fbb..31af0ba0fe 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
@@ -48,13 +48,15 @@ imm += R_imm_4.read(ba) << 4;
 		partInit.code() = std::string("//CADDI4SPN\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (imm) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + "U;\n";
 } else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 64);
@@ -125,12 +127,15 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_int32)(mem_val_0);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -204,11 +209,14 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -277,10 +285,11 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//CADDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if ((rs1 % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -340,7 +349,8 @@ nzimm += R_nzimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CNOP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -398,10 +408,11 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//CLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -463,14 +474,16 @@ imm += R_imm_17.read(ba) << 17;
 		partInit.code() = std::string("//CLUI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (imm == 0U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
@@ -534,13 +547,15 @@ nzimm += R_nzimm_9.read(ba) << 9;
 		partInit.code() = std::string("//CADDI16SP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (nzimm) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[2U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
 } else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 64);
@@ -600,9 +615,11 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//__reserved_clui\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -655,8 +672,9 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(shamt) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -715,10 +733,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (shamt) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -779,8 +798,9 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//CANDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -841,8 +861,9 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CSUB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -902,8 +923,9 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CXOR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -963,8 +985,9 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//COR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1024,8 +1047,9 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CAND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1096,8 +1120,9 @@ imm += R_imm_11.read(ba) << 11;
 		partInit.code() = std::string("//CJ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1174,10 +1199,11 @@ imm += R_imm_8.read(ba) << 8;
 		partInit.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] == 0UL) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] == 0UL) {\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1252,10 +1278,11 @@ imm += R_imm_8.read(ba) << 8;
 		partInit.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] != 0UL) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] != 0UL) {\n";
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1322,10 +1349,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (nzuimm) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(nzuimm) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(nzuimm) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1388,16 +1416,19 @@ uimm += R_uimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CLWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (rd % 32U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ", (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = mem_val_0;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
 } else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1460,10 +1491,11 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CMV\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1519,12 +1551,13 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CJR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (rs1) {
-partInit.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2L;\n";
+partInit.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & -2L;\n";
 } else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1574,9 +1607,11 @@ static InstructionDefinition __reserved_cmv_ (
 		partInit.code() = std::string("//__reserved_cmv\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1626,10 +1661,11 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CADD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1686,10 +1722,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//CJALR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 partInit.code() += "cpu->nextPc = new_pc & -2L;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1740,8 +1777,9 @@ static InstructionDefinition cebreak_ (
 		partInit.code() = std::string("//CEBREAK\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1795,11 +1833,14 @@ uimm += R_uimm_2.read(ba) << 2;
 		partInit.code() = std::string("//CSWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1855,8 +1896,9 @@ static InstructionDefinition dii_ (
 		partInit.code() = std::string("//DII\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index ab0e392b4f..d3f1418ad2 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
@@ -42,10 +42,11 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//LUI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -103,10 +104,11 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//AUIPC\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -170,15 +172,16 @@ imm += R_imm_20.read(ba) << 20;
 		partInit.code() = std::string("//JAL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 }
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -246,17 +249,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//JALR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
 partInit.code() += "if (new_pc % 2UL) {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 }
 partInit.code() += "cpu->nextPc = new_pc & -2L;\n";
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -328,16 +332,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -413,16 +418,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -498,16 +504,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -583,16 +590,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -668,16 +676,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -753,16 +762,17 @@ imm += R_imm_12.read(ba) << 12;
 		partInit.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 } else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -832,15 +842,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -906,15 +919,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -980,15 +996,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1054,15 +1073,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LBU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1128,15 +1150,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LHU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1204,11 +1229,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//SB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1278,11 +1306,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//SH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1352,11 +1383,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//SW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -1424,10 +1458,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//ADDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1492,10 +1527,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//SLTI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1560,10 +1596,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//SLTIU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + ")) ? (1U) : (0U);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U)) ? (1U) : (0U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1628,10 +1665,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//XORI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1696,10 +1734,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//ORI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1764,10 +1803,11 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//ANDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1832,10 +1872,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1900,10 +1941,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1968,10 +2010,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2036,10 +2079,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//ADD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2105,10 +2149,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SUB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2174,10 +2219,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SLL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 63UL);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2243,10 +2289,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SLT\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (1U) : (0U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2312,10 +2359,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SLTU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (1U) : (0U);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (1U) : (0U);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2381,10 +2429,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//XOR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2450,10 +2499,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SRL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 63UL);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2519,10 +2569,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SRA\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 63UL);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2588,10 +2639,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//OR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2657,10 +2709,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//AND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2732,8 +2785,9 @@ fm += R_fm_0.read(ba) << 0;
 		partInit.code() = std::string("//FENCE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FENCE[" + std::to_string(0) + "] = " + std::to_string(pred << 4U | succ) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FENCE[" + std::to_string(0) + "U] = " + std::to_string(pred << 4U | succ) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -2793,8 +2847,9 @@ static InstructionDefinition ecall_ (
 		partInit.code() = std::string("//ECALL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -2840,8 +2895,9 @@ static InstructionDefinition wfi_ (
 		partInit.code() = std::string("//WFI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "cpu->exception = ETISS_RETURNCODE_CPUFINISHED;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index f049adaab0..1c36fc0495 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 03 Nov 2022 14:26:19 +0100.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
@@ -45,11 +45,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MUL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -115,11 +116,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MULH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((res >> 64UL));\n";
+partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64UL));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -185,11 +187,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MULHSU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((res >> 64UL));\n";
+partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64UL));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -255,11 +258,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MULHU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint128 res = (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((res >> 64UL));\n";
+partInit.code() += "etiss_uint128 res = (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64UL));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -325,21 +329,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//DIV\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
 etiss_uint64 MMIN = 9223372036854775808UL;
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(MMIN) + ";\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(MMIN) + "U;\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1L;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -405,15 +410,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//DIVU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1L;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -479,21 +485,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//REM\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
 etiss_uint64 MMIN = 9223372036854775808UL;
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = 0UL;\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = 0UL;\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -559,15 +566,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//REMU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index c2608173f2..88729b235c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
@@ -51,17 +51,22 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOSWAPD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
 }
-partInit.code() += "etiss_uint64 mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "etiss_uint64 mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -140,19 +145,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOADDD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -231,19 +241,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOXORD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -322,19 +337,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOANDD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n";
+partInit.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -413,19 +433,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOORD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint64 res2 = (((res) << 64) | (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n";
+partInit.code() += "etiss_uint64 res2 = (((res) << 64) | (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
 partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -504,19 +529,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMIND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
 partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -595,19 +625,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMAXD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res);\n";
+partInit.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res);\n";
 partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -686,19 +721,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMINUD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
 }
-partInit.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res);\n";
+partInit.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res);\n";
 partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -777,19 +817,24 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//AMOMAXUD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res1);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res1);\n";
 }
-partInit.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n";
+partInit.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
 partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index 303955c7af..1527063d69 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
@@ -45,10 +45,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_L_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), 0U, " + std::to_string(rm) + ");\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 0U, " + std::to_string(rm) + "U);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -112,10 +113,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_LU_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), 1U, " + std::to_string(rm) + ");\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 1U, " + std::to_string(rm) + "U);\n";
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -179,9 +181,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_L\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "], 2U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 2U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -245,9 +248,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_D_LU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "], 3U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 3U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -308,8 +312,9 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FMV_X_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U];\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -367,8 +372,9 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FMV_D_X\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index 07f5801698..48ef984f20 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
@@ -45,13 +45,14 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_L_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), 0U, " + std::to_string(rm) + ");\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 0U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -115,13 +116,14 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_LU_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), 1U, " + std::to_string(rm) + ");\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 1U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint32 flags = fget_flags();\n";
 partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -185,9 +187,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_L\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "], 2U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 2U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -251,9 +254,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 		partInit.code() = std::string("//FCVT_S_LU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "], 3U, " + std::to_string(rm) + ");\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 3U, " + std::to_string(rm) + "U);\n";
+partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index 203761484d..b0f3908aeb 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
@@ -44,10 +44,11 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//CADDIW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if ((rs1 % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "U] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -110,8 +111,9 @@ nzuimm += R_nzuimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] >> " + std::to_string(nzuimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(nzuimm) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -174,8 +176,9 @@ shamt += R_shamt_5.read(ba) << 5;
 		partInit.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -238,12 +241,14 @@ shamt += R_shamt_5.read(ba) << 5;
 		partInit.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (rs1 == 0U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "] << " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] << " + std::to_string(shamt) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1], 64);
@@ -308,12 +313,15 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_int64)(mem_val_0);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int64)(mem_val_0);\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -383,11 +391,14 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -452,9 +463,10 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CSUBW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_uint64)((etiss_int32)(res));\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -514,9 +526,10 @@ rd += R_rd_0.read(ba) << 0;
 		partInit.code() = std::string("//CADDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_uint64)((etiss_int32)(res));\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -580,17 +593,20 @@ uimm += R_uimm_5.read(ba) << 5;
 		partInit.code() = std::string("//CLDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if (rd % 32U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 } else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -656,11 +672,14 @@ uimm += R_uimm_3.read(ba) << 3;
 		partInit.code() = std::string("//CSDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index 2147fed13e..0e8500ad65 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
@@ -45,15 +45,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LWU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -119,15 +122,18 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//LD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -195,11 +201,14 @@ imm += R_imm_5.read(ba) << 5;
 		partInit.code() = std::string("//SD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -267,10 +276,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -335,10 +345,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -403,10 +414,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) >> " + std::to_string(shamt) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -471,11 +483,12 @@ imm += R_imm_0.read(ba) << 0;
 		partInit.code() = std::string("//ADDIW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+partInit.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -540,11 +553,12 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SLLIW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) << " + std::to_string(shamt) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) << " + std::to_string(shamt) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -609,11 +623,12 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SRLIW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) >> " + std::to_string(shamt) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -678,11 +693,12 @@ shamt += R_shamt_0.read(ba) << 0;
 		partInit.code() = std::string("//SRAIW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) >> " + std::to_string(shamt) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(sh_val);\n";
+partInit.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(sh_val);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -747,11 +763,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//ADDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+partInit.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -817,11 +834,12 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SUBW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+partInit.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -887,12 +905,13 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SLLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) & 31U;\n";
-partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) << count;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
+partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) << count;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -958,12 +977,13 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SRLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) & 31U;\n";
-partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) >> count;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
+partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> count;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -1029,12 +1049,13 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//SRAW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) & 31U;\n";
-partInit.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) >> count;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(sh_val);\n";
+partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
+partInit.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> count;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(sh_val);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index d32b924b94..8a364a190d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 03 Nov 2022 14:46:05 +0100.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
@@ -45,10 +45,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//MULW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]))));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -114,21 +115,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//DIVW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
 etiss_int32 MMIN = 2147483648U;
-partInit.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -2147483648L;\n";
+partInit.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -2147483648L;\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])));\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1L;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -194,15 +196,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//DIVUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) != 0U) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]))));\n";
+partInit.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) != 0U) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1L;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -268,21 +271,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//REMW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0UL) {\n";
+partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
 etiss_int32 MMIN = 2147483648U;
-partInit.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = 0UL;\n";
+partInit.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = 0UL;\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])));\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])));\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -348,15 +352,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		partInit.code() = std::string("//REMUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) != 0U) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]))));\n";
+partInit.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) != 0U) {\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])));\n";
 partInit.code() += "}\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index e9cdecbabd..5b177fa036 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
@@ -46,8 +46,9 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FENCE[" + std::to_string(1) + "] = " + std::to_string(imm) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "((RV64IMACFD*)cpu)->FENCE[" + std::to_string(1) + "U] = " + std::to_string(imm) + "U;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index 1dd9e8228d..a4de9de678 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
@@ -45,15 +45,16 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 } else {
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -118,15 +119,16 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRS\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if (rs1 != 0U) {
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | xrs1);\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | xrs1);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -191,15 +193,16 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRC\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if (rs1 != 0U) {
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & ~(xrs1));\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & ~(xrs1));\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -264,12 +267,13 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRWI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", " + std::to_string((etiss_uint64)(zimm)) + ");\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, " + std::to_string((etiss_uint64)(zimm)) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -333,14 +337,15 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRSI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
 if (zimm != 0U) {
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | " + std::to_string((etiss_uint64)(zimm)) + ");\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | " + std::to_string((etiss_uint64)(zimm)) + "U);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
@@ -404,14 +409,15 @@ csr += R_csr_0.read(ba) << 0;
 		partInit.code() = std::string("//CSRRCI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
 if (zimm != 0U) {
-partInit.code() += "cpu->exception = 0; csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + ");\n";
+partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "U);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index 7ac35e7077..81c49dcab7 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
@@ -36,18 +36,19 @@ static InstructionDefinition mret_ (
 		partInit.code() = std::string("//MRET\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833];\n";
 partInit.code() += "etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[768];\n";
-partInit.code() += "etiss_uint64 prev_prv = get_field(s, " + std::to_string(6144) + ");\n";
+partInit.code() += "etiss_uint64 prev_prv = get_field(s, " + std::to_string(6144) + "U);\n";
 partInit.code() += "if (prev_prv != 3L) {\n";
-partInit.code() += "s = set_field(s, " + std::to_string(131072) + ", 0U);\n";
+partInit.code() += "s = set_field(s, " + std::to_string(131072) + "U, 0U);\n";
 partInit.code() += "}\n";
-partInit.code() += "s = set_field(s, " + std::to_string(8) + ", get_field(s, " + std::to_string(128) + "));\n";
-partInit.code() += "s = set_field(s, " + std::to_string(128) + ", 1U);\n";
-partInit.code() += "s = set_field(s, " + std::to_string(6144) + ", " + std::to_string(3) + ");\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->CSR[" + std::to_string(768) + "] = s;\n";
+partInit.code() += "s = set_field(s, " + std::to_string(8) + "U, get_field(s, " + std::to_string(128) + "U));\n";
+partInit.code() += "s = set_field(s, " + std::to_string(128) + "U, 1U);\n";
+partInit.code() += "s = set_field(s, " + std::to_string(6144) + "U, " + std::to_string(3) + "U);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->CSR[" + std::to_string(768) + "U] = s;\n";
 partInit.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index d4bb4d68c7..7ebf994fb8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
@@ -48,16 +48,19 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//LRD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
 if (rd) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -132,17 +135,20 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//SCD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "etiss_uint64 mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "}\n";
 if (rd) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
 }
 partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index 0b2836bd12..c44c246923 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
@@ -48,16 +48,19 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//LRW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
 if (rd) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int64)(res);\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
 }
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -132,17 +135,20 @@ aq += R_aq_0.read(ba) << 0;
 		partInit.code() = std::string("//SCW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n";
+partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "}\n";
 if (rd) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
 }
 partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index 031ef5022e..6356851b4f 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 04 Nov 2022 23:55:27 +0100.
+ * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.
@@ -36,32 +36,39 @@ static InstructionDefinition ebreak_ (
 		partInit.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + ";\n";
+partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "if (etiss_semihost_enabled()) {\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4UL) + ", (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4UL) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0UL) + ", (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0UL) + "U, (etiss_uint8*)&mem_val_1, 4);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
 partInit.code() += "etiss_uint32 mem_val_2;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4UL) + ", (etiss_uint8*)&mem_val_2, 4);\n";
-partInit.code() += "if (cpu->exception) translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4UL) + "U, (etiss_uint8*)&mem_val_2, 4);\n";
+partInit.code() += "if (cpu->exception) {\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
 partInit.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
 partInit.code() += "etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10U];\n";
 partInit.code() += "etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11U];\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[10U] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(64) + ", operation, parameter));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[10U] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(64) + "U, operation, parameter));\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + ");\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 partInit.code() += " else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + ");\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------

From 9a15fd30b21e412d0ccf8d72eaf1e9acdadc78aa Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Mon, 14 Nov 2022 18:47:04 +0100
Subject: [PATCH 18/44] load correct rv64 core

---
 src/SimpleMemSystem.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/SimpleMemSystem.cpp b/src/SimpleMemSystem.cpp
index 8264c10414..ea0bf5618c 100644
--- a/src/SimpleMemSystem.cpp
+++ b/src/SimpleMemSystem.cpp
@@ -174,7 +174,7 @@ void SimpleMemSystem::load_elf()
         if (reader.get_machine() == EM_RISCV)
         {
             if ((reader.get_class() == ELFCLASS64)) {
-                etiss::cfg().set<std::string>("arch.cpu", "RISCV64"); // RISCV and OR1K work as well
+                etiss::cfg().set<std::string>("arch.cpu", "RV64IMACFD"); // RISCV and OR1K work as well
             } else if ((reader.get_class() == ELFCLASS32)) {
                 etiss::cfg().set<std::string>("arch.cpu", "RV32IMACFD");
             // add conditions

From 7749b6dbf64c6e5aeec5049a0dd4c1cacd7e1e44 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Tue, 15 Nov 2022 00:07:50 +0100
Subject: [PATCH 19/44] update arch

---
 ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp | 8 ++++----
 ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
index 442e9d7eac..e77f552a71 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -116,8 +116,8 @@ error_code += R_error_code_0.read(ba) << 0;
 		partInit.code() = std::string("//trap_entry 32\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + ");\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -149,8 +149,8 @@ error_code += R_error_code_0.read(ba) << 0;
 		partInit.code() = std::string("//trap_entry 16\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + ");\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
index 83d236a357..3db4526fe4 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -121,8 +121,8 @@ error_code += R_error_code_0.read(ba) << 0;
 		partInit.code() = std::string("//trap_entry 32\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + ";\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + ");\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------
@@ -154,8 +154,8 @@ error_code += R_error_code_0.read(ba) << 0;
 		partInit.code() = std::string("//trap_entry 16\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + ";\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + ");\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
 // -----------------------------------------------------------------------------

From 2dc4aee774eff353c53266f98a7c02c3b9a6e70d Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Wed, 16 Nov 2022 15:48:00 +0100
Subject: [PATCH 20/44] update arch

---
 ArchImpl/RV32IMACFD/CMakeLists.txt            |  4 +-
 .../RV32IMACFD/RV32IMACFDArchSpecificImp.cpp  |  6 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         | 29 +++---
 ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h       |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp       |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp | 83 +++++++++++------
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     | 20 +++--
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp | 11 ++-
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     | 20 +++--
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp | 11 ++-
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 59 ++++++++-----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 88 ++++++++++++-------
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp | 14 +--
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |  2 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    |  5 +-
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    |  2 +-
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    | 11 ++-
 .../RV32IMACFD_tum_semihostingInstr.cpp       | 21 +++--
 ArchImpl/RV64IMACFD/CMakeLists.txt            |  4 +-
 .../RV64IMACFD/RV64IMACFDArchSpecificImp.cpp  |  6 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h         | 29 +++---
 ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h       |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp       |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp | 83 +++++++++++------
 .../RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp     | 20 +++--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp | 11 ++-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp | 11 ++-
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     | 59 ++++++++-----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp | 88 ++++++++++++-------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp | 14 +--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp | 83 +++++++++++------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp |  2 +-
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     | 29 +++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp | 14 +--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp | 14 +--
 .../RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp   |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    |  5 +-
 .../RV64IMACFD/RV64IMACFD_tum_retInstr.cpp    |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp  | 11 ++-
 .../RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp    | 11 ++-
 .../RV64IMACFD_tum_semihostingInstr.cpp       | 21 +++--
 42 files changed, 586 insertions(+), 329 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index 5f99bac347..37e82eaa83 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Fri, 04 Nov 2022 23:33:07 +0100.
+# Generated on Wed, 16 Nov 2022 11:39:01 +0100.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
@@ -17,8 +17,8 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFD_RV32DInstr.cpp
 	RV32IMACFD_RV32DCInstr.cpp
 	RV32IMACFD_ZifenceiInstr.cpp
-	RV32IMACFD_tum_csrInstr.cpp
 	RV32IMACFD_tum_retInstr.cpp
+	RV32IMACFD_tum_csrInstr.cpp
 	RV32IMACFD_RV32AInstr.cpp
 	RV32IMACFD_tum_rvaInstr.cpp
 	RV32IMACFD_tum_semihostingInstr.cpp
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
index e77f552a71..7b71f4b96c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -116,7 +116,8 @@ error_code += R_error_code_0.read(ba) << 0;
 		partInit.code() = std::string("//trap_entry 32\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
@@ -149,7 +150,8 @@ error_code += R_error_code_0.read(ba) << 0;
 		partInit.code() = std::string("//trap_entry 16\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index 47821e84ee..afc62a2957 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:52:53 +0100.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -163,15 +163,20 @@ static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * cons
 etiss_int32 code = 0U;
 if (cause == -5) {
 code = 5;
-} else if (cause == -14) {
+}
+ else if (cause == -14) {
 code = 13;
-} else if (cause == -6) {
+}
+ else if (cause == -6) {
 code = 7;
-} else if (cause == -15) {
+}
+ else if (cause == -15) {
 code = 15;
-} else if (cause == -7) {
+}
+ else if (cause == -7) {
 code = 1;
-} else {
+}
+else {
 code = 2;
 }
 cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
@@ -226,13 +231,17 @@ static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system,
 {
 if (csr == 1) {
 *((RV32IMACFD*)cpu)->CSR[3] = (*((RV32IMACFD*)cpu)->CSR[3] & 224U) | (val & 31U);
-} else if (csr == 2) {
+}
+ else if (csr == 2) {
 *((RV32IMACFD*)cpu)->CSR[3] = ((val & 7U) << 5U) | (*((RV32IMACFD*)cpu)->CSR[3] & 31U);
-} else if (csr == 3) {
+}
+ else if (csr == 3) {
 *((RV32IMACFD*)cpu)->CSR[3] = val & 255U;
-} else if (csr == 768) {
+}
+ else if (csr == 768) {
 *((RV32IMACFD*)cpu)->CSR[768] = val & 136U;
-} else if (csr != 769) {
+}
+ else if (csr != 769) {
 *((RV32IMACFD*)cpu)->CSR[csr] = val;
 }
 }
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
index 08b9fd2ec1..e285113550 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the GDBCore adapter for the RV32IMACFD core architecture.
  *
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
index 45c17e16cf..4a7b6f153c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index 3f94d6ddaa..e60caa94fb 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -57,14 +57,17 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n";
 }
-partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -150,17 +153,20 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -246,17 +252,20 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -342,17 +351,20 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -438,17 +450,20 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -534,17 +549,20 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -630,17 +648,20 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -726,17 +747,20 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 > *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -822,17 +846,20 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index aa7e86781e..790a413488 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -52,7 +52,8 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
@@ -127,10 +128,12 @@ uimm += R_uimm_3.read(ba) << 3;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -205,7 +208,8 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
@@ -276,10 +280,12 @@ uimm += R_uimm_3.read(ba) << 3;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index 93d9529ece..2f54ce9a8a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -50,7 +50,8 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
@@ -123,10 +124,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index ee0c988ea2..68e1772e81 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -54,7 +54,8 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = -4294967296L | res;\n";
@@ -133,10 +134,12 @@ uimm += R_uimm_3.read(ba) << 3;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -213,7 +216,8 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | res;\n";
@@ -284,10 +288,12 @@ uimm += R_uimm_2.read(ba) << 2;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 921058209e..4770c695fd 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -50,7 +50,8 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
@@ -123,10 +124,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index f6745627ec..279945a085 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -51,8 +51,10 @@ imm += R_imm_4.read(ba) << 4;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (imm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + "U;\n";
-} else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -132,7 +134,8 @@ partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
@@ -211,10 +214,12 @@ uimm += R_uimm_3.read(ba) << 3;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -560,7 +565,8 @@ imm += R_imm_17.read(ba) << 17;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (imm == 0U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
@@ -634,8 +640,10 @@ nzimm += R_nzimm_9.read(ba) << 9;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (nzimm) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[2U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
-} else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -700,7 +708,8 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
@@ -1505,12 +1514,15 @@ if (rd % 32U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = mem_val_0;\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res);\n";
-} else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1638,8 +1650,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (rs1) {
 partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & -2;\n";
-} else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1692,7 +1706,8 @@ static InstructionDefinition __reserved_cmv_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
@@ -1862,7 +1877,8 @@ static InstructionDefinition cebreak_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
@@ -1919,10 +1935,12 @@ uimm += R_uimm_2.read(ba) << 2;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1981,7 +1999,8 @@ static InstructionDefinition dii_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 81e4d9aa1a..9041632d68 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -174,8 +174,10 @@ imm += R_imm_20.read(ba) << 20;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 }
@@ -252,9 +254,10 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
 partInit.code() += "if (new_pc % 2U) {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 }
@@ -335,8 +338,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -421,8 +426,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -507,8 +514,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -593,8 +602,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -679,8 +690,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -765,8 +778,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -847,7 +862,8 @@ partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -924,7 +940,8 @@ partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -1001,7 +1018,8 @@ partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -1078,7 +1096,8 @@ partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -1155,7 +1174,8 @@ partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -1231,10 +1251,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint8 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1308,10 +1330,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint16 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1385,10 +1409,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -2848,7 +2874,8 @@ static InstructionDefinition ecall_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
@@ -2896,10 +2923,9 @@ static InstructionDefinition wfi_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "cpu->exception = ETISS_RETURNCODE_CPUFINISHED;\n";
+partInit.code() += "wait(1U);\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index bf99ab720a..a44f1a2ca4 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
@@ -336,11 +336,11 @@ etiss_uint32 MMIN = 2147483648U;
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(MMIN) + "U;\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1;\n";
 partInit.code() += "}\n";
 }
@@ -415,7 +415,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1;\n";
 partInit.code() += "}\n";
 }
@@ -492,11 +492,11 @@ etiss_uint32 MMIN = 2147483648U;
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = 0U;\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "}\n";
 }
@@ -571,7 +571,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "}\n";
 }
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index 89ea4a1ab8..763ab6d678 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index 22821bc140..8e9ceabbe1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:52:53 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
@@ -51,7 +51,8 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
 partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
-} else {
+}
+else {
 partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index df141fbc4b..9c25e95a77 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 7ff52ecfc2..265afcda8b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -53,7 +53,8 @@ partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";
@@ -138,10 +139,12 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) {\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 if (rd) {
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index dfb0e566be..e5c2dd3d75 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
@@ -41,19 +41,22 @@ partInit.code() += "if (etiss_semihost_enabled()) {\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4U) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "etiss_uint32 mem_val_1;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0U) + "U, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
 partInit.code() += "etiss_uint32 mem_val_2;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4U) + "U, (etiss_uint8*)&mem_val_2, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
 partInit.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
@@ -61,12 +64,14 @@ partInit.code() += "etiss_uint32 operation = *((RV32IMACFD*)cpu)->X[10U];\n";
 partInit.code() += "etiss_uint32 parameter = *((RV32IMACFD*)cpu)->X[11U];\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[10U] = (etiss_int32)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(32) + "U, operation, parameter));\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "else {\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "else {\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt
index 1fd468800d..efb1120161 100644
--- a/ArchImpl/RV64IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV64IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Fri, 04 Nov 2022 23:37:47 +0100.
+# Generated on Wed, 16 Nov 2022 11:39:01 +0100.
 #
 # This file contains the CMake build info for the RV64IMACFD core architecture.
 
@@ -23,8 +23,8 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV64IMACFD_RV32AInstr.cpp
 	RV64IMACFD_RV64AInstr.cpp
 	RV64IMACFD_ZifenceiInstr.cpp
-	RV64IMACFD_tum_csrInstr.cpp
 	RV64IMACFD_tum_retInstr.cpp
+	RV64IMACFD_tum_csrInstr.cpp
 	RV64IMACFD_tum_rvaInstr.cpp
 	RV64IMACFD_tum_rva64Instr.cpp
 	RV64IMACFD_tum_semihostingInstr.cpp
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
index 3db4526fe4..91c2e3d048 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -121,7 +121,8 @@ error_code += R_error_code_0.read(ba) << 0;
 		partInit.code() = std::string("//trap_entry 32\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
@@ -154,7 +155,8 @@ error_code += R_error_code_0.read(ba) << 0;
 		partInit.code() = std::string("//trap_entry 16\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index 504b1a6e88..1331890c69 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 18:28:02 +0100.
+ * Generated on Wed, 16 Nov 2022 11:52:53 +0100.
  *
  * This file contains the function macros for the RV64IMACFD core architecture.
  */
@@ -163,15 +163,20 @@ static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * cons
 etiss_int32 code = 0U;
 if (cause == -5) {
 code = 5;
-} else if (cause == -14) {
+}
+ else if (cause == -14) {
 code = 13;
-} else if (cause == -6) {
+}
+ else if (cause == -6) {
 code = 7;
-} else if (cause == -15) {
+}
+ else if (cause == -15) {
 code = 15;
-} else if (cause == -7) {
+}
+ else if (cause == -7) {
 code = 1;
-} else {
+}
+else {
 code = 2;
 }
 cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
@@ -226,13 +231,17 @@ static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system,
 {
 if (csr == 1) {
 *((RV64IMACFD*)cpu)->CSR[3] = (*((RV64IMACFD*)cpu)->CSR[3] & 224UL) | (val & 31UL);
-} else if (csr == 2) {
+}
+ else if (csr == 2) {
 *((RV64IMACFD*)cpu)->CSR[3] = ((val & 7UL) << 5U) | (*((RV64IMACFD*)cpu)->CSR[3] & 31UL);
-} else if (csr == 3) {
+}
+ else if (csr == 3) {
 *((RV64IMACFD*)cpu)->CSR[3] = val & 255UL;
-} else if (csr == 768) {
+}
+ else if (csr == 768) {
 *((RV64IMACFD*)cpu)->CSR[768] = val & 136UL;
-} else if (csr != 769) {
+}
+ else if (csr != 769) {
 *((RV64IMACFD*)cpu)->CSR[csr] = val;
 }
 }
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
index 1bc725ec32..e2bf2ec25c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the GDBCore adapter for the RV64IMACFD core architecture.
  *
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
index 56293d9d22..4662f463b8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index 2686737236..5c1d3903c8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
@@ -57,14 +57,17 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
 }
-partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -150,17 +153,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -246,17 +252,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -342,17 +351,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -438,17 +450,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -534,17 +549,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -630,17 +648,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -726,17 +747,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -822,17 +846,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
 }
 partInit.code() += "etiss_uint32 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint32 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index 2c3100bd96..0facbb270f 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
@@ -52,7 +52,8 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
@@ -127,10 +128,12 @@ uimm += R_uimm_3.read(ba) << 3;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -205,7 +208,8 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
@@ -276,10 +280,12 @@ uimm += R_uimm_3.read(ba) << 3;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index 0e751b3668..20c381b6c7 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
@@ -50,7 +50,8 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
@@ -123,10 +124,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index 892a91fc0c..0fbeb31720 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
@@ -50,7 +50,8 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
@@ -123,10 +124,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index 31af0ba0fe..f44b7f3561 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
@@ -51,8 +51,10 @@ imm += R_imm_4.read(ba) << 4;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (imm) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + "U;\n";
-} else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -132,7 +134,8 @@ partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
@@ -211,10 +214,12 @@ uimm += R_uimm_3.read(ba) << 3;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -476,7 +481,8 @@ imm += R_imm_17.read(ba) << 17;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (imm == 0U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
@@ -550,8 +556,10 @@ nzimm += R_nzimm_9.read(ba) << 9;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (nzimm) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[2U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
-} else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -616,7 +624,8 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
@@ -1421,12 +1430,15 @@ if (rd % 32U) {
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = mem_val_0;\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
-} else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1554,8 +1566,10 @@ rs1 += R_rs1_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (rs1) {
 partInit.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & -2L;\n";
-} else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1608,7 +1622,8 @@ static InstructionDefinition __reserved_cmv_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
@@ -1778,7 +1793,8 @@ static InstructionDefinition cebreak_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
@@ -1835,10 +1851,12 @@ uimm += R_uimm_2.read(ba) << 2;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1897,7 +1915,8 @@ static InstructionDefinition dii_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index d3f1418ad2..2154c0b62a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
@@ -174,8 +174,10 @@ imm += R_imm_20.read(ba) << 20;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 }
@@ -252,9 +254,10 @@ imm += R_imm_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
 partInit.code() += "if (new_pc % 2UL) {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 }
@@ -335,8 +338,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -421,8 +426,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -507,8 +514,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -593,8 +602,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -679,8 +690,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -765,8 +778,10 @@ imm += R_imm_12.read(ba) << 12;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-} else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
 partInit.code() += "}\n";
@@ -847,7 +862,8 @@ partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -924,7 +940,8 @@ partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -1001,7 +1018,8 @@ partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -1078,7 +1096,8 @@ partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint8 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -1155,7 +1174,8 @@ partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::
 partInit.code() += "etiss_uint16 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -1231,10 +1251,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint8 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1308,10 +1330,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint16 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1385,10 +1409,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -2848,7 +2874,8 @@ static InstructionDefinition ecall_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 partInit.code() += "return cpu->exception;\n";
@@ -2896,10 +2923,9 @@ static InstructionDefinition wfi_ (
 
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "cpu->exception = ETISS_RETURNCODE_CPUFINISHED;\n";
+partInit.code() += "wait(1U);\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index 1c36fc0495..29f8ffada1 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
@@ -336,11 +336,11 @@ etiss_uint64 MMIN = 9223372036854775808UL;
 partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(MMIN) + "U;\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
 partInit.code() += "}\n";
 }
@@ -415,7 +415,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
 partInit.code() += "}\n";
 }
@@ -492,11 +492,11 @@ etiss_uint64 MMIN = 9223372036854775808UL;
 partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = 0UL;\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "}\n";
 }
@@ -571,7 +571,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "}\n";
 }
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index 88729b235c..462db677cb 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
@@ -57,14 +57,17 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
 }
-partInit.code() += "etiss_uint64 mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_1;\n";
+partInit.code() += "mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -150,17 +153,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint64 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -246,17 +252,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint64 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -342,17 +351,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint64 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -438,17 +450,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint64 res2 = (((res) << 64) | (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint64 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -534,17 +549,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
 }
 partInit.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint64 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -630,17 +648,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
 }
 partInit.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res);\n";
-partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint64 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -726,17 +747,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
 }
 partInit.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res);\n";
-partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint64 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -822,17 +846,20 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint64 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res1);\n";
 }
 partInit.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint64 mem_val_1 = res2;\n";
+partInit.code() += "etiss_uint64 mem_val_1;\n";
+partInit.code() += "mem_val_1 = res2;\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index 1527063d69..1c81bd0be1 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index 48ef984f20..33e05e98a9 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index b0f3908aeb..096c1f6157 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
@@ -243,7 +243,8 @@ shamt += R_shamt_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (rs1 == 0U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] << " + std::to_string(shamt) + "U;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
@@ -318,7 +319,8 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int64)(mem_val_0);\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
@@ -393,10 +395,12 @@ uimm += R_uimm_3.read(ba) << 3;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -598,13 +602,16 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = mem_val_0;\n";
 if (rd % 32U) {
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
-} else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+}
+else {
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -674,10 +681,12 @@ uimm += R_uimm_3.read(ba) << 3;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index 0e8500ad65..3a82261dce 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
@@ -50,7 +50,8 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -127,7 +128,8 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
@@ -203,10 +205,12 @@ imm += R_imm_5.read(ba) << 5;
 // -----------------------------------------------------------------------------
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index 8a364a190d..7d4b216a53 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
@@ -122,11 +122,11 @@ etiss_int32 MMIN = 2147483648U;
 partInit.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -2147483648L;\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])));\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
 partInit.code() += "}\n";
 }
@@ -201,7 +201,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) != 0U) {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
 partInit.code() += "}\n";
 }
@@ -278,11 +278,11 @@ etiss_int32 MMIN = 2147483648U;
 partInit.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = 0UL;\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])));\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])));\n";
 partInit.code() += "}\n";
 }
@@ -357,7 +357,7 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) != 0U) {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
+partInit.code() += "else {\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])));\n";
 partInit.code() += "}\n";
 }
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index 5b177fa036..e5a7622d65 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index a4de9de678..91258c5312 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:52:53 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
@@ -51,7 +51,8 @@ if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
 partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
-} else {
+}
+else {
 partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index 81c49dcab7..ff1f7358a7 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index 7ebf994fb8..cb4d4cd4cd 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
@@ -53,7 +53,8 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint64 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
@@ -138,10 +139,12 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
-partInit.code() += "etiss_uint64 mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint64 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 if (rd) {
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index c44c246923..8c1cbe3e0f 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
@@ -53,7 +53,8 @@ partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_strin
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
@@ -138,10 +139,12 @@ aq += R_aq_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 partInit.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
-partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+partInit.code() += "etiss_uint32 mem_val_0;\n";
+partInit.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
 partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
 if (rd) {
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index 6356851b4f..b4e6fd29d0 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 14 Nov 2022 16:47:27 +0100.
+ * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.
@@ -41,19 +41,22 @@ partInit.code() += "if (etiss_semihost_enabled()) {\n";
 partInit.code() += "etiss_uint32 mem_val_0;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4UL) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "etiss_uint32 mem_val_1;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0UL) + "U, (etiss_uint8*)&mem_val_1, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
 partInit.code() += "etiss_uint32 mem_val_2;\n";
 partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4UL) + "U, (etiss_uint8*)&mem_val_2, 4);\n";
 partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
 partInit.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
@@ -61,12 +64,14 @@ partInit.code() += "etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10U];\n";
 partInit.code() += "etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11U];\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[10U] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(64) + "U, operation, parameter));\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "else {\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "}\n";
-partInit.code() += " else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U); goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+partInit.code() += "else {\n";
+partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U);\n";
+partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";

From ade2c57b816258581a3476ed8d0bdf4db4513144 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Mon, 12 Dec 2022 15:51:07 +0100
Subject: [PATCH 21/44] update arch files

---
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         |  7 +++--
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp | 20 ++++++-------
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     | 10 +++----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp |  6 ++--
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     | 10 +++----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp |  6 ++--
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 20 ++++++-------
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 30 +++++++++----------
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |  6 ++--
 .../RV32IMACFD_tum_semihostingInstr.cpp       |  4 +--
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h         |  7 +++--
 ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h       |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp       |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp | 20 ++++++-------
 .../RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp     | 10 +++----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp |  6 ++--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp |  6 ++--
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     | 20 ++++++-------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp | 30 +++++++++----------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp |  8 ++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp | 20 ++++++-------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp |  2 +-
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     | 12 ++++----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp |  8 ++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp |  2 +-
 .../RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp   |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_retInstr.cpp    |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp  |  6 ++--
 .../RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp    |  6 ++--
 .../RV64IMACFD_tum_semihostingInstr.cpp       |  4 +--
 32 files changed, 152 insertions(+), 146 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index afc62a2957..2dd9199212 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:52:53 +0100.
+ * Generated on Mon, 05 Dec 2022 22:55:33 +0100.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -161,7 +161,10 @@ s = set_field(s, 8, 0U);
 static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
 {
 etiss_int32 code = 0U;
-if (cause == -5) {
+if (cause == -2147483648) {
+return;
+}
+ else if (cause == -5) {
 code = 5;
 }
  else if (cause == -14) {
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index e60caa94fb..e8b18908d2 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -71,7 +71,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -170,7 +170,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -269,7 +269,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -368,7 +368,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -467,7 +467,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -566,7 +566,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -665,7 +665,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -764,7 +764,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -863,7 +863,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index 790a413488..a2d450b901 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -59,7 +59,7 @@ partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -137,7 +137,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -215,7 +215,7 @@ partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -289,7 +289,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index 2f54ce9a8a..a76e37a05b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -57,7 +57,7 @@ partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -133,7 +133,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 68e1772e81..de64dd7f25 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -61,7 +61,7 @@ partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = -4294967296L | res;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -143,7 +143,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -223,7 +223,7 @@ partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | res;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -297,7 +297,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 4770c695fd..1ebbdc93c3 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -57,7 +57,7 @@ partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -133,7 +133,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index 279945a085..9375cde7fd 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -58,7 +58,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -140,7 +140,7 @@ partInit.code() += "}\n";
 partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -223,7 +223,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
@@ -573,7 +573,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = "
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -647,7 +647,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
@@ -712,7 +712,7 @@ partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U,
 partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1526,7 +1526,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
@@ -1710,7 +1710,7 @@ partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U,
 partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1944,7 +1944,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 9041632d68..3662ac1f05 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -347,7 +347,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -435,7 +435,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -523,7 +523,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -611,7 +611,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -699,7 +699,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -787,7 +787,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -871,7 +871,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -949,7 +949,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1027,7 +1027,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1105,7 +1105,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1183,7 +1183,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1260,7 +1260,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1339,7 +1339,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -1418,7 +1418,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 265afcda8b..d8c464b570 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -63,7 +63,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
@@ -153,7 +153,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index e5c2dd3d75..3aa91dfc78 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
@@ -75,7 +75,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[10U], 32);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index 1331890c69..b29892e9c3 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:52:53 +0100.
+ * Generated on Mon, 05 Dec 2022 22:55:33 +0100.
  *
  * This file contains the function macros for the RV64IMACFD core architecture.
  */
@@ -161,7 +161,10 @@ s = set_field(s, 8, 0U);
 static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
 {
 etiss_int32 code = 0U;
-if (cause == -5) {
+if (cause == -2147483648) {
+return;
+}
+ else if (cause == -5) {
 code = 5;
 }
  else if (cause == -14) {
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
index e2bf2ec25c..6c526672a8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the GDBCore adapter for the RV64IMACFD core architecture.
  *
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
index 4662f463b8..20c12ab196 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index 5c1d3903c8..92e7ea75b6 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
@@ -71,7 +71,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -170,7 +170,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -269,7 +269,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -368,7 +368,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -467,7 +467,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -566,7 +566,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -665,7 +665,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -764,7 +764,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -863,7 +863,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index 0facbb270f..a38b290db3 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
@@ -59,7 +59,7 @@ partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
@@ -137,7 +137,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
@@ -215,7 +215,7 @@ partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 64);
@@ -289,7 +289,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index 20c381b6c7..1ed56ffd27 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
@@ -57,7 +57,7 @@ partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -133,7 +133,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index 0fbeb31720..f4ce1fa9a5 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
@@ -57,7 +57,7 @@ partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -133,7 +133,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index f44b7f3561..04f367f69e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
@@ -58,7 +58,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 64);
@@ -140,7 +140,7 @@ partInit.code() += "}\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
@@ -223,7 +223,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
@@ -489,7 +489,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = "
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
@@ -563,7 +563,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 64);
@@ -628,7 +628,7 @@ partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U,
 partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1442,7 +1442,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
@@ -1626,7 +1626,7 @@ partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U,
 partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getAffectedRegisters().add("instructionPointer", 32);
@@ -1860,7 +1860,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index 2154c0b62a..1e7b63408d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
@@ -347,7 +347,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -435,7 +435,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -523,7 +523,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -611,7 +611,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -699,7 +699,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -787,7 +787,7 @@ partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((eti
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -871,7 +871,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -949,7 +949,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -1027,7 +1027,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -1105,7 +1105,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -1183,7 +1183,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -1260,7 +1260,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -1339,7 +1339,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -1418,7 +1418,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index 29f8ffada1..dd21f7b4c8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:55:33 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
@@ -119,7 +119,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64UL));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64ULL));\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -190,7 +190,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64UL));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64ULL));\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -261,7 +261,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
 partInit.code() += "etiss_uint128 res = (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64UL));\n";
+partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64ULL));\n";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index 462db677cb..614f96b271 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
@@ -71,7 +71,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -170,7 +170,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -269,7 +269,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -368,7 +368,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -467,7 +467,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -566,7 +566,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -665,7 +665,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -764,7 +764,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -863,7 +863,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index 1c81bd0be1..c50e9b83b5 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index 33e05e98a9..7131be4f5d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index 096c1f6157..3d5f28852e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
@@ -249,7 +249,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] << " + std::to_string(shamt) + "U;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1], 64);
@@ -325,7 +325,7 @@ partInit.code() += "}\n";
 partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int64)(mem_val_0);\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
@@ -404,7 +404,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
@@ -615,7 +615,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 64);
@@ -690,7 +690,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[2U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index 3a82261dce..5f56d3374d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
@@ -59,7 +59,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -137,7 +137,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -214,7 +214,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index 7d4b216a53..244bf9f96a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index e5a7622d65..fef7afae29 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index 91258c5312..01da76051d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:52:53 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index ff1f7358a7..3ba7c5c4f0 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index cb4d4cd4cd..8780c54c81 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
@@ -63,7 +63,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -153,7 +153,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index 8c1cbe3e0f..49dd0fed7f 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
@@ -63,7 +63,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 }
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
@@ -153,7 +153,7 @@ partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (
 partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending) return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index b4e6fd29d0..c091668c98 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.
@@ -75,7 +75,7 @@ partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";
 partInit.code() += "}\n";
 partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 
 		partInit.getRegisterDependencies().add(reg_name[10U], 64);

From 44f695f25d9a11f8ea34cd35e8985da25c01ffc3 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 27 Jan 2023 18:20:26 +0100
Subject: [PATCH 22/44] make exit on loop-to-self optional

---
 src/CPUCore.cpp                    | 3 ++-
 src/bare_etiss_processor/ETISS.ini | 5 +++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/CPUCore.cpp b/src/CPUCore.cpp
index 64bbd6a424..fbee975baf 100644
--- a/src/CPUCore.cpp
+++ b/src/CPUCore.cpp
@@ -685,6 +685,7 @@ etiss::int32 CPUCore::execute(ETISS_System &_system)
 
     // start execution loop
 
+    bool exit_on_loop = etiss::cfg().get<bool>("etiss.exit_on_loop", false);
 
     float startTime = (float)clock() / CLOCKS_PER_SEC; // TESTING
 
@@ -792,7 +793,7 @@ etiss::int32 CPUCore::execute(ETISS_System &_system)
 
 
                     // exit simulator when a loop to self instruction is encountered
-                    if (!exception &&
+                    if (exit_on_loop && !exception &&
                             old_time + cpu_->cpuCycleTime_ps == cpu_->cpuTime_ps &&
                             old_pc == cpu_->instructionPointer)
                     {
diff --git a/src/bare_etiss_processor/ETISS.ini b/src/bare_etiss_processor/ETISS.ini
index 42feed3115..438d671619 100644
--- a/src/bare_etiss_processor/ETISS.ini
+++ b/src/bare_etiss_processor/ETISS.ini
@@ -77,6 +77,11 @@
 
   etiss.load_integrated_libraries=true
 
+  ; Exit simulation if infinite loop-to-self is detected
+  ; default = false
+
+  etiss.exit_on_loop=false
+
   ;Causes the JIT Engines to compile in debug mode
   ; default = false
 

From e05f86c0a5c00594a7c535ca113093fb7f697606 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Mon, 30 Jan 2023 20:42:22 +0100
Subject: [PATCH 23/44] move invalid callback into architectures

---
 ArchImpl/OR1K/OR1KArch.cpp                | 26 +++++++++++++++++++++++
 ArchImpl/RISCV/RISCVArchSpecificImp.h     | 23 ++++++++++++++++++++
 ArchImpl/RISCV64/RISCV64ArchSpecificImp.h | 23 ++++++++++++++++++++
 src/Instruction.cpp                       | 13 +-----------
 4 files changed, 73 insertions(+), 12 deletions(-)

diff --git a/ArchImpl/OR1K/OR1KArch.cpp b/ArchImpl/OR1K/OR1KArch.cpp
index 6f64ea7c06..f7c2ef9d71 100644
--- a/ArchImpl/OR1K/OR1KArch.cpp
+++ b/ArchImpl/OR1K/OR1KArch.cpp
@@ -358,6 +358,32 @@ void OR1KArch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const
     {
         etiss_log(ERROR, "Failed to add instructions of the OR1K instruction set");
     }
+
+    mis.foreach(
+        [](etiss::instr::VariableInstructionSet &vis) {
+            vis.foreach(
+                [](etiss::instr::InstructionSet &is) {
+                    is.getInvalid().addCallback(
+                        [](etiss::instr::BitArray &ba, CodeSet &cs, etiss::instr::InstructionContext &ic) {
+                            etiss_uint32 error_code = 0;
+                            static etiss::instr::BitArrayRange R_error_code_0(31, 0);
+                            error_code += R_error_code_0.read(ba) << 0;
+
+                            std::stringstream ss;
+                            ss << "\t\t//trap_entry 32\n";
+                            ss << "\t\treturn " << std::to_string(error_code) << "U;";
+                            //#if DEBUG
+                            ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba;
+                            //#endif
+                            ss << "\n";
+                            cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str();
+                            return true;
+                        },
+                        0);
+                }
+            );
+        }
+    );
 }
 
 void OR1KArch::initCodeBlock(etiss::CodeBlock &cb) const
diff --git a/ArchImpl/RISCV/RISCVArchSpecificImp.h b/ArchImpl/RISCV/RISCVArchSpecificImp.h
index 00b0c4a23f..92f79fbd79 100755
--- a/ArchImpl/RISCV/RISCVArchSpecificImp.h
+++ b/ArchImpl/RISCV/RISCVArchSpecificImp.h
@@ -394,6 +394,29 @@ void RISCVArch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const
     etiss::instr::VariableInstructionSet *vis = mis.get(1);
     using namespace etiss;
     using namespace etiss::instr;
+
+    vis->foreach(
+        [](InstructionSet &is) {
+            is.getInvalid().addCallback(
+                [](BitArray &ba, CodeSet &cs, InstructionContext &ic) {
+                    etiss_uint32 error_code = 0;
+                    static BitArrayRange R_error_code_0(31, 0);
+                    error_code += R_error_code_0.read(ba) << 0;
+
+                    std::stringstream ss;
+                    ss << "\t\t//trap_entry 32\n";
+                    ss << "\t\treturn " << std::to_string(error_code) << "U;";
+                    //#if DEBUG
+                    ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba;
+                    //#endif
+                    ss << "\n";
+                    cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str();
+                    return true;
+                },
+                0);
+        }
+    );
+
     vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) {
         std::function<void(InstructionContext & ic, etiss_uint32 opRd)> updateRiscvInstrLength =
             [](InstructionContext &ic, etiss_uint32 opRd) {
diff --git a/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h b/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h
index ed283366da..a488e46139 100644
--- a/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h
+++ b/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h
@@ -418,6 +418,29 @@ void RISCV64Arch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const
 
     using namespace etiss;
     using namespace etiss::instr;
+
+    vis->foreach(
+        [](InstructionSet &is) {
+            is.getInvalid().addCallback(
+                [](BitArray &ba, CodeSet &cs, InstructionContext &ic) {
+                    etiss_uint32 error_code = 0;
+                    static BitArrayRange R_error_code_0(31, 0);
+                    error_code += R_error_code_0.read(ba) << 0;
+
+                    std::stringstream ss;
+                    ss << "\t\t//trap_entry 32\n";
+                    ss << "\t\treturn " << std::to_string(error_code) << "U;";
+                    //#if DEBUG
+                    ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba;
+                    //#endif
+                    ss << "\n";
+                    cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str();
+                    return true;
+                },
+                0);
+        }
+    );
+
     vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) {
         std::function<void(InstructionContext & ic, etiss_uint32 opRd)> updateRiscvInstrLength =
             [](InstructionContext &ic, etiss_uint32 opRd) {
diff --git a/src/Instruction.cpp b/src/Instruction.cpp
index 57c8650c5c..bfe540ebfa 100644
--- a/src/Instruction.cpp
+++ b/src/Instruction.cpp
@@ -893,19 +893,8 @@ InstructionSet::InstructionSet(VariableInstructionSet &parent, unsigned width, c
     : parent_(parent), name_(name), width_(width), root_(nullptr), invalid(width, -1, -1, "INVALID")
 {
 
-    invalid.addCallback(
-        [](BitArray &ba, CodeSet &cs, InstructionContext &ic) {
-            std::stringstream ss;
-            ss << "\t\treturn ETISS_RETURNCODE_ILLEGALINSTRUCTION;";
-            //#if DEBUG
-            ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba;
-            //#endif
-            ss << "\n";
-            cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str();
-            return true;
-        },
-        0);
 }
+
 InstructionSet::~InstructionSet()
 {
     delete root_;

From 2256d90f3f62170ee58de3f59d4edea89e2ac341 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Tue, 7 Feb 2023 18:26:00 +0100
Subject: [PATCH 24/44] update architecture

---
 .../RV32IMACFD/RV32IMACFDArchSpecificImp.cpp  |   50 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         |  132 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp |  601 +++++----
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     |  174 ++-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp |  632 ++++-----
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     |  174 ++-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp |  702 +++++-----
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     |  842 +++++++-----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 1176 ++++++++++-------
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp |  254 ++--
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |   29 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    |  154 +--
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    |  119 +-
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |  108 +-
 .../RV32IMACFD_tum_semihostingInstr.cpp       |  103 +-
 .../RV64IMACFD/RV64IMACFDArchSpecificImp.cpp  |   50 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h         |  132 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp |  601 +++++----
 .../RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp     |  174 ++-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp |  632 ++++-----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp |  702 +++++-----
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     |  813 +++++++-----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp | 1176 ++++++++++-------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp |  254 ++--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp |  601 +++++----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp |  128 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp |   94 +-
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     |  332 +++--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp |  423 +++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp |  177 +--
 .../RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp   |   29 +-
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    |  154 +--
 .../RV64IMACFD/RV64IMACFD_tum_retInstr.cpp    |  119 +-
 .../RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp  |  108 +-
 .../RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp    |  108 +-
 .../RV64IMACFD_tum_semihostingInstr.cpp       |  103 +-
 36 files changed, 6947 insertions(+), 5213 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
index 7b71f4b96c..28ba8d34c0 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -111,19 +111,28 @@ error_code += R_error_code_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//trap_entry 32\n");
+		cp.code() = std::string("//trap_entry 32\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//trap_entry 32\n");
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -145,19 +154,28 @@ error_code += R_error_code_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//trap_entry 16\n");
+		cp.code() = std::string("//trap_entry 16\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//trap_entry 16\n");
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index 2dd9199212..72b58c7f0a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:55:33 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -17,119 +17,126 @@
 
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void leave(etiss_int32 priv_lvl);
+extern void leave(etiss_int32 priv_lvl);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void wait(etiss_int32 flag);
+extern void wait(etiss_int32 flag);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
+static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
+{
+return (*((RV32IMACFD*)cpu)->CSR[769] >> (extension - 65U)) & 1U;
+}
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
+extern etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
+extern etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
+extern etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
+extern etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 unbox_s(etiss_uint64);
+extern etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fclass_s(etiss_uint32);
+extern etiss_uint32 unbox_s(etiss_uint64);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fget_flags();
+extern etiss_uint32 fclass_s(etiss_uint32);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
+extern etiss_uint32 fget_flags();
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
+extern etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
+extern etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
+extern etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
+extern etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
+extern etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
+extern etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
+extern etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
+extern etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
+extern etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
+extern etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 unbox_d(etiss_uint64);
+extern etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fclass_d(etiss_uint64);
+extern etiss_uint64 unbox_d(etiss_uint64);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+extern etiss_uint64 fclass_d(etiss_uint64);
 #endif
 static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
 {
@@ -145,6 +152,18 @@ static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, voi
 {
 cpu->return_pending = 1;
 etiss_uint32 epc = cpu->instructionPointer;
+if (((RV32IMACFD*)cpu)->PRIV <= 1 && (*((RV32IMACFD*)cpu)->CSR[770] >> mcause) & 1U) {
+cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[261] & -2);
+*((RV32IMACFD*)cpu)->CSR[321] = epc;
+*((RV32IMACFD*)cpu)->CSR[322] = mcause;
+etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[256];
+s = set_field(s, 32, get_field(s, 2));
+s = set_field(s, 256, ((RV32IMACFD*)cpu)->PRIV);
+s = set_field(s, 2, 0U);
+*((RV32IMACFD*)cpu)->CSR[256] = s;
+((RV32IMACFD*)cpu)->PRIV = (1) & 0x7;
+}
+else {
 cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773] & -2);
 *((RV32IMACFD*)cpu)->CSR[833] = epc;
 *((RV32IMACFD*)cpu)->CSR[834] = mcause;
@@ -155,6 +174,7 @@ s = set_field(s, 8, 0U);
 *((RV32IMACFD*)cpu)->CSR[768] = s;
 ((RV32IMACFD*)cpu)->PRIV = (3) & 0x7;
 }
+}
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
@@ -187,15 +207,46 @@ cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+extern etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+extern etiss_uint64 etiss_get_time();
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+extern etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 etiss_get_time();
+static inline etiss_uint32 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+etiss_uint32 mask = 0U;
+if (extension_enabled(cpu, system, plugin_pointers, 83U)) {
+mask = mask | 5767458U;
+if (extension_enabled(cpu, system, plugin_pointers, 86U)) {
+mask = mask | 1536;
+}
+if (extension_enabled(cpu, system, plugin_pointers, 70U)) {
+mask = mask | 24576;
+}
+if (extension_enabled(cpu, system, plugin_pointers, 88U)) {
+mask = mask | 98304;
+}
+if (1U && get_field(*((RV32IMACFD*)cpu)->CSR[384], 2147483648U) || 0U && get_field(*((RV32IMACFD*)cpu)->CSR[384], 17293822569102704640UL)) {
+mask = mask | 262144;
+}
+}
+return mask;
+}
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+static inline etiss_uint32 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+etiss_uint32 mask = 6280U;
+return mask | sstatus_mask(cpu, system, plugin_pointers);
+}
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
@@ -225,6 +276,12 @@ return etiss_get_instret(cpu, system, plugin_pointers);
 if (csr == 3202) {
 return etiss_get_instret(cpu, system, plugin_pointers) >> 32U;
 }
+if (csr == 768 || csr == 256) {
+return *((RV32IMACFD*)cpu)->CSR[768] | 8589934592UL | 34359738368UL;
+}
+if (csr == 769) {
+return (((1U) << 31) | ((((*((RV32IMACFD*)cpu)->CSR[769]) >> (0U)) & 2147483647)));
+}
 return *((RV32IMACFD*)cpu)->CSR[csr];
 }
 #endif
@@ -242,7 +299,10 @@ if (csr == 1) {
 *((RV32IMACFD*)cpu)->CSR[3] = val & 255U;
 }
  else if (csr == 768) {
-*((RV32IMACFD*)cpu)->CSR[768] = val & 136U;
+*((RV32IMACFD*)cpu)->CSR[768] = val & mstatus_mask(cpu, system, plugin_pointers);
+}
+ else if (csr == 256) {
+*((RV32IMACFD*)cpu)->CSR[768] = val & sstatus_mask(cpu, system, plugin_pointers);
 }
  else if (csr != 769) {
 *((RV32IMACFD*)cpu)->CSR[csr] = val;
@@ -251,10 +311,10 @@ if (csr == 1) {
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint8 etiss_semihost_enabled();
+extern etiss_uint8 etiss_semihost_enabled();
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
+extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
 #endif
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index e8b18908d2..454ee0ee1c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -46,38 +46,47 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOSWAPW\n");
+		cp.code() = std::string("//AMOSWAPW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n";
 }
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOSWAPW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -143,40 +152,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOADDW\n");
+		cp.code() = std::string("//AMOADDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOADDW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -242,40 +260,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOXORW\n");
+		cp.code() = std::string("//AMOXORW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOXORW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -341,40 +368,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOANDW\n");
+		cp.code() = std::string("//AMOANDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOANDW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -440,40 +476,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOORW\n");
+		cp.code() = std::string("//AMOORW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOORW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -539,40 +584,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMINW\n");
+		cp.code() = std::string("//AMOMINW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMINW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -638,40 +692,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMAXW\n");
+		cp.code() = std::string("//AMOMAXW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMAXW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -737,40 +800,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMINUW\n");
+		cp.code() = std::string("//AMOMINUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res1);\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 > *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = (res1 > *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMINUW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -836,40 +908,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMAXUW\n");
+		cp.code() = std::string("//AMOMAXUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res1);\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = (res1 < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMAXUW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index a2d450b901..d57e301789 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -42,28 +42,37 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CFLD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CFLD\n");
+		cp.code() = std::string("//CFLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -121,27 +130,36 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CFSD\n");
+		cp.code() = std::string("//CFSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CFSD\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -198,28 +216,37 @@ uimm += R_uimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CFLDSP\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CFLDSP\n");
+		cp.code() = std::string("//CFLDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[2U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -273,27 +300,36 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CFSDSP\n");
+		cp.code() = std::string("//CFSDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CFSDSP\n");
 
-		partInit.getRegisterDependencies().add(reg_name[2U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index a76e37a05b..6183c2b464 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -40,28 +40,37 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//FLD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//FLD\n");
+		cp.code() = std::string("//FLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -117,27 +126,36 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSD\n");
+		cp.code() = std::string("//FSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//FSD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -199,21 +217,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMADD_D\n");
+		cp.code() = std::string("//FMADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -279,21 +298,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMSUB_D\n");
+		cp.code() = std::string("//FMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -359,21 +379,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FNMADD_D\n");
+		cp.code() = std::string("//FNMADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -439,21 +460,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FNMSUB_D\n");
+		cp.code() = std::string("//FNMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -516,21 +538,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FADD_D\n");
+		cp.code() = std::string("//FADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -590,21 +613,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSUB_D\n");
+		cp.code() = std::string("//FSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -664,21 +688,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMUL_D\n");
+		cp.code() = std::string("//FMUL_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -738,21 +763,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FDIV_D\n");
+		cp.code() = std::string("//FDIV_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -809,21 +835,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSQRT_D\n");
+		cp.code() = std::string("//FSQRT_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -877,19 +904,20 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJ_D\n");
+		cp.code() = std::string("//FSGNJ_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -943,19 +971,20 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJN_D\n");
+		cp.code() = std::string("//FSGNJN_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1009,19 +1038,20 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJX_D\n");
+		cp.code() = std::string("//FSGNJX_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) & 9223372036854775808UL);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) & 9223372036854775808UL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1075,21 +1105,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMIN_D\n");
+		cp.code() = std::string("//FMIN_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 0U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 0U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1143,21 +1174,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMAX_D\n");
+		cp.code() = std::string("//FMAX_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 1U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 1U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1211,19 +1243,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_S_D\n");
+		cp.code() = std::string("//FCVT_S_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L + res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L + res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1277,19 +1310,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_D_S\n");
+		cp.code() = std::string("//FCVT_D_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1343,25 +1377,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FEQ_D\n");
+		cp.code() = std::string("//FEQ_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = 0U;\n";
+cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 0U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1415,25 +1450,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FLT_D\n");
+		cp.code() = std::string("//FLT_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = 0U;\n";
+cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 2U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1487,25 +1523,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FLE_D\n");
+		cp.code() = std::string("//FLE_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 1U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = 0U;\n";
+cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 1U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1556,19 +1593,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCLASS_D\n");
+		cp.code() = std::string("//FCLASS_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1619,25 +1657,26 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_W_D\n");
+		cp.code() = std::string("//FCVT_W_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_int32 res = 0U;\n";
-partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 0U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_int32 res = 0U;\n";
+cp.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 0U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1691,25 +1730,26 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_WU_D\n");
+		cp.code() = std::string("//FCVT_WU_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 1U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 1U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1763,20 +1803,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_D_W\n");
+		cp.code() = std::string("//FCVT_D_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1830,20 +1871,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_D_WU\n");
+		cp.code() = std::string("//FCVT_D_WU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index de64dd7f25..44000aadb1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -44,28 +44,37 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CFLW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = -4294967296L | res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CFLW\n");
+		cp.code() = std::string("//CFLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = -4294967296L | res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -127,27 +136,36 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CFSW\n");
+		cp.code() = std::string("//CFSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CFSW\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -206,28 +224,37 @@ uimm += R_uimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CFLWSP\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CFLWSP\n");
+		cp.code() = std::string("//CFLWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[2U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -281,27 +308,36 @@ uimm += R_uimm_2.read(ba) << 2;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CFSWSP\n");
+		cp.code() = std::string("//CFSWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CFSWSP\n");
 
-		partInit.getRegisterDependencies().add(reg_name[2U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 1ebbdc93c3..c5a54002d2 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -40,28 +40,37 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//FLW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//FLW\n");
+		cp.code() = std::string("//FLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -117,27 +126,36 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSW\n");
+		cp.code() = std::string("//FSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//FSW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -199,21 +217,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMADD_S\n");
+		cp.code() = std::string("//FMADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -279,21 +298,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMSUB_S\n");
+		cp.code() = std::string("//FMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -359,24 +379,25 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FNMADD_S\n");
+		cp.code() = std::string("//FNMADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -442,24 +463,25 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FNMSUB_S\n");
+		cp.code() = std::string("//FNMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -522,23 +544,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FADD_S\n");
+		cp.code() = std::string("//FADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -598,23 +621,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSUB_S\n");
+		cp.code() = std::string("//FSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -674,23 +698,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMUL_S\n");
+		cp.code() = std::string("//FMUL_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -750,23 +775,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FDIV_S\n");
+		cp.code() = std::string("//FDIV_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -823,22 +849,23 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSQRT_S\n");
+		cp.code() = std::string("//FSQRT_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -892,21 +919,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJ_S\n");
+		cp.code() = std::string("//FSGNJ_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -960,21 +988,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJN_S\n");
+		cp.code() = std::string("//FSGNJN_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1028,21 +1057,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJX_S\n");
+		cp.code() = std::string("//FSGNJX_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1096,23 +1126,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMIN_S\n");
+		cp.code() = std::string("//FMIN_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1166,23 +1197,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMAX_S\n");
+		cp.code() = std::string("//FMAX_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1236,26 +1268,27 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_W_S\n");
+		cp.code() = std::string("//FCVT_W_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_int32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_int32 res = 0U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1309,26 +1342,27 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_WU_S\n");
+		cp.code() = std::string("//FCVT_WU_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)((etiss_int32)(res));\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)((etiss_int32)(res));\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1382,27 +1416,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FEQ_S\n");
+		cp.code() = std::string("//FEQ_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "res = fcmp_s(frs1, frs2, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 0U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1456,27 +1491,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FLT_S\n");
+		cp.code() = std::string("//FLT_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "res = fcmp_s(frs1, frs2, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 2U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1530,27 +1566,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FLE_S\n");
+		cp.code() = std::string("//FLE_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "res = fcmp_s(frs1, frs2, 1U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 1U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1601,23 +1638,24 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCLASS_S\n");
+		cp.code() = std::string("//FCLASS_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1668,20 +1706,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_S_W\n");
+		cp.code() = std::string("//FCVT_S_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1735,20 +1774,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_S_WU\n");
+		cp.code() = std::string("//FCVT_S_WU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1799,21 +1839,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMV_X_W\n");
+		cp.code() = std::string("//FMV_X_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1861,19 +1902,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMV_W_X\n");
+		cp.code() = std::string("//FMV_W_X\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index 9375cde7fd..df71ae9ed8 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -43,27 +43,36 @@ imm += R_imm_4.read(ba) << 4;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CADDI4SPN\n");
+		cp.code() = std::string("//CADDI4SPN\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (imm) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + "U;\n";
 }
 else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[2U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CADDI4SPN\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -124,28 +133,37 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CLW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CLW\n");
+		cp.code() = std::string("//CLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -207,28 +225,37 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CSW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CSW\n");
+		cp.code() = std::string("//CSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -285,22 +312,23 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CADDI\n");
+		cp.code() = std::string("//CADDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if ((rs1 % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rs1 % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -349,17 +377,18 @@ nzimm += R_nzimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CNOP\n");
+		cp.code() = std::string("//CNOP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -417,21 +446,30 @@ imm += R_imm_11.read(ba) << 11;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CJAL\n");
+		cp.code() = std::string("//CJAL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add(reg_name[1U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add(reg_name[1U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CJAL\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -492,21 +530,22 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CLI\n");
+		cp.code() = std::string("//CLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -558,26 +597,35 @@ imm += R_imm_17.read(ba) << 17;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CLUI\n");
+		cp.code() = std::string("//CLUI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (imm == 0U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CLUI\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -632,27 +680,36 @@ nzimm += R_nzimm_9.read(ba) << 9;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CADDI16SP\n");
+		cp.code() = std::string("//CADDI16SP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (nzimm) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[2U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[2U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
 }
 else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getAffectedRegisters().add(reg_name[2U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[2U], 32);
-		partInit.getAffectedRegisters().add(reg_name[2U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CADDI16SP\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -702,20 +759,29 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//__reserved_clui\n");
+		cp.code() = std::string("//__reserved_clui\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//__reserved_clui\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -760,20 +826,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRLI\n");
+		cp.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(shamt) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -821,22 +888,23 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRAI\n");
+		cp.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (shamt) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -886,20 +954,21 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CANDI\n");
+		cp.code() = std::string("//CANDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -949,21 +1018,22 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSUB\n");
+		cp.code() = std::string("//CSUB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1011,21 +1081,22 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CXOR\n");
+		cp.code() = std::string("//CXOR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1073,21 +1144,22 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//COR\n");
+		cp.code() = std::string("//COR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1135,21 +1207,22 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CAND\n");
+		cp.code() = std::string("//CAND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1208,19 +1281,28 @@ imm += R_imm_11.read(ba) << 11;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CJ\n");
+		cp.code() = std::string("//CJ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CJ\n");
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1287,22 +1369,31 @@ imm += R_imm_8.read(ba) << 8;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CBEQZ\n");
+		cp.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] == 0U) {\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] == 0U) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CBEQZ\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1366,22 +1457,31 @@ imm += R_imm_8.read(ba) << 8;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CBNEZ\n");
+		cp.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] != 0U) {\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] != 0U) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CBNEZ\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1437,22 +1537,23 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSLLI\n");
+		cp.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (nzuimm) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(nzuimm) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(nzuimm) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rs1 % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1504,33 +1605,42 @@ uimm += R_uimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CLWSP\n");
+		cp.code() = std::string("//CLWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (rd % 32U) {
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res = mem_val_0;\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res);\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res = mem_val_0;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res);\n";
 }
 else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CLWSP\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1582,22 +1692,23 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CMV\n");
+		cp.code() = std::string("//CMV\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1642,26 +1753,35 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CJR\n");
+		cp.code() = std::string("//CJR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if (rs1) {
-partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & -2;\n";
+cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & -2;\n";
 }
 else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CJR\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1700,20 +1820,29 @@ static InstructionDefinition __reserved_cmv_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//__reserved_cmv\n");
+		cp.code() = std::string("//__reserved_cmv\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//__reserved_cmv\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1755,23 +1884,24 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CADD\n");
+		cp.code() = std::string("//CADD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1816,23 +1946,32 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CJALR\n");
+		cp.code() = std::string("//CJALR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->nextPc = new_pc & -2;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = new_pc & -2;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[1U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[1U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CJALR\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1871,20 +2010,29 @@ static InstructionDefinition cebreak_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CEBREAK\n");
+		cp.code() = std::string("//CEBREAK\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CEBREAK\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1928,28 +2076,37 @@ uimm += R_uimm_2.read(ba) << 2;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CSWSP\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CSWSP\n");
+		cp.code() = std::string("//CSWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[2U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1993,20 +2150,29 @@ static InstructionDefinition dii_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//DII\n");
+		cp.code() = std::string("//DII\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//DII\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 3662ac1f05..f6f5706f10 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -37,21 +37,22 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LUI\n");
+		cp.code() = std::string("//LUI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string((etiss_uint32)(((etiss_int32)(imm)))) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string((etiss_uint32)(((etiss_int32)(imm)))) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -99,21 +100,22 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AUIPC\n");
+		cp.code() = std::string("//AUIPC\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -167,29 +169,38 @@ imm += R_imm_20.read(ba) << 20;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//JAL\n");
+		cp.code() = std::string("//JAL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 }
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//JAL\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -246,31 +257,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//JALR\n");
+		cp.code() = std::string("//JALR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
-partInit.code() += "if (new_pc % 2U) {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
+cp.code() += "if (new_pc % 2U) {\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 }
-partInit.code() += "cpu->nextPc = new_pc & -2;\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
-// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = new_pc & -2;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//JALR\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -330,29 +350,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BEQ\n");
+		cp.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//BEQ\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -418,29 +447,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BNE\n");
+		cp.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//BNE\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -506,29 +544,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BLT\n");
+		cp.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//BLT\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -594,29 +641,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BGE\n");
+		cp.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//BGE\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -682,29 +738,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BLTU\n");
+		cp.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//BLTU\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -770,29 +835,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BGEU\n");
+		cp.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//BGEU\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -852,31 +926,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LB\n");
+		cp.code() = std::string("//LB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint8 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint8 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//LB\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -930,31 +1013,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LH\n");
+		cp.code() = std::string("//LH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint16 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint16 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//LH\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1008,31 +1100,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LW\n");
+		cp.code() = std::string("//LW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//LW\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1086,31 +1187,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LBU\n");
+		cp.code() = std::string("//LBU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint8 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint8 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//LBU\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1164,31 +1274,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LHU\n");
+		cp.code() = std::string("//LHU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint16 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint16 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//LHU\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1244,28 +1363,37 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SB\n");
+		cp.code() = std::string("//SB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint8 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint8 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//SB\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1323,28 +1451,37 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SH\n");
+		cp.code() = std::string("//SH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint16 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint16 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//SH\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1402,28 +1539,37 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SW\n");
+		cp.code() = std::string("//SW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//SW\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1479,22 +1625,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ADDI\n");
+		cp.code() = std::string("//ADDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1548,22 +1695,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLTI\n");
+		cp.code() = std::string("//SLTI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1617,22 +1765,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLTIU\n");
+		cp.code() = std::string("//SLTIU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U)) ? (1U) : (0U);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U)) ? (1U) : (0U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1686,22 +1835,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//XORI\n");
+		cp.code() = std::string("//XORI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1755,22 +1905,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ORI\n");
+		cp.code() = std::string("//ORI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1824,22 +1975,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ANDI\n");
+		cp.code() = std::string("//ANDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1893,22 +2045,23 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLLI\n");
+		cp.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1962,22 +2115,23 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRLI\n");
+		cp.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2031,22 +2185,23 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRAI\n");
+		cp.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2100,23 +2255,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ADD\n");
+		cp.code() = std::string("//ADD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2170,23 +2326,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SUB\n");
+		cp.code() = std::string("//SUB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2240,23 +2397,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLL\n");
+		cp.code() = std::string("//SLL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2310,23 +2468,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLT\n");
+		cp.code() = std::string("//SLT\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (1U) : (0U);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (1U) : (0U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2380,23 +2539,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLTU\n");
+		cp.code() = std::string("//SLTU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (1U) : (0U);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (1U) : (0U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2450,23 +2610,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//XOR\n");
+		cp.code() = std::string("//XOR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2520,23 +2681,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRL\n");
+		cp.code() = std::string("//SRL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2590,23 +2752,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRA\n");
+		cp.code() = std::string("//SRA\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2660,23 +2823,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//OR\n");
+		cp.code() = std::string("//OR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2730,23 +2894,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AND\n");
+		cp.code() = std::string("//AND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2806,18 +2971,19 @@ fm += R_fm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FENCE\n");
+		cp.code() = std::string("//FENCE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(0) + "U] = " + std::to_string(pred << 4U | succ) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "((RV32IMACFD*)cpu)->FENCE[0U] = " + std::to_string(pred << 4U | succ) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2868,20 +3034,29 @@ static InstructionDefinition ecall_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ECALL\n");
+		cp.code() = std::string("//ECALL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//ECALL\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -2917,18 +3092,19 @@ static InstructionDefinition wfi_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//WFI\n");
+		cp.code() = std::string("//WFI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "wait(1U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "wait(1U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index a44f1a2ca4..18ff0f96f4 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
@@ -40,24 +40,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MUL\n");
+		cp.code() = std::string("//MUL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)(res);\n";
+cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -111,24 +112,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MULH\n");
+		cp.code() = std::string("//MULH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)((res >> 32UL));\n";
+cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)((res >> 32UL));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -182,24 +184,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MULHSU\n");
+		cp.code() = std::string("//MULHSU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)((res >> 32UL));\n";
+cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)((res >> 32UL));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -253,24 +256,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MULHU\n");
+		cp.code() = std::string("//MULHU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint32)((res >> 32UL));\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)((res >> 32UL));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -324,34 +328,35 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//DIV\n");
+		cp.code() = std::string("//DIV\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
 etiss_uint32 MMIN = 2147483648U;
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(MMIN) + "U;\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1;\n";
-partInit.code() += "}\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(MMIN) + "U;\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1;\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -405,28 +410,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//DIVU\n");
+		cp.code() = std::string("//DIVU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1;\n";
-partInit.code() += "}\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1;\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -480,34 +486,35 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//REM\n");
+		cp.code() = std::string("//REM\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
 etiss_uint32 MMIN = 2147483648U;
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = 0U;\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "}\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = 0U;\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -561,28 +568,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//REMU\n");
+		cp.code() = std::string("//REMU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "}\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index 763ab6d678..a78ddf73a4 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
@@ -40,20 +40,29 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FENCE_I\n");
+		cp.code() = std::string("//FENCE_I\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(1) + "U] = " + std::to_string(imm) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "((RV32IMACFD*)cpu)->FENCE[1U] = " + std::to_string(imm) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//FENCE_I\n");
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index 8e9ceabbe1..1f14378c31 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:52:53 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
@@ -40,28 +40,29 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRW\n");
+		cp.code() = std::string("//CSRRW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
 else {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -115,27 +116,28 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRS\n");
+		cp.code() = std::string("//CSRRS\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if (rs1 != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | xrs1);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | xrs1);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -189,27 +191,28 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRC\n");
+		cp.code() = std::string("//CSRRC\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if (rs1 != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & ~(xrs1));\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & ~(xrs1));\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -263,23 +266,24 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRWI\n");
+		cp.code() = std::string("//CSRRWI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, " + std::to_string((etiss_uint32)(zimm)) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, " + std::to_string((etiss_uint32)(zimm)) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -333,25 +337,26 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRSI\n");
+		cp.code() = std::string("//CSRRSI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
 if (zimm != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | " + std::to_string((etiss_uint32)(zimm)) + "U);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | " + std::to_string((etiss_uint32)(zimm)) + "U);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -405,25 +410,26 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRCI\n");
+		cp.code() = std::string("//CSRRCI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
 if (zimm != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "U);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "U);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 9c25e95a77..2e56b51f59 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
@@ -31,29 +31,42 @@ static InstructionDefinition mret_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MRET\n");
+		cp.code() = std::string("//MRET\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833];\n";
-partInit.code() += "etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[768];\n";
-partInit.code() += "etiss_uint32 prev_prv = get_field(s, " + std::to_string(6144) + "U);\n";
-partInit.code() += "if (prev_prv != 3) {\n";
-partInit.code() += "s = set_field(s, " + std::to_string(131072) + "U, 0U);\n";
-partInit.code() += "}\n";
-partInit.code() += "s = set_field(s, " + std::to_string(8) + "U, get_field(s, " + std::to_string(128) + "U));\n";
-partInit.code() += "s = set_field(s, " + std::to_string(128) + "U, 1U);\n";
-partInit.code() += "s = set_field(s, " + std::to_string(6144) + "U, " + std::to_string(3) + "U);\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768) + "U] = s;\n";
-partInit.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < 3) {\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833];\n";
+cp.code() += "etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[768];\n";
+cp.code() += "etiss_uint32 prev_prv = get_field(s, 6144);\n";
+cp.code() += "if (prev_prv != 3) {\n";
+cp.code() += "s = set_field(s, 131072, 0U);\n";
+cp.code() += "}\n";
+cp.code() += "s = set_field(s, 8, get_field(s, 128));\n";
+cp.code() += "s = set_field(s, 128, 1U);\n";
+cp.code() += "s = set_field(s, 6144, (extension_enabled(cpu, system, plugin_pointers, 85U)) ? (0) : (3));\n";
+cp.code() += "*((RV32IMACFD*)cpu)->CSR[768] = s;\n";
+cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//MRET\n");
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -71,3 +84,71 @@ ss << "mret" << " # " << ba << (" []");
 		return ss.str();
 	}
 );
+
+// SRET ------------------------------------------------------------------------
+static InstructionDefinition sret_ (
+	ISA32_RV32IMACFD,
+	"sret",
+	(uint32_t) 0x10200073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//SRET\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((get_field(*((RV32IMACFD*)cpu)->CSR[768], 4194304)) ? (3) : (1))) {\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321];\n";
+cp.code() += "etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[256];\n";
+cp.code() += "etiss_uint32 prev_prv = get_field(s, 256);\n";
+cp.code() += "s = set_field(s, 2, get_field(s, 32));\n";
+cp.code() += "s = set_field(s, 32, 1U);\n";
+cp.code() += "s = set_field(s, 256, 0);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->CSR[768] = s;\n";
+cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//SRET\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sret" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index d8c464b570..29b52adf5c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -43,32 +43,41 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LRW\n");
+		cp.code() = std::string("//LRW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
-partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
+cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";
 if (rd) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//LRW\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -131,35 +140,44 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//SCW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) {\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+if (rd) {
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
+}
+cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//SCW\n");
+		cp.code() = std::string("//SCW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) {\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-if (rd) {
-partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
-}
-partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index 3aa91dfc78..15595f380c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
@@ -31,57 +31,66 @@ static InstructionDefinition ebreak_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//EBREAK\n");
+		cp.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-partInit.code() += "if (etiss_semihost_enabled()) {\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4U) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0U) + "U, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
-partInit.code() += "etiss_uint32 mem_val_2;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4U) + "U, (etiss_uint8*)&mem_val_2, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
-partInit.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
-partInit.code() += "etiss_uint32 operation = *((RV32IMACFD*)cpu)->X[10U];\n";
-partInit.code() += "etiss_uint32 parameter = *((RV32IMACFD*)cpu)->X[11U];\n";
-partInit.code() += "*((RV32IMACFD*)cpu)->X[10U] = (etiss_int32)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(32) + "U, operation, parameter));\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
+cp.code() += "if (etiss_semihost_enabled()) {\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4U) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0U) + "U, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
+cp.code() += "etiss_uint32 mem_val_2;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4U) + "U, (etiss_uint8*)&mem_val_2, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
+cp.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
+cp.code() += "etiss_uint32 operation = *((RV32IMACFD*)cpu)->X[10U];\n";
+cp.code() += "etiss_uint32 parameter = *((RV32IMACFD*)cpu)->X[11U];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[10U] = (etiss_int32)(etiss_semihost(cpu, system, plugin_pointers, 32U, operation, parameter));\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[10U], 32);
+		cp.getRegisterDependencies().add(reg_name[11U], 32);
+		cp.getAffectedRegisters().add(reg_name[10U], 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//EBREAK\n");
 
-		partInit.getRegisterDependencies().add(reg_name[10U], 32);
-		partInit.getRegisterDependencies().add(reg_name[11U], 32);
-		partInit.getAffectedRegisters().add(reg_name[10U], 32);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
index 91c2e3d048..46b6aabefe 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -116,19 +116,28 @@ error_code += R_error_code_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//trap_entry 32\n");
+		cp.code() = std::string("//trap_entry 32\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//trap_entry 32\n");
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -150,19 +159,28 @@ error_code += R_error_code_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//trap_entry 16\n");
+		cp.code() = std::string("//trap_entry 16\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//trap_entry 16\n");
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index b29892e9c3..39f9446a19 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:55:33 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the function macros for the RV64IMACFD core architecture.
  */
@@ -17,119 +17,126 @@
 
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void leave(etiss_int32 priv_lvl);
+extern void leave(etiss_int32 priv_lvl);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void wait(etiss_int32 flag);
+extern void wait(etiss_int32 flag);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
+static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
+{
+return (*((RV64IMACFD*)cpu)->CSR[769] >> (extension - 65U)) & 1U;
+}
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
+extern etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
+extern etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
+extern etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
+extern etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
+extern etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 unbox_s(etiss_uint64);
+extern etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fclass_s(etiss_uint32);
+extern etiss_uint32 unbox_s(etiss_uint64);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fget_flags();
+extern etiss_uint32 fclass_s(etiss_uint32);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
+extern etiss_uint32 fget_flags();
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
+extern etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
+extern etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
+extern etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
+extern etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
+extern etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
+extern etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
+extern etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
+extern etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
+extern etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
+extern etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 unbox_d(etiss_uint64);
+extern etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 fclass_d(etiss_uint64);
+extern etiss_uint64 unbox_d(etiss_uint64);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+extern etiss_uint64 fclass_d(etiss_uint64);
 #endif
 static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
 {
@@ -145,6 +152,18 @@ static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, voi
 {
 cpu->return_pending = 1;
 etiss_uint64 epc = cpu->instructionPointer;
+if (((RV64IMACFD*)cpu)->PRIV <= 1 && (*((RV64IMACFD*)cpu)->CSR[770] >> mcause) & 1U) {
+cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[261] & -2L);
+*((RV64IMACFD*)cpu)->CSR[321] = epc;
+*((RV64IMACFD*)cpu)->CSR[322] = mcause;
+etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[256];
+s = set_field(s, 32, get_field(s, 2));
+s = set_field(s, 256, ((RV64IMACFD*)cpu)->PRIV);
+s = set_field(s, 2, 0U);
+*((RV64IMACFD*)cpu)->CSR[256] = s;
+((RV64IMACFD*)cpu)->PRIV = (1) & 0x7;
+}
+else {
 cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773] & -2L);
 *((RV64IMACFD*)cpu)->CSR[833] = epc;
 *((RV64IMACFD*)cpu)->CSR[834] = mcause;
@@ -155,6 +174,7 @@ s = set_field(s, 8, 0U);
 *((RV64IMACFD*)cpu)->CSR[768] = s;
 ((RV64IMACFD*)cpu)->PRIV = (3) & 0x7;
 }
+}
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
@@ -187,15 +207,46 @@ cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+extern etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+extern etiss_uint64 etiss_get_time();
+#endif
+
+#ifndef ETISS_ARCH_STATIC_FN_ONLY
+extern etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 etiss_get_time();
+static inline etiss_uint64 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+etiss_uint64 mask = 0U;
+if (extension_enabled(cpu, system, plugin_pointers, 83U)) {
+mask = mask | 5767458UL;
+if (extension_enabled(cpu, system, plugin_pointers, 86U)) {
+mask = mask | 1536L;
+}
+if (extension_enabled(cpu, system, plugin_pointers, 70U)) {
+mask = mask | 24576L;
+}
+if (extension_enabled(cpu, system, plugin_pointers, 88U)) {
+mask = mask | 98304L;
+}
+if (0U && get_field(*((RV64IMACFD*)cpu)->CSR[384], 2147483648U) || 1U && get_field(*((RV64IMACFD*)cpu)->CSR[384], 17293822569102704640UL)) {
+mask = mask | 262144L;
+}
+}
+return mask;
+}
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+static inline etiss_uint64 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+etiss_uint64 mask = 6280U;
+return mask | sstatus_mask(cpu, system, plugin_pointers);
+}
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
@@ -225,6 +276,12 @@ return etiss_get_instret(cpu, system, plugin_pointers);
 if (csr == 3202) {
 return etiss_get_instret(cpu, system, plugin_pointers) >> 32U;
 }
+if (csr == 768 || csr == 256) {
+return *((RV64IMACFD*)cpu)->CSR[768] | 8589934592UL | 34359738368UL;
+}
+if (csr == 769) {
+return (((2U) << 63) | ((((*((RV64IMACFD*)cpu)->CSR[769]) >> (0U)) & 9223372036854775807)));
+}
 return *((RV64IMACFD*)cpu)->CSR[csr];
 }
 #endif
@@ -242,7 +299,10 @@ if (csr == 1) {
 *((RV64IMACFD*)cpu)->CSR[3] = val & 255UL;
 }
  else if (csr == 768) {
-*((RV64IMACFD*)cpu)->CSR[768] = val & 136UL;
+*((RV64IMACFD*)cpu)->CSR[768] = val & mstatus_mask(cpu, system, plugin_pointers);
+}
+ else if (csr == 256) {
+*((RV64IMACFD*)cpu)->CSR[768] = val & sstatus_mask(cpu, system, plugin_pointers);
 }
  else if (csr != 769) {
 *((RV64IMACFD*)cpu)->CSR[csr] = val;
@@ -251,10 +311,10 @@ if (csr == 1) {
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint8 etiss_semihost_enabled();
+extern etiss_uint8 etiss_semihost_enabled();
 #endif
 
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
+extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
 #endif
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index 92e7ea75b6..88b038cde9 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
@@ -46,38 +46,47 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOSWAPW\n");
+		cp.code() = std::string("//AMOSWAPW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
 }
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOSWAPW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -143,40 +152,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOADDW\n");
+		cp.code() = std::string("//AMOADDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOADDW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -242,40 +260,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOXORW\n");
+		cp.code() = std::string("//AMOXORW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOXORW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -341,40 +368,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOANDW\n");
+		cp.code() = std::string("//AMOANDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOANDW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -440,40 +476,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOORW\n");
+		cp.code() = std::string("//AMOORW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOORW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -539,40 +584,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMINW\n");
+		cp.code() = std::string("//AMOMINW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMINW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -638,40 +692,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMAXW\n");
+		cp.code() = std::string("//AMOMAXW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMAXW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -737,40 +800,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMINUW\n");
+		cp.code() = std::string("//AMOMINUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res1);\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = (res1 > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMINUW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -836,40 +908,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMAXUW\n");
+		cp.code() = std::string("//AMOMAXUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int32)(res1);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res1);\n";
 }
-partInit.code() += "etiss_uint32 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint32 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMAXUW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index a38b290db3..531db0e1df 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
@@ -42,28 +42,37 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CFLD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CFLD\n");
+		cp.code() = std::string("//CFLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -121,27 +130,36 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CFSD\n");
+		cp.code() = std::string("//CFSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CFSD\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -198,28 +216,37 @@ uimm += R_uimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CFLDSP\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CFLDSP\n");
+		cp.code() = std::string("//CFLDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[2U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -273,27 +300,36 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CFSDSP\n");
+		cp.code() = std::string("//CFSDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CFSDSP\n");
 
-		partInit.getRegisterDependencies().add(reg_name[2U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index 1ed56ffd27..d158ce3a74 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
@@ -40,28 +40,37 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//FLD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//FLD\n");
+		cp.code() = std::string("//FLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -117,27 +126,36 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSD\n");
+		cp.code() = std::string("//FSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//FSD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -199,21 +217,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMADD_D\n");
+		cp.code() = std::string("//FMADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -279,21 +298,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMSUB_D\n");
+		cp.code() = std::string("//FMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -359,21 +379,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FNMADD_D\n");
+		cp.code() = std::string("//FNMADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -439,21 +460,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FNMSUB_D\n");
+		cp.code() = std::string("//FNMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -516,21 +538,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FADD_D\n");
+		cp.code() = std::string("//FADD_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -590,21 +613,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSUB_D\n");
+		cp.code() = std::string("//FSUB_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -664,21 +688,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMUL_D\n");
+		cp.code() = std::string("//FMUL_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -738,21 +763,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FDIV_D\n");
+		cp.code() = std::string("//FDIV_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -809,21 +835,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSQRT_D\n");
+		cp.code() = std::string("//FSQRT_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -877,19 +904,20 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJ_D\n");
+		cp.code() = std::string("//FSGNJ_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1)) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1)) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -943,19 +971,20 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJN_D\n");
+		cp.code() = std::string("//FSGNJN_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1))) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1))) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1009,19 +1038,20 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJX_D\n");
+		cp.code() = std::string("//FSGNJX_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) & 9223372036854775808UL);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) & 9223372036854775808UL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1075,21 +1105,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMIN_D\n");
+		cp.code() = std::string("//FMIN_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 0U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 0U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1143,21 +1174,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMAX_D\n");
+		cp.code() = std::string("//FMAX_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 1U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 1U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1211,19 +1243,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_S_D\n");
+		cp.code() = std::string("//FCVT_S_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L + res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L + res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1277,19 +1310,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_D_S\n");
+		cp.code() = std::string("//FCVT_D_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1343,25 +1377,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FEQ_D\n");
+		cp.code() = std::string("//FEQ_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = 0U;\n";
+cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 0U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1415,25 +1450,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FLT_D\n");
+		cp.code() = std::string("//FLT_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = 0U;\n";
+cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 2U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1487,25 +1523,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FLE_D\n");
+		cp.code() = std::string("//FLE_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = 0U;\n";
-partInit.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 1U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = 0U;\n";
+cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 1U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1556,19 +1593,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCLASS_D\n");
+		cp.code() = std::string("//FCLASS_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1619,25 +1657,26 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_W_D\n");
+		cp.code() = std::string("//FCVT_W_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_int32 res = 0U;\n";
-partInit.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 0U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_int32 res = 0U;\n";
+cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 0U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1691,25 +1730,26 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_WU_D\n");
+		cp.code() = std::string("//FCVT_WU_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 1U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 1U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1763,20 +1803,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_D_W\n");
+		cp.code() = std::string("//FCVT_D_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1830,20 +1871,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_D_WU\n");
+		cp.code() = std::string("//FCVT_D_WU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index f4ce1fa9a5..2bc4ded06c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
@@ -40,28 +40,37 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//FLW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//FLW\n");
+		cp.code() = std::string("//FLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -117,27 +126,36 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSW\n");
+		cp.code() = std::string("//FSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//FSW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -199,21 +217,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMADD_S\n");
+		cp.code() = std::string("//FMADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -279,21 +298,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMSUB_S\n");
+		cp.code() = std::string("//FMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -359,24 +379,25 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FNMADD_S\n");
+		cp.code() = std::string("//FNMADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -442,24 +463,25 @@ rs3 += R_rs3_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FNMSUB_S\n");
+		cp.code() = std::string("//FNMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -522,23 +544,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FADD_S\n");
+		cp.code() = std::string("//FADD_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -598,23 +621,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSUB_S\n");
+		cp.code() = std::string("//FSUB_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -674,23 +698,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMUL_S\n");
+		cp.code() = std::string("//FMUL_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -750,23 +775,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FDIV_S\n");
+		cp.code() = std::string("//FDIV_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -823,22 +849,23 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSQRT_S\n");
+		cp.code() = std::string("//FSQRT_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -892,21 +919,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJ_S\n");
+		cp.code() = std::string("//FSGNJ_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -960,21 +988,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJN_S\n");
+		cp.code() = std::string("//FSGNJN_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1028,21 +1057,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FSGNJX_S\n");
+		cp.code() = std::string("//FSGNJX_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1096,23 +1126,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMIN_S\n");
+		cp.code() = std::string("//FMIN_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1166,23 +1197,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMAX_S\n");
+		cp.code() = std::string("//FMAX_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1236,26 +1268,27 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_W_S\n");
+		cp.code() = std::string("//FCVT_W_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_int32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_int32 res = 0U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1309,26 +1342,27 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_WU_S\n");
+		cp.code() = std::string("//FCVT_WU_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1382,27 +1416,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FEQ_S\n");
+		cp.code() = std::string("//FEQ_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "res = fcmp_s(frs1, frs2, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 0U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1456,27 +1491,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FLT_S\n");
+		cp.code() = std::string("//FLT_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "res = fcmp_s(frs1, frs2, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 2U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1530,27 +1566,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FLE_S\n");
+		cp.code() = std::string("//FLE_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-partInit.code() += "res = fcmp_s(frs1, frs2, 1U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 1U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1601,23 +1638,24 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCLASS_S\n");
+		cp.code() = std::string("//FCLASS_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = 0U;\n";
-partInit.code() += "res = fclass_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = 0U;\n";
+cp.code() += "res = fclass_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1668,20 +1706,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_S_W\n");
+		cp.code() = std::string("//FCVT_S_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1735,20 +1774,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_S_WU\n");
+		cp.code() = std::string("//FCVT_S_WU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1799,21 +1839,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMV_X_W\n");
+		cp.code() = std::string("//FMV_X_W\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1861,19 +1902,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMV_W_X\n");
+		cp.code() = std::string("//FMV_W_X\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index 04f367f69e..3a680a137d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
@@ -43,27 +43,36 @@ imm += R_imm_4.read(ba) << 4;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CADDI4SPN\n");
+		cp.code() = std::string("//CADDI4SPN\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (imm) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + "U;\n";
 }
 else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[2U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CADDI4SPN\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -124,28 +133,37 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CLW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CLW\n");
+		cp.code() = std::string("//CLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -207,28 +225,37 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CSW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CSW\n");
+		cp.code() = std::string("//CSW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -285,22 +312,23 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CADDI\n");
+		cp.code() = std::string("//CADDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if ((rs1 % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rs1 % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -349,17 +377,18 @@ nzimm += R_nzimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CNOP\n");
+		cp.code() = std::string("//CNOP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -408,21 +437,22 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CLI\n");
+		cp.code() = std::string("//CLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -474,26 +504,35 @@ imm += R_imm_17.read(ba) << 17;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CLUI\n");
+		cp.code() = std::string("//CLUI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (imm == 0U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CLUI\n");
 
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -548,27 +587,36 @@ nzimm += R_nzimm_9.read(ba) << 9;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CADDI16SP\n");
+		cp.code() = std::string("//CADDI16SP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (nzimm) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[2U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[2U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
 }
 else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 64);
+		cp.getAffectedRegisters().add(reg_name[2U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[2U], 64);
-		partInit.getAffectedRegisters().add(reg_name[2U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CADDI16SP\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -618,20 +666,29 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//__reserved_clui\n");
+		cp.code() = std::string("//__reserved_clui\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//__reserved_clui\n");
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -676,20 +733,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRLI\n");
+		cp.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(shamt) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -737,22 +795,23 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRAI\n");
+		cp.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (shamt) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -802,20 +861,21 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CANDI\n");
+		cp.code() = std::string("//CANDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -865,21 +925,22 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSUB\n");
+		cp.code() = std::string("//CSUB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -927,21 +988,22 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CXOR\n");
+		cp.code() = std::string("//CXOR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -989,21 +1051,22 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//COR\n");
+		cp.code() = std::string("//COR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1051,21 +1114,22 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CAND\n");
+		cp.code() = std::string("//CAND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1124,19 +1188,28 @@ imm += R_imm_11.read(ba) << 11;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CJ\n");
+		cp.code() = std::string("//CJ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CJ\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1203,22 +1276,31 @@ imm += R_imm_8.read(ba) << 8;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CBEQZ\n");
+		cp.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] == 0UL) {\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] == 0UL) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CBEQZ\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1282,22 +1364,31 @@ imm += R_imm_8.read(ba) << 8;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CBNEZ\n");
+		cp.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] != 0UL) {\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] != 0UL) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CBNEZ\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1353,22 +1444,23 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSLLI\n");
+		cp.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (nzuimm) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(nzuimm) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(nzuimm) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rs1 % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1420,33 +1512,42 @@ uimm += R_uimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CLWSP\n");
+		cp.code() = std::string("//CLWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (rd % 32U) {
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res = mem_val_0;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res = mem_val_0;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
 }
 else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CLWSP\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1498,22 +1599,23 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CMV\n");
+		cp.code() = std::string("//CMV\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1558,26 +1660,35 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CJR\n");
+		cp.code() = std::string("//CJR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (rs1) {
-partInit.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & -2L;\n";
+cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & -2L;\n";
 }
 else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CJR\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1616,20 +1727,29 @@ static InstructionDefinition __reserved_cmv_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//__reserved_cmv\n");
+		cp.code() = std::string("//__reserved_cmv\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//__reserved_cmv\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1671,23 +1791,24 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CADD\n");
+		cp.code() = std::string("//CADD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1732,23 +1853,32 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CJALR\n");
+		cp.code() = std::string("//CJALR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "cpu->nextPc = new_pc & -2L;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = new_pc & -2L;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[1U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[1U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CJALR\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1787,20 +1917,29 @@ static InstructionDefinition cebreak_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CEBREAK\n");
+		cp.code() = std::string("//CEBREAK\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//CEBREAK\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1844,28 +1983,37 @@ uimm += R_uimm_2.read(ba) << 2;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CSWSP\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CSWSP\n");
+		cp.code() = std::string("//CSWSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[2U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1909,20 +2057,29 @@ static InstructionDefinition dii_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//DII\n");
+		cp.code() = std::string("//DII\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//DII\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index 1e7b63408d..752d415734 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
@@ -37,21 +37,22 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LUI\n");
+		cp.code() = std::string("//LUI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -99,21 +100,22 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AUIPC\n");
+		cp.code() = std::string("//AUIPC\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -167,29 +169,38 @@ imm += R_imm_20.read(ba) << 20;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//JAL\n");
+		cp.code() = std::string("//JAL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 }
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//JAL\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -246,31 +257,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//JALR\n");
+		cp.code() = std::string("//JALR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
-partInit.code() += "if (new_pc % 2UL) {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
+cp.code() += "if (new_pc % 2UL) {\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 }
-partInit.code() += "cpu->nextPc = new_pc & -2L;\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
-// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = new_pc & -2L;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//JALR\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -330,29 +350,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BEQ\n");
+		cp.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//BEQ\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -418,29 +447,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BNE\n");
+		cp.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//BNE\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -506,29 +544,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BLT\n");
+		cp.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//BLT\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -594,29 +641,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BGE\n");
+		cp.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//BGE\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -682,29 +738,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BLTU\n");
+		cp.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//BLTU\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -770,29 +835,38 @@ imm += R_imm_12.read(ba) << 12;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//BGEU\n");
+		cp.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
 if (imm % 2U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
 else {
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
 }
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//BGEU\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -852,31 +926,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LB\n");
+		cp.code() = std::string("//LB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint8 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint8 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//LB\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -930,31 +1013,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LH\n");
+		cp.code() = std::string("//LH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint16 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint16 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//LH\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1008,31 +1100,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LW\n");
+		cp.code() = std::string("//LW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//LW\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1086,31 +1187,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LBU\n");
+		cp.code() = std::string("//LBU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint8 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint8 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//LBU\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1164,31 +1274,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LHU\n");
+		cp.code() = std::string("//LHU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint16 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint16 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//LHU\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1244,28 +1363,37 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SB\n");
+		cp.code() = std::string("//SB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint8 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint8 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//SB\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1323,28 +1451,37 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SH\n");
+		cp.code() = std::string("//SH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint16 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint16 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//SH\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1402,28 +1539,37 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SW\n");
+		cp.code() = std::string("//SW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//SW\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -1479,22 +1625,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ADDI\n");
+		cp.code() = std::string("//ADDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1548,22 +1695,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLTI\n");
+		cp.code() = std::string("//SLTI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1617,22 +1765,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLTIU\n");
+		cp.code() = std::string("//SLTIU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U)) ? (1U) : (0U);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U)) ? (1U) : (0U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1686,22 +1835,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//XORI\n");
+		cp.code() = std::string("//XORI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1755,22 +1905,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ORI\n");
+		cp.code() = std::string("//ORI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1824,22 +1975,23 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ANDI\n");
+		cp.code() = std::string("//ANDI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1893,22 +2045,23 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLLI\n");
+		cp.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1962,22 +2115,23 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRLI\n");
+		cp.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2031,22 +2185,23 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRAI\n");
+		cp.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2100,23 +2255,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ADD\n");
+		cp.code() = std::string("//ADD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2170,23 +2326,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SUB\n");
+		cp.code() = std::string("//SUB\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2240,23 +2397,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLL\n");
+		cp.code() = std::string("//SLL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2310,23 +2468,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLT\n");
+		cp.code() = std::string("//SLT\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (1U) : (0U);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (1U) : (0U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2380,23 +2539,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLTU\n");
+		cp.code() = std::string("//SLTU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (1U) : (0U);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (1U) : (0U);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2450,23 +2610,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//XOR\n");
+		cp.code() = std::string("//XOR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2520,23 +2681,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRL\n");
+		cp.code() = std::string("//SRL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2590,23 +2752,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRA\n");
+		cp.code() = std::string("//SRA\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2660,23 +2823,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//OR\n");
+		cp.code() = std::string("//OR\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2730,23 +2894,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AND\n");
+		cp.code() = std::string("//AND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2806,18 +2971,19 @@ fm += R_fm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FENCE\n");
+		cp.code() = std::string("//FENCE\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FENCE[" + std::to_string(0) + "U] = " + std::to_string(pred << 4U | succ) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "((RV64IMACFD*)cpu)->FENCE[0U] = " + std::to_string(pred << 4U | succ) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -2868,20 +3034,29 @@ static InstructionDefinition ecall_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ECALL\n");
+		cp.code() = std::string("//ECALL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.code() = std::string("//ECALL\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -2917,18 +3092,19 @@ static InstructionDefinition wfi_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//WFI\n");
+		cp.code() = std::string("//WFI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "wait(1U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "wait(1U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index dd21f7b4c8..3fe27802bf 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:55:33 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
@@ -40,24 +40,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MUL\n");
+		cp.code() = std::string("//MUL\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
+cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -111,24 +112,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MULH\n");
+		cp.code() = std::string("//MULH\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64ULL));\n";
+cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((res >> 64ULL));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -182,24 +184,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MULHSU\n");
+		cp.code() = std::string("//MULHSU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64ULL));\n";
+cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((res >> 64ULL));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -253,24 +256,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MULHU\n");
+		cp.code() = std::string("//MULHU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint128 res = (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((res >> 64ULL));\n";
+cp.code() += "etiss_uint128 res = (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((res >> 64ULL));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -324,34 +328,35 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//DIV\n");
+		cp.code() = std::string("//DIV\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
 etiss_uint64 MMIN = 9223372036854775808UL;
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = " + std::to_string(MMIN) + "U;\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
-partInit.code() += "}\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(MMIN) + "U;\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1L;\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -405,28 +410,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//DIVU\n");
+		cp.code() = std::string("//DIVU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
-partInit.code() += "}\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1L;\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -480,34 +486,35 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//REM\n");
+		cp.code() = std::string("//REM\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
 etiss_uint64 MMIN = 9223372036854775808UL;
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = 0UL;\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "}\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = 0UL;\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -561,28 +568,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//REMU\n");
+		cp.code() = std::string("//REMU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "}\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index 614f96b271..bfeb997b6b 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
@@ -46,38 +46,47 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOSWAPD\n");
+		cp.code() = std::string("//AMOSWAPD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
 }
-partInit.code() += "etiss_uint64 mem_val_1;\n";
-partInit.code() += "mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint64 mem_val_1;\n";
+cp.code() += "mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOSWAPD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -143,40 +152,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOADDD\n");
+		cp.code() = std::string("//AMOADDD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int64 res = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOADDD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -242,40 +260,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOXORD\n");
+		cp.code() = std::string("//AMOXORD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int64 res = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOXORD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -341,40 +368,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOANDD\n");
+		cp.code() = std::string("//AMOANDD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int64 res = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOANDD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -440,40 +476,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOORD\n");
+		cp.code() = std::string("//AMOORD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int64 res = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint64 res2 = (((res) << 64) | (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-partInit.code() += "etiss_uint64 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint64 res2 = (((res) << 64) | (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
+cp.code() += "etiss_uint64 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOORD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -539,40 +584,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMIND\n");
+		cp.code() = std::string("//AMOMIND\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int64 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int64 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res1;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
 }
-partInit.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint64 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+cp.code() += "etiss_uint64 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMIND\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -638,40 +692,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMAXD\n");
+		cp.code() = std::string("//AMOMAXD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int64 res = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res);\n";
-partInit.code() += "etiss_uint64 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res);\n";
+cp.code() += "etiss_uint64 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMAXD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -737,40 +800,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMINUD\n");
+		cp.code() = std::string("//AMOMINUD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint64 res = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint64 res = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
 }
-partInit.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res);\n";
-partInit.code() += "etiss_uint64 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res);\n";
+cp.code() += "etiss_uint64 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMINUD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -836,40 +908,49 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//AMOMAXUD\n");
+		cp.code() = std::string("//AMOMAXUD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint64 res1 = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint64 res1 = mem_val_0;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res1);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res1);\n";
 }
-partInit.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
-partInit.code() += "etiss_uint64 mem_val_1;\n";
-partInit.code() += "mem_val_1 = res2;\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+cp.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+cp.code() += "etiss_uint64 mem_val_1;\n";
+cp.code() += "mem_val_1 = res2;\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//AMOMAXUD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index c50e9b83b5..a83c47f11e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
@@ -40,21 +40,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_L_D\n");
+		cp.code() = std::string("//FCVT_L_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 0U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 0U, " + std::to_string(rm) + "U);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -108,21 +109,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_LU_D\n");
+		cp.code() = std::string("//FCVT_LU_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 1U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 1U, " + std::to_string(rm) + "U);\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -176,20 +178,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_D_L\n");
+		cp.code() = std::string("//FCVT_D_L\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 2U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 2U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -243,20 +246,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_D_LU\n");
+		cp.code() = std::string("//FCVT_D_LU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 3U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 3U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -307,19 +311,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMV_X_D\n");
+		cp.code() = std::string("//FMV_X_D\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U];\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U];\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -367,19 +372,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FMV_D_X\n");
+		cp.code() = std::string("//FMV_D_X\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index 7131be4f5d..f9c135ac82 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
@@ -40,24 +40,25 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_L_S\n");
+		cp.code() = std::string("//FCVT_L_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 0U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 0U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -111,24 +112,25 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_LU_S\n");
+		cp.code() = std::string("//FCVT_LU_S\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 1U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 1U, " + std::to_string(rm) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
-partInit.code() += "etiss_uint32 flags = fget_flags();\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "etiss_uint32 flags = fget_flags();\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -182,20 +184,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_S_L\n");
+		cp.code() = std::string("//FCVT_S_L\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 2U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 2U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -249,20 +252,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FCVT_S_LU\n");
+		cp.code() = std::string("//FCVT_S_LU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 3U, " + std::to_string(rm) + "U);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 3U, " + std::to_string(rm) + "U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index 3d5f28852e..c0dce6f47d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
@@ -39,22 +39,23 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CADDIW\n");
+		cp.code() = std::string("//CADDIW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if ((rs1 % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "U] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rs1 % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -106,20 +107,21 @@ nzuimm += R_nzuimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRLI\n");
+		cp.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(nzuimm) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(nzuimm) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -171,20 +173,21 @@ shamt += R_shamt_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRAI\n");
+		cp.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -236,25 +239,34 @@ shamt += R_shamt_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSLLI\n");
+		cp.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
 if (rs1 == 0U) {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] << " + std::to_string(shamt) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] << " + std::to_string(shamt) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CSLLI\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1], 64);
-		partInit.getAffectedRegisters().add(reg_name[rs1], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -309,28 +321,37 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CLD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int64)(mem_val_0);\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CLD\n");
+		cp.code() = std::string("//CLD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int64)(mem_val_0);\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -388,28 +409,37 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CSD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CSD\n");
+		cp.code() = std::string("//CSD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -462,22 +492,23 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSUBW\n");
+		cp.code() = std::string("//CSUBW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -525,22 +556,23 @@ rd += R_rd_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CADDW\n");
+		cp.code() = std::string("//CADDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd + 8U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -592,35 +624,44 @@ uimm += R_uimm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CLDSP\n");
+		cp.code() = std::string("//CLDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int64 res = mem_val_0;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int64 res = mem_val_0;\n";
 if (rd % 32U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = res;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
 }
 else {
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//CLDSP\n");
 
-		partInit.getRegisterDependencies().add(reg_name[2U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -674,28 +715,37 @@ uimm += R_uimm_3.read(ba) << 3;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//CSDSP\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[2U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//CSDSP\n");
+		cp.code() = std::string("//CSDSP\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[2U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index 5f56d3374d..e76dab4e66 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
@@ -40,31 +40,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LWU\n");
+		cp.code() = std::string("//LWU\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//LWU\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -118,31 +127,40 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LD\n");
+		cp.code() = std::string("//LD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(res);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//LD\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -198,28 +216,37 @@ imm += R_imm_5.read(ba) << 5;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//SD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//SD\n");
+		cp.code() = std::string("//SD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -275,22 +302,23 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLLI\n");
+		cp.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -344,22 +372,23 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRLI\n");
+		cp.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -413,22 +442,23 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRAI\n");
+		cp.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -482,23 +512,24 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ADDIW\n");
+		cp.code() = std::string("//ADDIW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
+cp.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -552,23 +583,24 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLLIW\n");
+		cp.code() = std::string("//SLLIW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) << " + std::to_string(shamt) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) << " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -622,23 +654,24 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRLIW\n");
+		cp.code() = std::string("//SRLIW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -692,23 +725,24 @@ shamt += R_shamt_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRAIW\n");
+		cp.code() = std::string("//SRAIW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(sh_val);\n";
+cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(sh_val);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -762,24 +796,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//ADDW\n");
+		cp.code() = std::string("//ADDW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
+cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -833,24 +868,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SUBW\n");
+		cp.code() = std::string("//SUBW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
+cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -904,25 +940,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SLLW\n");
+		cp.code() = std::string("//SLLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
-partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) << count;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
+cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) << count;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -976,25 +1013,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRLW\n");
+		cp.code() = std::string("//SRLW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
-partInit.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> count;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
+cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> count;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -1048,25 +1086,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//SRAW\n");
+		cp.code() = std::string("//SRAW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
-partInit.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> count;\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(sh_val);\n";
+cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
+cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> count;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(sh_val);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index 244bf9f96a..f450aca453 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
@@ -40,23 +40,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MULW\n");
+		cp.code() = std::string("//MULW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -110,34 +111,35 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//DIVW\n");
+		cp.code() = std::string("//DIVW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
 etiss_int32 MMIN = 2147483648U;
-partInit.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -2147483648L;\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])));\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
-partInit.code() += "}\n";
+cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -2147483648L;\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])));\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1L;\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -191,28 +193,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//DIVUW\n");
+		cp.code() = std::string("//DIVUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) != 0U) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = -1L;\n";
-partInit.code() += "}\n";
+cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) != 0U) {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1L;\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -266,34 +269,35 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//REMW\n");
+		cp.code() = std::string("//REMW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
 etiss_int32 MMIN = 2147483648U;
-partInit.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = 0UL;\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])));\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])));\n";
-partInit.code() += "}\n";
+cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = 0UL;\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])));\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])));\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -347,28 +351,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//REMUW\n");
+		cp.code() = std::string("//REMUW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) != 0U) {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])));\n";
-partInit.code() += "}\n";
+cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) != 0U) {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])));\n";
+cp.code() += "}\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index fef7afae29..c2a916e9d0 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
@@ -40,20 +40,29 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//FENCE_I\n");
+		cp.code() = std::string("//FENCE_I\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "((RV64IMACFD*)cpu)->FENCE[" + std::to_string(1) + "U] = " + std::to_string(imm) + "U;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "((RV64IMACFD*)cpu)->FENCE[1U] = " + std::to_string(imm) + "U;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//FENCE_I\n");
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index 01da76051d..4f38bc7c56 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
@@ -40,28 +40,29 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRW\n");
+		cp.code() = std::string("//CSRRW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
 else {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -115,27 +116,28 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRS\n");
+		cp.code() = std::string("//CSRRS\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if (rs1 != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | xrs1);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | xrs1);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -189,27 +191,28 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRC\n");
+		cp.code() = std::string("//CSRRC\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-partInit.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
 if (rs1 != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & ~(xrs1));\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & ~(xrs1));\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -263,23 +266,24 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRWI\n");
+		cp.code() = std::string("//CSRRWI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, " + std::to_string((etiss_uint64)(zimm)) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, " + std::to_string((etiss_uint64)(zimm)) + "U);\n";
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -333,25 +337,26 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRSI\n");
+		cp.code() = std::string("//CSRRSI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
 if (zimm != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | " + std::to_string((etiss_uint64)(zimm)) + "U);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | " + std::to_string((etiss_uint64)(zimm)) + "U);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
@@ -405,25 +410,26 @@ csr += R_csr_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//CSRRCI\n");
+		cp.code() = std::string("//CSRRCI\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
 if (zimm != 0U) {
-partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "U);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "U);\n";
 }
 if ((rd % 32U) != 0U) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = xrd;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index 3ba7c5c4f0..c8b4e1ebb8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
@@ -31,29 +31,42 @@ static InstructionDefinition mret_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//MRET\n");
+		cp.code() = std::string("//MRET\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833];\n";
-partInit.code() += "etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[768];\n";
-partInit.code() += "etiss_uint64 prev_prv = get_field(s, " + std::to_string(6144) + "U);\n";
-partInit.code() += "if (prev_prv != 3L) {\n";
-partInit.code() += "s = set_field(s, " + std::to_string(131072) + "U, 0U);\n";
-partInit.code() += "}\n";
-partInit.code() += "s = set_field(s, " + std::to_string(8) + "U, get_field(s, " + std::to_string(128) + "U));\n";
-partInit.code() += "s = set_field(s, " + std::to_string(128) + "U, 1U);\n";
-partInit.code() += "s = set_field(s, " + std::to_string(6144) + "U, " + std::to_string(3) + "U);\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->CSR[" + std::to_string(768) + "U] = s;\n";
-partInit.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < 3) {\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833];\n";
+cp.code() += "etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[768];\n";
+cp.code() += "etiss_uint64 prev_prv = get_field(s, 6144);\n";
+cp.code() += "if (prev_prv != 3L) {\n";
+cp.code() += "s = set_field(s, 131072, 0U);\n";
+cp.code() += "}\n";
+cp.code() += "s = set_field(s, 8, get_field(s, 128));\n";
+cp.code() += "s = set_field(s, 128, 1U);\n";
+cp.code() += "s = set_field(s, 6144, (extension_enabled(cpu, system, plugin_pointers, 85U)) ? (0) : (3));\n";
+cp.code() += "*((RV64IMACFD*)cpu)->CSR[768] = s;\n";
+cp.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//MRET\n");
 
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -71,3 +84,71 @@ ss << "mret" << " # " << ba << (" []");
 		return ss.str();
 	}
 );
+
+// SRET ------------------------------------------------------------------------
+static InstructionDefinition sret_ (
+	ISA32_RV64IMACFD,
+	"sret",
+	(uint32_t) 0x10200073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//SRET\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < ((get_field(*((RV64IMACFD*)cpu)->CSR[768], 4194304)) ? (3) : (1))) {\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321];\n";
+cp.code() += "etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[256];\n";
+cp.code() += "etiss_uint64 prev_prv = get_field(s, 256);\n";
+cp.code() += "s = set_field(s, 2, get_field(s, 32));\n";
+cp.code() += "s = set_field(s, 32, 1U);\n";
+cp.code() += "s = set_field(s, 256, 0);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->CSR[768] = s;\n";
+cp.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//SRET\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sret" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index 8780c54c81..f8df68b3f4 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
@@ -43,32 +43,41 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LRD\n");
+		cp.code() = std::string("//LRD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
+cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
 if (rd) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//LRD\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -131,35 +140,44 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//SCD\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
+cp.code() += "etiss_uint64 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+if (rd) {
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
+}
+cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//SCD\n");
+		cp.code() = std::string("//SCD\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
-partInit.code() += "etiss_uint64 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-if (rd) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
-}
-partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index 49dd0fed7f..40ba93e2e1 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
@@ -43,32 +43,41 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//LRW\n");
+		cp.code() = std::string("//LRW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
-partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
+cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
 if (rd) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = (etiss_int64)(res);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
 }
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//LRW\n");
 
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},
@@ -131,35 +140,44 @@ aq += R_aq_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//SCW\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+if (rd) {
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
+}
+cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
-		partInit.code() = std::string("//SCW\n");
+		cp.code() = std::string("//SCW\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-partInit.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-partInit.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-if (rd) {
-partInit.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "U] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
-}
-partInit.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
-
-		partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		partInit.getAffectedRegisters().add(reg_name[rd % 32], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+	}
 
 		return true;
 	},
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index c091668c98..b088f23676 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.
@@ -31,57 +31,66 @@ static InstructionDefinition ebreak_ (
 
 // -----------------------------------------------------------------------------
 
-		CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
-		partInit.code() = std::string("//EBREAK\n");
+		cp.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-partInit.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-partInit.code() += "if (etiss_semihost_enabled()) {\n";
-partInit.code() += "etiss_uint32 mem_val_0;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4UL) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
-partInit.code() += "etiss_uint32 mem_val_1;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0UL) + "U, (etiss_uint8*)&mem_val_1, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
-partInit.code() += "etiss_uint32 mem_val_2;\n";
-partInit.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4UL) + "U, (etiss_uint8*)&mem_val_2, 4);\n";
-partInit.code() += "if (cpu->exception) {\n";
-partInit.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
-partInit.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
-partInit.code() += "etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10U];\n";
-partInit.code() += "etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11U];\n";
-partInit.code() += "*((RV64IMACFD*)cpu)->X[10U] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, " + std::to_string(64) + "U, operation, parameter));\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "}\n";
-partInit.code() += "else {\n";
-partInit.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, " + std::to_string(3) + "U);\n";
-partInit.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-partInit.code() += "}\n";
-partInit.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-partInit.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-partInit.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
+cp.code() += "if (etiss_semihost_enabled()) {\n";
+cp.code() += "etiss_uint32 mem_val_0;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4UL) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
+cp.code() += "etiss_uint32 mem_val_1;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0UL) + "U, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
+cp.code() += "etiss_uint32 mem_val_2;\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4UL) + "U, (etiss_uint8*)&mem_val_2, 4);\n";
+cp.code() += "if (cpu->exception) {\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
+cp.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
+cp.code() += "etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10U];\n";
+cp.code() += "etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11U];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[10U] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64U, operation, parameter));\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "}\n";
+cp.code() += "else {\n";
+cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "}\n";
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[10U], 64);
+		cp.getRegisterDependencies().add(reg_name[11U], 64);
+		cp.getAffectedRegisters().add(reg_name[10U], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//EBREAK\n");
 
-		partInit.getRegisterDependencies().add(reg_name[10U], 64);
-		partInit.getRegisterDependencies().add(reg_name[11U], 64);
-		partInit.getAffectedRegisters().add(reg_name[10U], 64);
-		partInit.getAffectedRegisters().add("instructionPointer", 32);
+// -----------------------------------------------------------------------------
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
 
 		return true;
 	},

From a09aea80a433d6b35a2df82176a4f6e39a8fa3e5 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Mon, 27 Mar 2023 14:27:12 +0200
Subject: [PATCH 25/44] update arch

---
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index 72b58c7f0a..bf44157a74 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -280,7 +280,7 @@ if (csr == 768 || csr == 256) {
 return *((RV32IMACFD*)cpu)->CSR[768] | 8589934592UL | 34359738368UL;
 }
 if (csr == 769) {
-return (((1U) << 31) | ((((*((RV32IMACFD*)cpu)->CSR[769]) >> (0U)) & 2147483647)));
+return (((1U) << 30) | ((((*((RV32IMACFD*)cpu)->CSR[769]) >> (0U)) & 1073741823)));
 }
 return *((RV32IMACFD*)cpu)->CSR[csr];
 }
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index 39f9446a19..fa540047e2 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -280,7 +280,7 @@ if (csr == 768 || csr == 256) {
 return *((RV64IMACFD*)cpu)->CSR[768] | 8589934592UL | 34359738368UL;
 }
 if (csr == 769) {
-return (((2U) << 63) | ((((*((RV64IMACFD*)cpu)->CSR[769]) >> (0U)) & 9223372036854775807)));
+return (((2U) << 62) | ((((*((RV64IMACFD*)cpu)->CSR[769]) >> (0U)) & 4611686018427387903)));
 }
 return *((RV64IMACFD*)cpu)->CSR[csr];
 }
@@ -317,4 +317,4 @@ extern etiss_uint8 etiss_semihost_enabled();
 #ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
 #endif
-#endif
\ No newline at end of file
+#endif

From e109ba8eb5f848cfe1163ed7ef3325ed36c68a80 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 18:11:48 +0200
Subject: [PATCH 26/44] link arch plugins against jit plugins

---
 cmake/ETISSPlugin.cmake    | 2 ++
 src/jitlibs/CMakeLists.txt | 1 +
 2 files changed, 3 insertions(+)

diff --git a/cmake/ETISSPlugin.cmake b/cmake/ETISSPlugin.cmake
index a656bc1d8c..174015b04a 100644
--- a/cmake/ETISSPlugin.cmake
+++ b/cmake/ETISSPlugin.cmake
@@ -27,4 +27,6 @@ ENDMACRO()
 
 MACRO(ETISSPluginArch ProjName)
     ETISSPluginArchName(${ProjName} ${ProjName})
+    get_property(jitlibs GLOBAL PROPERTY etiss_jitlibs)
+    TARGET_LINK_LIBRARIES(${PROJECT_NAME} PUBLIC "${jitlibs}")
 ENDMACRO()
diff --git a/src/jitlibs/CMakeLists.txt b/src/jitlibs/CMakeLists.txt
index 300e31a4ee..292e2267ed 100644
--- a/src/jitlibs/CMakeLists.txt
+++ b/src/jitlibs/CMakeLists.txt
@@ -1,4 +1,5 @@
 MACRO(InstallJitLib TARGET_NAME)
+    set_property(GLOBAL APPEND PROPERTY etiss_jitlibs ${TARGET_NAME})
     INSTALL(TARGETS ${TARGET_NAME} DESTINATION include/jit/etiss/jit)
 ENDMACRO()
 

From 31758752ec7e5183f9688785bf4f8162937a2c86 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 18:15:47 +0200
Subject: [PATCH 27/44] change file/functionglobalcode to vector

---
 ArchImpl/OR1K/OR1KArch.cpp                                | 4 ++--
 ArchImpl/RISCV/RISCVArch.cpp                              | 2 +-
 ArchImpl/RISCV64/RISCV64Arch.cpp                          | 2 +-
 include/etiss/CodePart.h                                  | 8 ++++----
 src/IntegratedLibrary/InstructionAccurateCallback.cpp     | 2 +-
 .../InstructionSpecificAddressCallback.cpp                | 4 ++--
 src/IntegratedLibrary/PrintInstruction.cpp                | 2 +-
 src/IntegratedLibrary/VariableValueLogger.cpp             | 2 +-
 src/IntegratedLibrary/gdb/GDBServer.cpp                   | 2 +-
 src/Translation.cpp                                       | 6 +++---
 10 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/ArchImpl/OR1K/OR1KArch.cpp b/ArchImpl/OR1K/OR1KArch.cpp
index f7c2ef9d71..32eb84f9e4 100644
--- a/ArchImpl/OR1K/OR1KArch.cpp
+++ b/ArchImpl/OR1K/OR1KArch.cpp
@@ -389,8 +389,8 @@ void OR1KArch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const
 void OR1KArch::initCodeBlock(etiss::CodeBlock &cb) const
 {
 
-    cb.fileglobalCode().insert("#include \"Arch/OR1K/OR1K.h\"\n");
-    cb.fileglobalCode().insert("#include \"etiss/jit/fpu/softfloat.h\"\n");
+    cb.fileglobalCode().push_back("#include \"Arch/OR1K/OR1K.h\"\n");
+    cb.fileglobalCode().push_back("#include \"etiss/jit/fpu/softfloat.h\"\n");
 }
 
 const std::set<std::string> &OR1KArch::getHeaders() const
diff --git a/ArchImpl/RISCV/RISCVArch.cpp b/ArchImpl/RISCV/RISCVArch.cpp
index f359d3394c..134913e0d1 100644
--- a/ArchImpl/RISCV/RISCVArch.cpp
+++ b/ArchImpl/RISCV/RISCVArch.cpp
@@ -216,7 +216,7 @@ const std::set<std::string> & RISCVArch::getHeaders() const
 		
 void RISCVArch::initCodeBlock(etiss::CodeBlock & cb) const
 {
-    cb.fileglobalCode().insert("#include \"Arch/RISCV/RISCV.h\"\n");
+    cb.fileglobalCode().push_back("#include \"Arch/RISCV/RISCV.h\"\n");
 }
 
 etiss::plugin::gdb::GDBCore & RISCVArch::getGDBCore()
diff --git a/ArchImpl/RISCV64/RISCV64Arch.cpp b/ArchImpl/RISCV64/RISCV64Arch.cpp
index 66864a3021..ae7c15ec69 100644
--- a/ArchImpl/RISCV64/RISCV64Arch.cpp
+++ b/ArchImpl/RISCV64/RISCV64Arch.cpp
@@ -222,7 +222,7 @@ const std::set<std::string> & RISCV64Arch::getHeaders() const
 		
 void RISCV64Arch::initCodeBlock(etiss::CodeBlock & cb) const
 {
-    cb.fileglobalCode().insert("#include \"Arch/RISCV64/RISCV64.h\"\n");
+    cb.fileglobalCode().push_back("#include \"Arch/RISCV64/RISCV64.h\"\n");
 }
 
 etiss::plugin::gdb::GDBCore & RISCV64Arch::getGDBCore()
diff --git a/include/etiss/CodePart.h b/include/etiss/CodePart.h
index b64e0697ab..af857fccd1 100644
--- a/include/etiss/CodePart.h
+++ b/include/etiss/CodePart.h
@@ -600,16 +600,16 @@ class CodeBlock
         return lines_.back();
     }
     inline unsigned length() const { return (unsigned)lines_.size(); }
-    inline std::set<std::string> &fileglobalCode() { return fileglobal_code; }
-    inline std::set<std::string> &functionglobalCode() { return functionglobal_code; }
+    inline std::vector<std::string> &fileglobalCode() { return fileglobal_code; }
+    inline std::vector<std::string> &functionglobalCode() { return functionglobal_code; }
     void toCode(std::stringstream &out, const std::string &funcname, std::set<std::string> *fileglobalcode);
 
   private:
     std::vector<Line> lines_;
     etiss::uint64 startindex_;
     etiss::uint64 endaddress_;
-    std::set<std::string> fileglobal_code;
-    std::set<std::string> functionglobal_code;
+    std::vector<std::string> fileglobal_code;
+    std::vector<std::string> functionglobal_code;
 };
 } // namespace etiss
 #endif
diff --git a/src/IntegratedLibrary/InstructionAccurateCallback.cpp b/src/IntegratedLibrary/InstructionAccurateCallback.cpp
index bd07731825..668db78ba2 100644
--- a/src/IntegratedLibrary/InstructionAccurateCallback.cpp
+++ b/src/IntegratedLibrary/InstructionAccurateCallback.cpp
@@ -64,7 +64,7 @@ InstructionAccurateCallback::~InstructionAccurateCallback() {}
 
 void InstructionAccurateCallback::initCodeBlock(etiss::CodeBlock &block) const
 {
-    block.fileglobalCode().insert("extern void etiss_plugin_InstructionAccurateCallback(void *); ");
+    block.fileglobalCode().push_back("extern void etiss_plugin_InstructionAccurateCallback(void *); ");
 }
 
 void InstructionAccurateCallback::finalizeInstrSet(etiss::instr::ModedInstructionSet &mis) const
diff --git a/src/IntegratedLibrary/InstructionSpecificAddressCallback.cpp b/src/IntegratedLibrary/InstructionSpecificAddressCallback.cpp
index e130b971f8..dc55bf2cc6 100644
--- a/src/IntegratedLibrary/InstructionSpecificAddressCallback.cpp
+++ b/src/IntegratedLibrary/InstructionSpecificAddressCallback.cpp
@@ -84,8 +84,8 @@ InstructionSpecificAddressCallback::~InstructionSpecificAddressCallback() {}
 
 void InstructionSpecificAddressCallback::initCodeBlock(etiss::CodeBlock &block) const
 {
-    block.fileglobalCode().insert("extern int InstructionSpecificAddressCallback_callback(void *);\n");
-    block.functionglobalCode().insert("  if ( (*(uint32_t*)(" + getPointerCode() +
+    block.fileglobalCode().push_back("extern int InstructionSpecificAddressCallback_callback(void *);\n");
+    block.functionglobalCode().push_back("  if ( (*(uint32_t*)(" + getPointerCode() +
                                       ")) != " + etiss::toString(pluginData_.state_) +
                                       ") return ETISS_RETURNCODE_RELOADCURRENTBLOCK;\n"); // add print function
 }
diff --git a/src/IntegratedLibrary/PrintInstruction.cpp b/src/IntegratedLibrary/PrintInstruction.cpp
index 1e22ad61ff..f851d744f4 100644
--- a/src/IntegratedLibrary/PrintInstruction.cpp
+++ b/src/IntegratedLibrary/PrintInstruction.cpp
@@ -62,7 +62,7 @@ using namespace etiss::plugin;
 
 void PrintInstruction::initCodeBlock(etiss::CodeBlock &block) const
 {
-    block.fileglobalCode().insert("extern void PrintInstruction_print(const char *,uint64_t);"); // add print function
+    block.fileglobalCode().push_back("extern void PrintInstruction_print(const char *,uint64_t);"); // add print function
 }
 
 void PrintInstruction::finalizeInstrSet(etiss::instr::ModedInstructionSet &mis) const
diff --git a/src/IntegratedLibrary/VariableValueLogger.cpp b/src/IntegratedLibrary/VariableValueLogger.cpp
index 9d64ba1927..eaa5c35e78 100644
--- a/src/IntegratedLibrary/VariableValueLogger.cpp
+++ b/src/IntegratedLibrary/VariableValueLogger.cpp
@@ -76,7 +76,7 @@ VariableValueLogger::VariableValueLogger(
 
 void VariableValueLogger::initCodeBlock(etiss::CodeBlock &block) const
 {
-    block.fileglobalCode().insert("extern void etiss_plugin_VariableValueLogger(void *); ");
+    block.fileglobalCode().push_back("extern void etiss_plugin_VariableValueLogger(void *); ");
 }
 
 void VariableValueLogger::finalizeInstrSet(etiss::instr::ModedInstructionSet &mis) const
diff --git a/src/IntegratedLibrary/gdb/GDBServer.cpp b/src/IntegratedLibrary/gdb/GDBServer.cpp
index f706a1246d..0f903d2679 100644
--- a/src/IntegratedLibrary/gdb/GDBServer.cpp
+++ b/src/IntegratedLibrary/gdb/GDBServer.cpp
@@ -277,7 +277,7 @@ void Server::finalizeInstrSet(etiss::instr::ModedInstructionSet &mis) const
 void Server::finalizeCodeBlock(etiss::CodeBlock &cb) const
 {
 
-    cb.fileglobalCode().insert("extern etiss_int32 gdb_pre_instruction(ETISS_CPU * ,ETISS_System * ,void * );extern "
+    cb.fileglobalCode().push_back("extern etiss_int32 gdb_pre_instruction(ETISS_CPU * ,ETISS_System * ,void * );extern "
                                "void gdb_pre_instruction_noreturn(ETISS_CPU * ,ETISS_System * ,void * );");
 }
 
diff --git a/src/Translation.cpp b/src/Translation.cpp
index be485b340c..af2db7510f 100644
--- a/src/Translation.cpp
+++ b/src/Translation.cpp
@@ -318,7 +318,7 @@ BlockLink *Translation::getBlock(BlockLink *prev, const etiss::uint64 &instructi
     }
 
     CodeBlock block(instructionindex);
-    block.fileglobalCode().insert("#include \"etiss/jit/CPU.h\"\n"
+    block.fileglobalCode().push_back("#include \"etiss/jit/CPU.h\"\n"
                                   "#include \"etiss/jit/System.h\"\n"
                                   "#include \"etiss/jit/libresources.h\"\n"
                                   "#include \"etiss/jit/libsemihost.h\"\n"
@@ -326,10 +326,10 @@ BlockLink *Translation::getBlock(BlockLink *prev, const etiss::uint64 &instructi
                                   "#include \"etiss/jit/libCSRCounters.h\"\n");
 
     for(auto &it: jitExtHeaders()){
-        if(it != "") block.fileglobalCode().insert("#include \"" + it + "\"\n");
+        if(it != "") block.fileglobalCode().push_back("#include \"" + it + "\"\n");
     }
 
-    block.functionglobalCode().insert("if (cpu->mode != " + toString(cpu_.mode) +
+    block.functionglobalCode().push_back("if (cpu->mode != " + toString(cpu_.mode) +
                                       ") return ETISS_RETURNCODE_RELOADCURRENTBLOCK;");
 
     plugins_initCodeBlock_(plugins_array_, block);

From ca4cb5cf0b0be8d03db78d5bb2bffb96283afd5e Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 18:16:09 +0200
Subject: [PATCH 28/44] only signal mmu if there is one

---
 src/mm/MMU.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mm/MMU.cpp b/src/mm/MMU.cpp
index 04643cf335..b57de82c76 100644
--- a/src/mm/MMU.cpp
+++ b/src/mm/MMU.cpp
@@ -264,6 +264,8 @@ extern "C"
                                      "indirectly from ETISS_signalChangedRegisterValue()");
             return;
         }
-        core->getMMU()->SignalMMU(mmu_signal_);
+        auto mmu = core->getMMU();
+        if (mmu)
+            mmu->SignalMMU(mmu_signal_);
     }
 }

From 3367f96ff6a36cafda56071e5bfa48079fcaea0d Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 18:18:06 +0200
Subject: [PATCH 29/44] add interruptenable class

---
 include/etiss/CPUArch.h          |  5 +++++
 include/etiss/CPUCore.h          |  4 ++++
 include/etiss/InterruptEnable.h  | 37 ++++++++++++++++++++++++++++++++
 include/etiss/InterruptHandler.h |  4 +++-
 src/CPUArch.cpp                  |  7 ++++++
 src/CPUCore.cpp                  |  1 +
 src/InterruptHandler.cpp         | 11 +++++++---
 7 files changed, 65 insertions(+), 4 deletions(-)
 create mode 100644 include/etiss/InterruptEnable.h

diff --git a/include/etiss/CPUArch.h b/include/etiss/CPUArch.h
index 9c76a7ab41..da5c98df73 100644
--- a/include/etiss/CPUArch.h
+++ b/include/etiss/CPUArch.h
@@ -62,6 +62,7 @@
 #include "etiss/Instruction.h"
 #include "etiss/IntegratedLibrary/gdb/GDBCore.h"
 #include "etiss/InterruptVector.h"
+#include "etiss/InterruptEnable.h"
 #include "etiss/Plugin.h"
 #include "etiss/VirtualStruct.h"
 #include "etiss/jit/CPU.h"
@@ -237,6 +238,10 @@ class CPUArch : public CPUArchRegListenerInterface,
             delete an allocated interrupt vector object
     */
     virtual void deleteInterruptVector(etiss::InterruptVector *vec, ETISS_CPU *cpu);
+
+    virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu);
+    virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu);
+
     /**
             returns arch dependent gdb functions. althought not required it is strongly recommended to implement this
     */
diff --git a/include/etiss/CPUCore.h b/include/etiss/CPUCore.h
index 78709d38b4..e0257eca8f 100644
--- a/include/etiss/CPUCore.h
+++ b/include/etiss/CPUCore.h
@@ -59,6 +59,7 @@
 #include "etiss/Translation.h"
 #include "etiss/System.h"
 #include "etiss/InterruptHandler.h"
+#include "etiss/InterruptEnable.h"
 #include "etiss/Plugin.h"
 #include "etiss/jit/ReturnCode.h"
 #include "etiss/mm/MMU.h"
@@ -186,6 +187,8 @@ class CPUCore : public VirtualStructSupport, public etiss::ToString
      */
     inline etiss::InterruptVector *getInterruptVector() { return intwrapper_; }
 
+    inline etiss::InterruptEnable *getInterruptEnable() { return intenable_; }
+
     /**
      * @brief Get the CPU architecture.
      *
@@ -381,6 +384,7 @@ class CPUCore : public VirtualStructSupport, public etiss::ToString
     std::shared_ptr<etiss::VirtualStruct> vcpu_;
     etiss::InterruptVector *intvector_;  /// cpu interrupt vector derived from cpu_ and allocated by arch_
     InterruptVectorWrapper *intwrapper_; /// wrapped interrupt vector to allow interrupt listening
+    etiss::InterruptEnable *intenable_;
     bool timer_enabled_; /// if true the a timer plugin allocated by arch_ will be added in CPUCore::execute
     std::shared_ptr<etiss::JIT>
         jit_;       /// JIT instance to use. may be 0 (etiss::getDefaultJIT() will be used in that case)
diff --git a/include/etiss/InterruptEnable.h b/include/etiss/InterruptEnable.h
new file mode 100644
index 0000000000..bcf4de3baf
--- /dev/null
+++ b/include/etiss/InterruptEnable.h
@@ -0,0 +1,37 @@
+#ifndef ETISS_INCLUDE_INTERRUPTENABLE_H_
+#define ETISS_INCLUDE_INTERRUPTENABLE_H_
+
+namespace etiss {
+
+class InterruptEnable
+{
+	public:
+		virtual ~InterruptEnable() {}
+		virtual bool isEnabled() { return true; }
+};
+
+template <typename t>
+class MappedInterruptEnable : public InterruptEnable
+{
+	public:
+		MappedInterruptEnable(t* enable_reg, t mask) :
+			enable_reg_(enable_reg),
+			mask_(mask)
+		{
+
+		}
+
+		virtual ~MappedInterruptEnable() {}
+
+		bool isEnabled() override
+		{
+			return *enable_reg_ & mask_;
+		};
+
+	private:
+		t* enable_reg_;
+		t mask_;
+};
+
+}
+#endif
\ No newline at end of file
diff --git a/include/etiss/InterruptHandler.h b/include/etiss/InterruptHandler.h
index 7a4ce4a0a4..eb7327b255 100644
--- a/include/etiss/InterruptHandler.h
+++ b/include/etiss/InterruptHandler.h
@@ -55,6 +55,7 @@
 
 #include "etiss/CPUArch.h"
 #include "etiss/InterruptVector.h"
+#include "etiss/InterruptHandler.h"
 #include "etiss/LibraryInterface.h"
 #include "etiss/Plugin.h"
 #include "etiss/jit/types.h"
@@ -84,7 +85,7 @@ enum InterruptType
 class InterruptHandler : public etiss::CoroutinePlugin
 {
   public:
-    InterruptHandler(etiss::InterruptVector *interruptVector, std::shared_ptr<etiss::CPUArch> arch,
+    InterruptHandler(etiss::InterruptVector *interruptVector, etiss::InterruptEnable *interruptEnable, std::shared_ptr<etiss::CPUArch> arch,
                      InterruptType itype = EDGE_TRIGGERED, bool sync = true);
     virtual ~InterruptHandler();
     /**
@@ -104,6 +105,7 @@ class InterruptHandler : public etiss::CoroutinePlugin
     std::mutex mu_;
     const bool sync_;
     InterruptVector *const vector_;
+    InterruptEnable *const enable_;
     /** list: (time , (line ,state) ) */
     std::list<std::pair<etiss::uint64, std::pair<unsigned, bool>>> pending_;
     const std::shared_ptr<etiss::CPUArch> cpuarch_;
diff --git a/src/CPUArch.cpp b/src/CPUArch.cpp
index 9bf3eae81e..0ded3222c3 100644
--- a/src/CPUArch.cpp
+++ b/src/CPUArch.cpp
@@ -135,6 +135,13 @@ void CPUArch::deleteInterruptVector(etiss::InterruptVector *vec, ETISS_CPU *cpu)
   // memory leak
 }
 
+etiss::InterruptEnable* CPUArch::createInterruptEnable(ETISS_CPU *cpu) {
+    return new etiss::InterruptEnable();
+}
+void CPUArch::deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu) {
+    delete en;
+}
+
 etiss::plugin::gdb::GDBCore &CPUArch::getGDBCore()
 { // disfunctional implementation
     return gdbcore_;
diff --git a/src/CPUCore.cpp b/src/CPUCore.cpp
index f13b2bc42c..0861e1cce5 100644
--- a/src/CPUCore.cpp
+++ b/src/CPUCore.cpp
@@ -142,6 +142,7 @@ CPUCore::CPUCore(std::shared_ptr<etiss::CPUArch> arch)
     , cpu_(arch->newCPU())
     , vcpu_(arch->getVirtualStruct(cpu_))
     , intvector_(arch->createInterruptVector(cpu_))
+    , intenable_(arch->createInterruptEnable(cpu_))
     , mmu_enabled_(false)
 {
     arch_->resetCPU(cpu_, 0);
diff --git a/src/InterruptHandler.cpp b/src/InterruptHandler.cpp
index e024d0fd52..c8e45ee58a 100644
--- a/src/InterruptHandler.cpp
+++ b/src/InterruptHandler.cpp
@@ -53,9 +53,9 @@
 
 using namespace etiss;
 
-InterruptHandler::InterruptHandler(etiss::InterruptVector *interruptVector, std::shared_ptr<CPUArch> arch,
+InterruptHandler::InterruptHandler(etiss::InterruptVector *interruptVector, etiss::InterruptEnable *interruptEnable, std::shared_ptr<CPUArch> arch,
                                    InterruptType itype, bool sync)
-    : itype_(itype), sync_(sync), vector_(interruptVector), cpuarch_(arch)
+    : itype_(itype), sync_(sync), vector_(interruptVector), enable_(interruptEnable), cpuarch_(arch)
 {
     empty_ = true;
 }
@@ -161,7 +161,12 @@ etiss::int32 InterruptHandler::execute()
     if (sync_)
         mu_.unlock();
 
-    return (mayinterrupt && vector_->isActive()) ? etiss::RETURNCODE::INTERRUPT : etiss::RETURNCODE::NOERROR;
+    auto active = vector_->isActive();
+    auto enabled = enable_->isEnabled();
+
+    // std::cout << "active: " << active << ", enabled: " << enabled << std::endl;
+
+    return (mayinterrupt && active && enabled) ? etiss::RETURNCODE::INTERRUPT : etiss::RETURNCODE::NOERROR;
 }
 
 std::string InterruptHandler::_getPluginName() const

From 62a2ffa38a58292756e8934ffe552d6e6025ec57 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 18:18:23 +0200
Subject: [PATCH 30/44] add interrupt handler plugin to bare_etiss

---
 src/bare_etiss_processor/main.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/bare_etiss_processor/main.cpp b/src/bare_etiss_processor/main.cpp
index ba60edf0f5..895abd6b67 100644
--- a/src/bare_etiss_processor/main.cpp
+++ b/src/bare_etiss_processor/main.cpp
@@ -121,6 +121,10 @@ int main(int argc, const char *argv[])
     std::cout << "=== Finished Setting up test system ===" << std::endl << std::endl;
 
     std::cout << "=== Setting up plug-ins ===" << std::endl;
+
+    auto irq_handler = std::make_shared<etiss::InterruptHandler>(cpu->getInterruptVector(), cpu->getInterruptEnable(), cpu->getArch(), etiss::LEVEL_TRIGGERED, false);
+    cpu->addPlugin(irq_handler);
+
     initializer.loadIniPlugins(cpu);
     initializer.loadIniJIT(cpu);
     // here own developped plug-ins can be added with:

From 62bbf617207aad51050b4ba6ffa486f84a50333c Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 18:18:57 +0200
Subject: [PATCH 31/44] add unloadblocksall method

---
 include/etiss/Translation.h |  2 ++
 src/Translation.cpp         | 25 +++++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/include/etiss/Translation.h b/include/etiss/Translation.h
index 4fb82aa4f8..502f1e1b1c 100644
--- a/include/etiss/Translation.h
+++ b/include/etiss/Translation.h
@@ -209,6 +209,8 @@ class Translation
 
     etiss::int32 translateBlock(CodeBlock &cb);
 
+    void unloadBlocksAll();
+
     void unloadBlocks(etiss::uint64 startindex = 0, etiss::uint64 endindex = ((etiss::uint64)((etiss::int64)-1)));
 
     std::string disasm(uint8_t *buf, unsigned len, int &append);
diff --git a/src/Translation.cpp b/src/Translation.cpp
index af2db7510f..9cea220f0a 100644
--- a/src/Translation.cpp
+++ b/src/Translation.cpp
@@ -586,8 +586,33 @@ etiss::int32 Translation::translateBlock(CodeBlock &cb)
     return etiss::RETURNCODE::NOERROR;
 }
 
+void Translation::unloadBlocksAll()
+{
+    for (auto &entry:blockmap_)
+    {
+        entry.second.erase(std::remove_if(entry.second.begin(), entry.second.end(),
+                            [](auto &bl)
+                            {
+                                bl->valid = false;
+                                BlockLink::updateRef(bl->next, 0);
+                                BlockLink::updateRef(bl->branch, 0);
+                                BlockLink::decrRef(bl); // remove reference of map
+                                return true;
+                            }),
+                            entry.second.end());
+    }
+    blockmap_.clear();
+}
+
 void Translation::unloadBlocks(etiss::uint64 startindex, etiss::uint64 endindex)
 {
+    // Hotfix: if everything needs to be deleted, new function unloadBlocksAll()
+    if (startindex == 0 && endindex == ((etiss::uint64)((etiss::int64)-1)))
+    {
+        unloadBlocksAll();
+        return;
+    }
+
     const etiss::uint64 startindexblock = startindex >> 9;
     const etiss::uint64 endindexblock = (endindex >> 9) + ((((endindex >> 9) << 9) == endindex) ? 0 : 1);
     for (etiss::uint64 block = startindexblock; block < endindexblock; block++)

From 8b7f87c76f370cacd4c8fbaf1a4d55a9d8156548 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 18:19:15 +0200
Subject: [PATCH 32/44] add icache flush method

---
 src/CPUArch.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/CPUArch.cpp b/src/CPUArch.cpp
index 0ded3222c3..b6761149da 100644
--- a/src/CPUArch.cpp
+++ b/src/CPUArch.cpp
@@ -197,4 +197,9 @@ extern "C"
     {
         CPUArch::signalChangedRegisterValue(cpu, registerName);
     }
+
+    void etiss_icache_flush(ETISS_CPU *cpu, ETISS_System * const system, void * const * const plugin_pointers)
+    {
+        cpu->exception = etiss::RETURNCODE::RELOADBLOCKS;
+    }
 }

From 5dc331f81fd1b04f8bdfa07ba193d1ab5819b555 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 19:05:38 +0200
Subject: [PATCH 33/44] generate error handling pseudo instruction

---
 src/Translation.cpp | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/src/Translation.cpp b/src/Translation.cpp
index 9cea220f0a..686bc55386 100644
--- a/src/Translation.cpp
+++ b/src/Translation.cpp
@@ -332,9 +332,37 @@ BlockLink *Translation::getBlock(BlockLink *prev, const etiss::uint64 &instructi
     block.functionglobalCode().push_back("if (cpu->mode != " + toString(cpu_.mode) +
                                       ") return ETISS_RETURNCODE_RELOADCURRENTBLOCK;");
 
+    etiss::int32 transerror = translateBlock(block);
+
+    etiss::instr::InstructionContext err_ctx;
+    etiss::CodeSet err_cs;
+    auto vis = mis_->get(cpu_.mode);
+
+    err_ctx.cf_delay_slot_ = 0;
+    err_ctx.force_block_end_ = false;
+    err_ctx.force_append_next_instr_ = false;
+    err_ctx.force_block_end_ = false;
+    err_ctx.current_address_ = block.endaddress_;
+    err_ctx.current_local_address_ = block.endaddress_ - block.startindex_;
+    err_ctx.instr_width_fully_evaluated_ = true;
+    err_ctx.is_not_default_width_ = false;
+    err_ctx.instr_width_ = vis->width_;
+
+    auto err_ins = &vis->getMain()->getInvalid();
+
+    etiss::instr::BitArray errba(32, 0);
+    errba = etiss::RETURNCODE::ILLEGALINSTRUCTION;
+
+    err_ins->translate(errba, err_cs, err_ctx);
+
+    etiss::RegisterSet dummy;
+    bool err_ok;
+
+    auto err_str = "if (cpu->exception) {\n" + err_cs.toString(dummy, err_ok) + "\n}\n\n";
+
     plugins_initCodeBlock_(plugins_array_, block);
 
-    etiss::int32 transerror = translateBlock(block);
+    block.functionglobalCode().insert(block.functionglobalCode().begin(), err_str);
 
     if (transerror != ETISS_RETURNCODE_NOERROR)
     {

From 7a553ef86d5abc8bc5dd162bf310da69377f432f Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 19:06:35 +0200
Subject: [PATCH 34/44] update architectures

---
 ArchImpl/RV32IMACFD/CMakeLists.txt            |   7 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp        |  10 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArch.h          |   3 +
 .../RV32IMACFD/RV32IMACFDArchSpecificImp.cpp  |  38 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         | 544 +++++++----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp | 344 ++++---
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     |  82 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp | 362 ++++---
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     |  90 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp | 528 +++++++---
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 452 +++++----
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 920 ++++++++++--------
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp | 258 +++--
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |   6 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    | 152 +--
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    | 198 +++-
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |  64 +-
 .../RV32IMACFD_tum_semihostingInstr.cpp       |  96 +-
 ArchImpl/RV64IMACFD/CMakeLists.txt            |   7 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp        |  10 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArch.h          |   4 +-
 .../RV64IMACFD/RV64IMACFDArchSpecificImp.cpp  |  46 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h         | 546 +++++++----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp | 344 ++++---
 .../RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp     |  82 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp | 362 ++++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp | 528 +++++++---
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     | 440 ++++++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp | 920 ++++++++++--------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp | 258 +++--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp | 344 ++++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp |  70 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp |  70 +-
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     | 190 ++--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp | 326 ++++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp | 184 ++--
 .../RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp   |   6 +-
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    | 152 +--
 .../RV64IMACFD/RV64IMACFD_tum_retInstr.cpp    | 198 +++-
 .../RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp  |  64 +-
 .../RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp    |  64 +-
 .../RV64IMACFD_tum_semihostingInstr.cpp       |  96 +-
 .../RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp | 118 +++
 43 files changed, 6213 insertions(+), 3370 deletions(-)
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp

diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index 37e82eaa83..81bb6cd154 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,9 +1,12 @@
-# Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+# Generated on Tue, 19 Sep 2023 16:07:36 +0200.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
 PROJECT(RV32IMACFD)
 
+SET(CMAKE_BUILD_WITH_INSTALL_RPATH TRUE)
+SET(CMAKE_INSTALL_RPATH "\$ORIGIN/../../include/jit/etiss/jit")
+
 ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFDArch.cpp
 	RV32IMACFDArchLib.cpp
@@ -17,8 +20,8 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFD_RV32DInstr.cpp
 	RV32IMACFD_RV32DCInstr.cpp
 	RV32IMACFD_ZifenceiInstr.cpp
-	RV32IMACFD_tum_retInstr.cpp
 	RV32IMACFD_tum_csrInstr.cpp
+	RV32IMACFD_tum_retInstr.cpp
 	RV32IMACFD_RV32AInstr.cpp
 	RV32IMACFD_tum_rvaInstr.cpp
 	RV32IMACFD_tum_semihostingInstr.cpp
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
index fc3a70a5b1..23d75ee4d5 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -206,11 +206,11 @@ const std::set<std::string> & RV32IMACFDArch::getHeaders() const
 
 void RV32IMACFDArch::initCodeBlock(etiss::CodeBlock & cb) const
 {
-	cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFD.h\"\n");
-	cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFDFuncs.h\"\n");
-	cb.functionglobalCode().insert("cpu->exception = 0;\n");
-	cb.functionglobalCode().insert("cpu->return_pending = 0;\n");
-	cb.functionglobalCode().insert("etiss_uint32 mem_ret_code = 0;\n");
+	cb.fileglobalCode().push_back("#include \"Arch/RV32IMACFD/RV32IMACFD.h\"\n");
+	cb.fileglobalCode().push_back("#include \"Arch/RV32IMACFD/RV32IMACFDFuncs.h\"\n");
+	cb.functionglobalCode().push_back("cpu->exception = 0;\n");
+	cb.functionglobalCode().push_back("cpu->return_pending = 0;\n");
+	cb.functionglobalCode().push_back("etiss_uint32 mem_ret_code = 0;\n");
 }
 
 etiss::plugin::gdb::GDBCore & RV32IMACFDArch::getGDBCore()
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
index 0e6600425e..7a772400d4 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
@@ -10,6 +10,7 @@
 #include "etiss/CPUArch.h"
 #include "etiss/Instruction.h"
 #include "etiss/InterruptVector.h"
+#include "etiss/InterruptEnable.h"
 #include "RV32IMACFD.h"
 #include "RV32IMACFDGDBCore.h"
 
@@ -89,6 +90,8 @@ class RV32IMACFDArch : public etiss::CPUArch {
 	*/
 	virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU * cpu);
 	virtual void deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu);
+    virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu);
+    virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu);
 
 	/**
 		@brief get the GDBcore for RV32IMACFD architecture
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
index 28ba8d34c0..79518de26b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -13,6 +13,11 @@
 #include "RV32IMACFDArch.h"
 #include "RV32IMACFDArchSpecificImp.h"
 
+#define ETISS_ARCH_STATIC_FN_ONLY
+extern "C" {
+#include "RV32IMACFDFuncs.h"
+}
+
 /**
 	@brief This function will be called automatically in order to handling exceptions such as interrupt, system call, illegal instructions
 
@@ -29,8 +34,10 @@
 */
 etiss::int32 RV32IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu)
 {
-    etiss::log(etiss::WARNING, "in old exception handler");
-    return cause;
+    translate_exc_code(cpu, nullptr, nullptr, cause);
+	cpu->instructionPointer = cpu->nextPc;
+
+	return 0;
 }
 
 /**
@@ -117,8 +124,12 @@ error_code += R_error_code_0.read(ba) << 0;
 		cp.code() = std::string("//trap_entry 32\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, (cpu->exception) ? (cpu->exception) : (" + std::to_string(error_code) + "ULL));\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -160,8 +171,12 @@ error_code += R_error_code_0.read(ba) << 0;
 		cp.code() = std::string("//trap_entry 16\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, (cpu->exception) ? (cpu->exception) : (" + std::to_string(error_code) + "ULL));\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -342,6 +357,11 @@ etiss::InterruptVector * RV32IMACFDArch::createInterruptVector(ETISS_CPU * cpu)
 	std::vector<etiss::uint32 *> vec;
 	std::vector<etiss::uint32 *> mask;
 
+	RV32IMACFD* rvcpu = (RV32IMACFD*)cpu;
+
+	vec.push_back(rvcpu->CSR[0x344]);
+	mask.push_back(rvcpu->CSR[0x304]);
+
 	return new etiss::MappedInterruptVector<etiss::uint32>(vec, mask);
 }
 
@@ -349,3 +369,13 @@ void RV32IMACFDArch::deleteInterruptVector(etiss::InterruptVector * vec, ETISS_C
 {
 	delete vec;
 }
+
+etiss::InterruptEnable* RV32IMACFDArch::createInterruptEnable(ETISS_CPU* cpu) {
+	RV32IMACFD* rvcpu = (RV32IMACFD*)cpu;
+
+	return new etiss::MappedInterruptEnable<etiss::uint32>(rvcpu->CSR[0x300], 0xf);
+}
+
+void RV32IMACFDArch::deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu) {
+	delete en;
+}
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index bf44157a74..6606c8bfa3 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Fri, 29 Sep 2023 16:41:15 +0200.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -16,305 +16,429 @@
 
 
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern void leave(etiss_int32 priv_lvl);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern void wait(etiss_int32 flag);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
-{
-return (*((RV32IMACFD*)cpu)->CSR[769] >> (extension - 65U)) & 1U;
-}
-#endif
+static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 unbox_s(etiss_uint64);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fclass_s(etiss_uint32);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fget_flags();
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 unbox_d(etiss_uint64);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fclass_d(etiss_uint64);
-#endif
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
-{
-return (reg & mask) / (mask & ~((mask << 1UL)));
-}
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
-{
-return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1UL)))) & mask));
-}
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
-{
-cpu->return_pending = 1;
-etiss_uint32 epc = cpu->instructionPointer;
-if (((RV32IMACFD*)cpu)->PRIV <= 1 && (*((RV32IMACFD*)cpu)->CSR[770] >> mcause) & 1U) {
-cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[261] & -2);
-*((RV32IMACFD*)cpu)->CSR[321] = epc;
-*((RV32IMACFD*)cpu)->CSR[322] = mcause;
-etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[256];
-s = set_field(s, 32, get_field(s, 2));
-s = set_field(s, 256, ((RV32IMACFD*)cpu)->PRIV);
-s = set_field(s, 2, 0U);
-*((RV32IMACFD*)cpu)->CSR[256] = s;
-((RV32IMACFD*)cpu)->PRIV = (1) & 0x7;
-}
-else {
-cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773] & -2);
-*((RV32IMACFD*)cpu)->CSR[833] = epc;
-*((RV32IMACFD*)cpu)->CSR[834] = mcause;
-etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[768];
-s = set_field(s, 128, get_field(s, 8));
-s = set_field(s, 6144, ((RV32IMACFD*)cpu)->PRIV);
-s = set_field(s, 8, 0U);
-*((RV32IMACFD*)cpu)->CSR[768] = s;
-((RV32IMACFD*)cpu)->PRIV = (3) & 0x7;
-}
-}
-#endif
-
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
-{
-etiss_int32 code = 0U;
-if (cause == -2147483648) {
-return;
-}
- else if (cause == -5) {
-code = 5;
-}
- else if (cause == -14) {
-code = 13;
-}
- else if (cause == -6) {
-code = 7;
-}
- else if (cause == -15) {
-code = 15;
-}
- else if (cause == -7) {
-code = 1;
-}
-else {
-code = 2;
-}
-cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
-}
-#endif
+extern etiss_int32 ETISS_SIGNAL_MMU(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 mmu_signal_);
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 etiss_get_time();
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint32 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+static inline etiss_uint32 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+
+static inline etiss_uint32 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+
+static inline etiss_uint32 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
+
+static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val);
+
+extern void etiss_icache_flush(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+
+static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask);
+
+static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
+
+static inline etiss_uint8 ctz(etiss_uint64 val);
+
+static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause);
+
+static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
+
+static inline etiss_uint32 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+
+static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+
+extern etiss_uint8 etiss_semihost_enabled();
+
+extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
+
+static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
 {
-etiss_uint32 mask = 0U;
-if (extension_enabled(cpu, system, plugin_pointers, 83U)) {
-mask = mask | 5767458U;
-if (extension_enabled(cpu, system, plugin_pointers, 86U)) {
-mask = mask | 1536;
-}
-if (extension_enabled(cpu, system, plugin_pointers, 70U)) {
-mask = mask | 24576;
-}
-if (extension_enabled(cpu, system, plugin_pointers, 88U)) {
-mask = mask | 98304;
-}
-if (1U && get_field(*((RV32IMACFD*)cpu)->CSR[384], 2147483648U) || 0U && get_field(*((RV32IMACFD*)cpu)->CSR[384], 17293822569102704640UL)) {
-mask = mask | 262144;
-}
+{ // block
+return (*((RV32IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
+} // block
 }
+
+static inline etiss_uint32 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 mask = 0ULL;
+if (extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
+{ // block
+mask = mask | 5767458ULL;
+if (extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
+mask = mask | 1536LL;
+} // conditional
+if (extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
+mask = mask | 24576LL;
+} // conditional
+if (extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
+mask = mask | 98304LL;
+} // conditional
+if ((get_field(*((RV32IMACFD*)cpu)->CSR[384LL], 2147483648ULL))) { // conditional
+mask = mask | 262144LL;
+} // conditional
+} // block
+} // conditional
 return mask;
+} // block
 }
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint32 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
 {
-etiss_uint32 mask = 6280U;
+{ // block
+etiss_uint32 mask = 6280ULL;
 return mask | sstatus_mask(cpu, system, plugin_pointers);
+} // block
 }
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint32 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
 {
-if (csr == 1) {
-return *((RV32IMACFD*)cpu)->CSR[3] & 31U;
-}
-if (csr == 2) {
-return (*((RV32IMACFD*)cpu)->CSR[3] >> 5U) & 7U;
-}
-if (csr == 3072) {
+{ // block
+if (csr == 1LL) { // conditional
+return *((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL;
+} // conditional
+if (csr == 2LL) { // conditional
+return (*((RV32IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
+} // conditional
+if (csr == 3072LL) { // conditional
 return etiss_get_cycles(cpu, system, plugin_pointers);
-}
-if (csr == 3200) {
-return etiss_get_cycles(cpu, system, plugin_pointers) >> 32U;
-}
-if (csr == 3073) {
+} // conditional
+if (csr == 3200LL) { // conditional
+return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 3073LL) { // conditional
 return etiss_get_time();
-}
-if (csr == 3201) {
-return etiss_get_time() >> 32U;
-}
-if (csr == 3074) {
+} // conditional
+if (csr == 3201LL) { // conditional
+return etiss_get_time() >> 32ULL;
+} // conditional
+if (csr == 3074LL) { // conditional
 return etiss_get_instret(cpu, system, plugin_pointers);
-}
-if (csr == 3202) {
-return etiss_get_instret(cpu, system, plugin_pointers) >> 32U;
-}
-if (csr == 768 || csr == 256) {
-return *((RV32IMACFD*)cpu)->CSR[768] | 8589934592UL | 34359738368UL;
-}
-if (csr == 769) {
-return (((1U) << 30) | ((((*((RV32IMACFD*)cpu)->CSR[769]) >> (0U)) & 1073741823)));
-}
+} // conditional
+if (csr == 3202LL) { // conditional
+return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 768LL || csr == 256LL) { // conditional
+return *((RV32IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
+} // conditional
+if (csr == 769LL) { // conditional
+return (((1ULL) << 30) | ((((*((RV32IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 1073741823)));
+} // conditional
 return *((RV32IMACFD*)cpu)->CSR[csr];
+} // block
 }
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
 {
-if (csr == 1) {
-*((RV32IMACFD*)cpu)->CSR[3] = (*((RV32IMACFD*)cpu)->CSR[3] & 224U) | (val & 31U);
-}
- else if (csr == 2) {
-*((RV32IMACFD*)cpu)->CSR[3] = ((val & 7U) << 5U) | (*((RV32IMACFD*)cpu)->CSR[3] & 31U);
-}
- else if (csr == 3) {
-*((RV32IMACFD*)cpu)->CSR[3] = val & 255U;
-}
- else if (csr == 768) {
-*((RV32IMACFD*)cpu)->CSR[768] = val & mstatus_mask(cpu, system, plugin_pointers);
+{ // block
+if (csr == 1LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[3LL] = (*((RV32IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
+} // conditional
+ else if (csr == 2LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL);
+} // conditional
+ else if (csr == 3LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
+} // conditional
+ else if (csr == 768LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[768LL] = val & mstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr == 256LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[768LL] = val & sstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr != 769LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[csr] = val;
+} // conditional
+if (csr == 384LL) { // conditional
+ETISS_SIGNAL_MMU(cpu, system, plugin_pointers, val);
+} // conditional
+} // block
 }
- else if (csr == 256) {
-*((RV32IMACFD*)cpu)->CSR[768] = val & sstatus_mask(cpu, system, plugin_pointers);
+
+static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
+{
+{ // block
+return (reg & mask) / (mask & ~((mask << 1ULL)));
+} // block
 }
- else if (csr != 769) {
-*((RV32IMACFD*)cpu)->CSR[csr] = val;
+
+static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
+{
+{ // block
+return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
+} // block
 }
+
+static inline etiss_uint8 ctz(etiss_uint64 val)
+{
+{ // block
+if (!(val)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint8 res = 0ULL;
+if ((val << 32ULL) == 0ULL) { // conditional
+{ // block
+res = res + 32ULL;
+val = val >> 32ULL;
+} // block
+} // conditional
+if ((val << 48ULL) == 0ULL) { // conditional
+{ // block
+res = res + 16ULL;
+val = val >> 16ULL;
+} // block
+} // conditional
+if ((val << 56ULL) == 0ULL) { // conditional
+{ // block
+res = res + 8ULL;
+val = val >> 8ULL;
+} // block
+} // conditional
+if ((val << 60ULL) == 0ULL) { // conditional
+{ // block
+res = res + 4ULL;
+val = val >> 4ULL;
+} // block
+} // conditional
+if ((val << 62ULL) == 0ULL) { // conditional
+{ // block
+res = res + 2ULL;
+val = val >> 2ULL;
+} // block
+} // conditional
+if ((val << 63ULL) == 0ULL) { // conditional
+{ // block
+res = res + 1ULL;
+val = val >> 1ULL;
+} // block
+} // conditional
+return res;
+} // block
+}
+
+static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause)
+{
+cpu->return_pending = 1;
+cpu->exception = 0;
+{ // block
+etiss_uint32 epc = cpu->instructionPointer;
+etiss_uint32 deleg = 0ULL;
+etiss_uint32 vector = 0ULL;
+etiss_uint32 bit = mcause;
+etiss_int32 irq2 = (mcause & 2147483648ULL) != 0ULL;
+if (irq2) { // conditional
+{ // block
+deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[771LL]) : (0ULL);
+bit = bit & -2147483649LL;
+} // block
+} // conditional
+else { // conditional
+{ // block
+deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[770LL]) : (0ULL);
+} // block
+} // conditional
+if (((RV32IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
+{ // block
+vector = ((*((RV32IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
+*((RV32IMACFD*)cpu)->CSR[321LL] = epc;
+*((RV32IMACFD*)cpu)->CSR[322LL] = mcause;
+etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 256LL);
+s = set_field(s, 32LL, get_field(s, 2LL));
+s = set_field(s, 256LL, ((RV32IMACFD*)cpu)->PRIV);
+s = set_field(s, 2LL, 0ULL);
+csr_write(cpu, system, plugin_pointers, 256LL, s);
+((RV32IMACFD*)cpu)->PRIV = (1LL) & 0x7;
+} // block
+} // conditional
+else { // conditional
+{ // block
+vector = ((*((RV32IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
+*((RV32IMACFD*)cpu)->CSR[833LL] = epc;
+*((RV32IMACFD*)cpu)->CSR[834LL] = mcause;
+etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 768LL);
+s = set_field(s, 128LL, get_field(s, 8LL));
+s = set_field(s, 6144LL, ((RV32IMACFD*)cpu)->PRIV);
+s = set_field(s, 8LL, 0ULL);
+csr_write(cpu, system, plugin_pointers, 768LL, s);
+((RV32IMACFD*)cpu)->PRIV = (3LL) & 0x7;
+} // block
+} // conditional
+} // block
 }
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-extern etiss_uint8 etiss_semihost_enabled();
-#endif
+static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
+{
+{ // block
+etiss_uint32 code = 0ULL;
+if (cause == -2147483648LL) { // conditional
+return;
+} // conditional
+ else if (cause == -5LL) { // conditional
+code = 5LL;
+} // conditional
+ else if (cause == -13LL) { // conditional
+code = 12LL;
+} // conditional
+ else if (cause == -14LL) { // conditional
+code = 13LL;
+} // conditional
+ else if (cause == -6LL) { // conditional
+code = 7LL;
+} // conditional
+ else if (cause == -15LL) { // conditional
+code = 15LL;
+} // conditional
+ else if (cause == -7LL) { // conditional
+code = 1LL;
+} // conditional
+ else if (cause == -9LL) { // conditional
+{ // block
+code = calc_irq_mcause(cpu, system, plugin_pointers);
+if (!(code)) { // conditional
+return;
+} // conditional
+} // block
+} // conditional
+else { // conditional
+code = 2LL;
+} // conditional
+raise(cpu, system, plugin_pointers, 0ULL, code);
+} // block
+}
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
-#endif
+static inline etiss_uint32 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 pending_interrupts = *((RV32IMACFD*)cpu)->CSR[772LL] & *((RV32IMACFD*)cpu)->CSR[836LL];
+if (!(pending_interrupts)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint32 mie = get_field(*((RV32IMACFD*)cpu)->CSR[768LL], 8LL);
+etiss_uint32 m_enabled = ((RV32IMACFD*)cpu)->PRIV < 3LL || (((RV32IMACFD*)cpu)->PRIV == 3LL && mie);
+etiss_uint32 enabled_interrupts = pending_interrupts & ~(*((RV32IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
+if (enabled_interrupts == 0ULL) { // conditional
+{ // block
+etiss_uint32 deleg = *((RV32IMACFD*)cpu)->CSR[771LL];
+etiss_uint32 sie = get_field(csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
+etiss_uint32 s_enabled = ((RV32IMACFD*)cpu)->PRIV < 1LL || (((RV32IMACFD*)cpu)->PRIV == 1LL && sie);
+enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
+} // block
+} // conditional
+if (enabled_interrupts) { // conditional
+{ // block
+if (enabled_interrupts >> 12ULL) { // conditional
+enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
+} // conditional
+ else if (enabled_interrupts & 2048LL) { // conditional
+enabled_interrupts = 2048LL;
+} // conditional
+ else if (enabled_interrupts & 8LL) { // conditional
+enabled_interrupts = 8LL;
+} // conditional
+ else if (enabled_interrupts & 128LL) { // conditional
+enabled_interrupts = 128LL;
+} // conditional
+ else if (enabled_interrupts & 512LL) { // conditional
+enabled_interrupts = 512LL;
+} // conditional
+ else if (enabled_interrupts & 2LL) { // conditional
+enabled_interrupts = 2LL;
+} // conditional
+ else if (enabled_interrupts & 32LL) { // conditional
+enabled_interrupts = 32LL;
+} // conditional
+ else if (enabled_interrupts & 8192LL) { // conditional
+enabled_interrupts = 8192LL;
+} // conditional
+ else if (enabled_interrupts & 1024LL) { // conditional
+enabled_interrupts = 1024LL;
+} // conditional
+ else if (enabled_interrupts & 4LL) { // conditional
+enabled_interrupts = 4LL;
+} // conditional
+ else if (enabled_interrupts & 64LL) { // conditional
+enabled_interrupts = 64LL;
+} // conditional
+else { // conditional
+return 0ULL;
+} // conditional
+return 2147483648ULL | ctz(enabled_interrupts);
+} // block
+} // conditional
+return 0ULL;
+} // block
+}
+
+static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 irq_mcause = calc_irq_mcause(cpu, system, plugin_pointers);
+if (irq_mcause) { // conditional
+raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
+} // conditional
+} // block
+}
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index 454ee0ee1c..ff1f96b480 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:47:58 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -52,30 +52,42 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOSWAPW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-if ((rd % 32U) != 0U) {
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n";
+} // conditional
 cp.code() += "etiss_uint32 mem_val_1;\n";
-cp.code() += "mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -158,32 +170,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOADDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -266,32 +290,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOXORW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -374,32 +410,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOANDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -482,32 +530,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOORW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -590,32 +650,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMINW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -698,32 +770,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -806,32 +890,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMINUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res1);\n";
-}
-cp.code() += "etiss_uint32 res2 = (res1 > *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res1);\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = (res1 > (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -914,32 +1010,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res1);\n";
-}
-cp.code() += "etiss_uint32 res2 = (res1 < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res1);\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = (res1 < (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index d57e301789..77b997805d 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -48,20 +48,28 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFLD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -136,19 +144,27 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFSD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -222,20 +238,28 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CFLDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -306,19 +330,27 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFSDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index 6183c2b464..91f090175f 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -46,20 +46,28 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//FLD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -132,19 +140,27 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//FSD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -223,11 +239,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -304,11 +324,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -385,11 +409,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -466,11 +494,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -544,11 +576,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -619,11 +655,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -694,11 +734,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMUL_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -769,11 +813,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FDIV_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -841,11 +889,15 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FSQRT_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -910,9 +962,13 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJ_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -977,9 +1033,13 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJN_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1044,9 +1104,13 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJX_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) & 9223372036854775808UL);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) & 9223372036854775808ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1111,11 +1175,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMIN_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 0U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 0ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1180,11 +1248,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMAX_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 1U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 1ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1249,9 +1321,13 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L + res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL + res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1316,9 +1392,17 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), " + std::to_string(rm) + "ULL);\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1383,18 +1467,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FEQ_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = 0U;\n";
-cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 0U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = 0ULL;\n";
+cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 0ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1456,18 +1544,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLT_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = 0U;\n";
-cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 2U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = 0ULL;\n";
+cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 2ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1529,18 +1621,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLE_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = 0U;\n";
-cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 1U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = 0ULL;\n";
+cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 1ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1599,12 +1695,16 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCLASS_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1663,18 +1763,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_W_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_int32 res = 0U;\n";
-cp.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 0U, " + std::to_string(rm) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int32 res = 0ULL;\n";
+cp.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 0ULL, " + std::to_string(rm) + "ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1736,18 +1840,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_WU_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 1U, " + std::to_string(rm) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+cp.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 1ULL, " + std::to_string(rm) + "ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1809,13 +1917,17 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1877,13 +1989,17 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_WU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 44000aadb1..b9802a9911 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -50,20 +50,32 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = -4294967296L | res;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = -4294967296LL | res;\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -142,19 +154,27 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFSW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -230,20 +250,32 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CFLWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | res;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | res;\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -314,19 +346,27 @@ uimm += R_uimm_2.read(ba) << 2;
 		cp.code() = std::string("//CFSWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 32);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index c5a54002d2..542e310267 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -46,20 +46,32 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//FLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -132,19 +144,27 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//FSW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -223,11 +243,19 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -304,11 +332,19 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -385,14 +421,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -469,14 +513,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -550,13 +602,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -627,13 +687,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -704,13 +772,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMUL_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -781,13 +857,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FDIV_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -855,12 +939,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FSQRT_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -925,11 +1017,19 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJ_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = ((((((frs2) >> (31ULL)) & 1)) << 31) | ((((frs1) >> (0ULL)) & 2147483647)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -994,11 +1094,19 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJN_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31ULL)) & 1))) << 31) | ((((frs1) >> (0ULL)) & 2147483647)));\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1063,11 +1171,19 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJX_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1132,13 +1248,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMIN_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1203,13 +1327,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMAX_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1274,19 +1406,27 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_W_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_int32 res = 0U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int32 res = 0ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "res = fcvt_s(frs1, 0ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "} // block\n";
+} // block
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1348,19 +1488,27 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_WU_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)((etiss_int32)(res));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "res = fcvt_s(frs1, 1ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "} // block\n";
+} // block
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((etiss_int32)(res));\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1422,20 +1570,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FEQ_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "res = fcmp_s(frs1, frs2, 0U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 0ULL);\n";
+cp.code() += "} // block\n";
+} // block
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1497,20 +1653,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLT_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "res = fcmp_s(frs1, frs2, 2U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 2ULL);\n";
+cp.code() += "} // block\n";
+} // block
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1572,20 +1736,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLE_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "res = fcmp_s(frs1, frs2, 1U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 1ULL);\n";
+cp.code() += "} // block\n";
+} // block
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32) | (flags & 31U);\n";
+cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1644,16 +1816,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCLASS_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+cp.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1712,13 +1888,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1780,13 +1964,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_WU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1845,14 +2037,18 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_X_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1908,12 +2104,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_W_X\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index df71ae9ed8..51d9fdf35f 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -49,19 +49,23 @@ imm += R_imm_4.read(ba) << 4;
 		cp.code() = std::string("//CADDI4SPN\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if (imm) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + "U;\n";
-}
-else {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if (imm) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(imm) + "ULL;\n";
+} // conditional
+else { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -139,20 +143,28 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int32)(mem_val_0);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -231,20 +243,28 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CSW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -318,15 +338,15 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CADDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if ((rs1 % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if ((rs1 % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -383,7 +403,11 @@ nzimm += R_nzimm_5.read(ba) << 5;
 		cp.code() = std::string("//CNOP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -452,13 +476,17 @@ imm += R_imm_11.read(ba) << 11;
 		cp.code() = std::string("//CJAL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[1U], 32);
+		cp.getAffectedRegisters().add(reg_name[1ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -536,14 +564,18 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -603,18 +635,26 @@ imm += R_imm_17.read(ba) << 17;
 		cp.code() = std::string("//CLUI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if (imm == 0U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm == 0ULL) { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int32)(((etiss_int32)imm) << (14)) >> (14))) + "LL;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -686,19 +726,23 @@ nzimm += R_nzimm_9.read(ba) << 9;
 		cp.code() = std::string("//CADDI16SP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if (nzimm) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[2U] = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
-}
-else {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if (nzimm) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[2ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)nzimm) << (6)) >> (6))) + "LL;\n";
+} // conditional
+else { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 32);
-		cp.getAffectedRegisters().add(reg_name[2U], 32);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[2ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -765,9 +809,13 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//__reserved_clui\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -832,13 +880,17 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -894,15 +946,23 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if (shamt) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if (shamt) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -960,13 +1020,17 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CANDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] & " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1024,14 +1088,18 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CSUB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1087,14 +1155,18 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CXOR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1150,14 +1222,18 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//COR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1213,14 +1289,18 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CAND\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1287,8 +1367,8 @@ imm += R_imm_11.read(ba) << 11;
 		cp.code() = std::string("//CJ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1375,14 +1455,14 @@ imm += R_imm_8.read(ba) << 8;
 		cp.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] == 0U) {\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
-cp.code() += "}\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] == 0ULL) { // conditional\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
+cp.code() += "} // conditional\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1391,7 +1471,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -1463,14 +1543,14 @@ imm += R_imm_8.read(ba) << 8;
 		cp.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] != 0U) {\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
-cp.code() += "}\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] != 0ULL) { // conditional\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
+cp.code() += "} // conditional\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1479,7 +1559,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -1543,15 +1623,15 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if (nzuimm) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(nzuimm) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if (nzuimm) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(nzuimm) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1611,25 +1691,41 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CLWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if (rd % 32U) {
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if (rd % 32ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res = mem_val_0;\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res);\n";
-}
-else {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1698,15 +1794,15 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CMV\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1759,18 +1855,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CJR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if (rs1) {
-cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & -2;\n";
-}
-else {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if (rs1) { // conditional
+cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & -2LL;\n";
+} // conditional
+else { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1826,9 +1926,13 @@ static InstructionDefinition __reserved_cmv_ (
 		cp.code() = std::string("//__reserved_cmv\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1890,16 +1994,16 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CADD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rd % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1952,15 +2056,19 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CJALR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "cpu->nextPc = new_pc & -2;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[1U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[1ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -2016,9 +2124,13 @@ static InstructionDefinition cebreak_ (
 		cp.code() = std::string("//CEBREAK\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -2082,20 +2194,28 @@ uimm += R_uimm_2.read(ba) << 2;
 		cp.code() = std::string("//CSWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -2156,9 +2276,13 @@ static InstructionDefinition dii_ (
 		cp.code() = std::string("//DII\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2U) + "U;\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index f6f5706f10..001772bc09 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Mon, 25 Sep 2023 14:27:10 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -43,14 +43,14 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//LUI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string((etiss_uint32)(((etiss_int32)(imm)))) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string((etiss_uint32)(((etiss_int32)(imm)))) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -106,14 +106,14 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//AUIPC\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + "LL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -175,21 +175,37 @@ imm += R_imm_20.read(ba) << 20;
 		cp.code() = std::string("//JAL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-}
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+} // conditional
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)(((etiss_int32)imm) << (11)) >> (11))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -263,23 +279,39 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//JALR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
-cp.code() += "if (new_pc % 2U) {\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL) & -2LL;\n";
+cp.code() += "if (new_pc % 2ULL) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-}
-cp.code() += "cpu->nextPc = new_pc & -2;\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+} // conditional
+cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -356,21 +388,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -379,7 +431,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -453,21 +505,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -476,7 +548,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -550,21 +622,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -573,7 +665,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -647,21 +739,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -670,7 +782,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -744,21 +856,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -767,7 +899,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -841,21 +973,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -864,7 +1016,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -932,23 +1084,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint8 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1019,23 +1179,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint16 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1106,23 +1274,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1193,23 +1369,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LBU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint8 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1280,23 +1464,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LHU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint16 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1369,20 +1561,28 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint8 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1457,20 +1657,28 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint16 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1545,20 +1753,28 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1631,15 +1847,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ADDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1701,15 +1917,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//SLTI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL)) ? (1ULL) : (0ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1771,15 +1987,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//SLTIU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U)) ? (1U) : (0U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL)) ? (1ULL) : (0ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1841,15 +2057,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//XORI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1911,15 +2127,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ORI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1981,15 +2197,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ANDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2051,15 +2267,15 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2121,15 +2337,15 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2191,15 +2407,15 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> " + std::to_string(shamt) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2261,16 +2477,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//ADD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2332,16 +2548,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SUB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2403,16 +2619,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2474,16 +2690,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLT\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (1U) : (0U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (1ULL) : (0ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2545,16 +2761,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLTU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (1U) : (0U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (1ULL) : (0ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2616,16 +2832,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//XOR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2687,16 +2903,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2758,16 +2974,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRA\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 31U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2829,16 +3045,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//OR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2900,16 +3116,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//AND\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2977,8 +3193,8 @@ fm += R_fm_0.read(ba) << 0;
 		cp.code() = std::string("//FENCE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "((RV32IMACFD*)cpu)->FENCE[0U] = " + std::to_string(pred << 4U | succ) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+cp.code() += "((RV32IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -3016,109 +3232,3 @@ ss << "fence" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std:
 		return ss.str();
 	}
 );
-
-// ECALL -----------------------------------------------------------------------
-static InstructionDefinition ecall_ (
-	ISA32_RV32IMACFD,
-	"ecall",
-	(uint32_t) 0x000073,
-	(uint32_t) 0xffffffff,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//ECALL\n");
-
-// -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
-cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-	{
-		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
-
-		cp.code() = std::string("//ECALL\n");
-
-// -----------------------------------------------------------------------------
-cp.code() += "return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "ecall" << " # " << ba << (" []");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
-// WFI -------------------------------------------------------------------------
-static InstructionDefinition wfi_ (
-	ISA32_RV32IMACFD,
-	"wfi",
-	(uint32_t) 0x10500073,
-	(uint32_t) 0xffffffff,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//WFI\n");
-
-// -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "wait(1U);\n";
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "wfi" << " # " << ba << (" []");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index 18ff0f96f4..e0bea58d8c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
@@ -46,17 +46,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MUL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)(res);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -118,17 +126,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)((res >> 32UL));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -190,17 +206,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULHSU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)((res >> 32UL));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -262,17 +286,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULHU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint32)((res >> 32UL));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -334,27 +366,39 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIV\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
-etiss_uint32 MMIN = 2147483648U;
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(MMIN) + "U;\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1;\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+etiss_uint32 MMIN = 2147483648ULL;
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(MMIN) + "ULL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -416,21 +460,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIVU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1;\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -492,27 +544,39 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REM\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
-etiss_uint32 MMIN = 2147483648U;
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = 0U;\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+etiss_uint32 MMIN = 2147483648ULL;
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0ULL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -574,21 +638,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REMU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0U) {\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index a78ddf73a4..e0797c97e0 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
@@ -47,8 +47,8 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "((RV32IMACFD*)cpu)->FENCE[1U] = " + std::to_string(imm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+cp.code() += "((RV32IMACFD*)cpu)->FENCE[1ULL] = " + std::to_string(imm) + "ULL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index 1f14378c31..59e6210750 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
@@ -46,21 +46,33 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
-else {
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -122,20 +134,24 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRS\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-if (rs1 != 0U) {
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | xrs1);\n";
-}
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+if (rs1 != 0ULL) { // conditional
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
+} // conditional
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -197,20 +213,24 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRC\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-if (rs1 != 0U) {
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & ~(xrs1));\n";
-}
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+if (rs1 != 0ULL) { // conditional
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
+} // conditional
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -272,16 +292,20 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRWI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, " + std::to_string((etiss_uint32)(zimm)) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -343,18 +367,22 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRSI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-if (zimm != 0U) {
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | " + std::to_string((etiss_uint32)(zimm)) + "U);\n";
-}
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+if (zimm != 0ULL) { // conditional
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
+} // conditional
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -416,18 +444,22 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRCI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-if (zimm != 0U) {
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "U);\n";
-}
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+if (zimm != 0ULL) { // conditional
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "ULL);\n";
+} // conditional
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 2e56b51f59..e6cfe0c4d0 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Mon, 25 Sep 2023 14:27:10 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
@@ -14,6 +14,73 @@ using namespace etiss;
 using namespace etiss::instr;
 
 
+// ECALL -----------------------------------------------------------------------
+static InstructionDefinition ecall_ (
+	ISA32_RV32IMACFD,
+	"ecall",
+	(uint32_t) 0x000073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//ECALL\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//ECALL\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ecall" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
 // MRET ------------------------------------------------------------------------
 static InstructionDefinition mret_ (
 	ISA32_RV32IMACFD,
@@ -37,22 +104,33 @@ static InstructionDefinition mret_ (
 		cp.code() = std::string("//MRET\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < 3) {\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833];\n";
-cp.code() += "etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[768];\n";
-cp.code() += "etiss_uint32 prev_prv = get_field(s, 6144);\n";
-cp.code() += "if (prev_prv != 3) {\n";
-cp.code() += "s = set_field(s, 131072, 0U);\n";
-cp.code() += "}\n";
-cp.code() += "s = set_field(s, 8, get_field(s, 128));\n";
-cp.code() += "s = set_field(s, 128, 1U);\n";
-cp.code() += "s = set_field(s, 6144, (extension_enabled(cpu, system, plugin_pointers, 85U)) ? (0) : (3));\n";
-cp.code() += "*((RV32IMACFD*)cpu)->CSR[768] = s;\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833LL];\n";
+cp.code() += "etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 768LL);\n";
+cp.code() += "etiss_uint32 prev_prv = get_field(s, 6144LL);\n";
+cp.code() += "if (prev_prv != 3LL) { // conditional\n";
+cp.code() += "s = set_field(s, 131072LL, 0ULL);\n";
+cp.code() += "} // conditional\n";
+cp.code() += "if (prev_prv != ((RV32IMACFD*)cpu)->PRIV && csr_read(cpu, system, plugin_pointers, 384LL) != 0ULL) { // conditional\n";
+cp.code() += "etiss_icache_flush(cpu, system, plugin_pointers);\n";
+cp.code() += "} // conditional\n";
+cp.code() += "s = set_field(s, 8LL, get_field(s, 128LL));\n";
+cp.code() += "s = set_field(s, 128LL, 1ULL);\n";
+cp.code() += "s = set_field(s, 6144LL, (extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -85,6 +163,66 @@ ss << "mret" << " # " << ba << (" []");
 	}
 );
 
+// WFI -------------------------------------------------------------------------
+static InstructionDefinition wfi_ (
+	ISA32_RV32IMACFD,
+	"wfi",
+	(uint32_t) 0x10500073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//WFI\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//WFI\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "wfi" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
 // SRET ------------------------------------------------------------------------
 static InstructionDefinition sret_ (
 	ISA32_RV32IMACFD,
@@ -108,19 +246,27 @@ static InstructionDefinition sret_ (
 		cp.code() = std::string("//SRET\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((get_field(*((RV32IMACFD*)cpu)->CSR[768], 4194304)) ? (3) : (1))) {\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((get_field(csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321];\n";
-cp.code() += "etiss_uint32 s = *((RV32IMACFD*)cpu)->CSR[256];\n";
-cp.code() += "etiss_uint32 prev_prv = get_field(s, 256);\n";
-cp.code() += "s = set_field(s, 2, get_field(s, 32));\n";
-cp.code() += "s = set_field(s, 32, 1U);\n";
-cp.code() += "s = set_field(s, 256, 0);\n";
-cp.code() += "*((RV32IMACFD*)cpu)->CSR[768] = s;\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321LL];\n";
+cp.code() += "etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 256LL);\n";
+cp.code() += "etiss_uint32 prev_prv = get_field(s, 256LL);\n";
+cp.code() += "s = set_field(s, 2LL, get_field(s, 32LL));\n";
+cp.code() += "s = set_field(s, 32LL, 1ULL);\n";
+cp.code() += "s = set_field(s, 256LL, 0LL);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 29b52adf5c..15fe6ba0ec 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -49,24 +49,32 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//LRW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";
-if (rd) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res);\n";
-}
+if (rd) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -146,27 +154,35 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//SCW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-cp.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+cp.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-if (rd) {
-cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
-}
-cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1;\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // conditional\n";
+if (rd) { // conditional
+cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
+} // conditional
+cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1LL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 32);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index 15595f380c..4067f19b1a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
@@ -37,49 +37,89 @@ static InstructionDefinition ebreak_ (
 		cp.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4U) + "U;\n";
-cp.code() += "if (etiss_semihost_enabled()) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (etiss_semihost_enabled()) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4U) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4ULL) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
-cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0U) + "U, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0ULL) + "ULL, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
 cp.code() += "etiss_uint32 mem_val_2;\n";
-cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4U) + "U, (etiss_uint8*)&mem_val_2, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4ULL) + "ULL, (etiss_uint8*)&mem_val_2, 4);\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
-cp.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
-cp.code() += "etiss_uint32 operation = *((RV32IMACFD*)cpu)->X[10U];\n";
-cp.code() += "etiss_uint32 parameter = *((RV32IMACFD*)cpu)->X[11U];\n";
-cp.code() += "*((RV32IMACFD*)cpu)->X[10U] = (etiss_int32)(etiss_semihost(cpu, system, plugin_pointers, 32U, operation, parameter));\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3);\n";
+cp.code() += "if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 operation = *((RV32IMACFD*)cpu)->X[10ULL];\n";
+cp.code() += "etiss_uint32 parameter = *((RV32IMACFD*)cpu)->X[11ULL];\n";
+cp.code() += "*((RV32IMACFD*)cpu)->X[10ULL] = (etiss_int32)(etiss_semihost(cpu, system, plugin_pointers, 32ULL, operation, parameter));\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3);\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[10U], 32);
-		cp.getRegisterDependencies().add(reg_name[11U], 32);
-		cp.getAffectedRegisters().add(reg_name[10U], 32);
+		cp.getRegisterDependencies().add(reg_name[10ULL], 32);
+		cp.getRegisterDependencies().add(reg_name[11ULL], 32);
+		cp.getAffectedRegisters().add(reg_name[10ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -88,7 +128,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt
index efb1120161..2c7bc4654f 100644
--- a/ArchImpl/RV64IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV64IMACFD/CMakeLists.txt
@@ -1,9 +1,12 @@
-# Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+# Generated on Wed, 13 Sep 2023 20:22:42 +0200.
 #
 # This file contains the CMake build info for the RV64IMACFD core architecture.
 
 PROJECT(RV64IMACFD)
 
+SET(CMAKE_BUILD_WITH_INSTALL_RPATH TRUE)
+SET(CMAKE_INSTALL_RPATH "\$ORIGIN/../../include/jit/etiss/jit")
+
 ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV64IMACFDArch.cpp
 	RV64IMACFDArchLib.cpp
@@ -23,8 +26,8 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV64IMACFD_RV32AInstr.cpp
 	RV64IMACFD_RV64AInstr.cpp
 	RV64IMACFD_ZifenceiInstr.cpp
-	RV64IMACFD_tum_retInstr.cpp
 	RV64IMACFD_tum_csrInstr.cpp
+	RV64IMACFD_tum_retInstr.cpp
 	RV64IMACFD_tum_rvaInstr.cpp
 	RV64IMACFD_tum_rva64Instr.cpp
 	RV64IMACFD_tum_semihostingInstr.cpp
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
index f5fc2d6905..fdb31b5e21 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
@@ -206,11 +206,11 @@ const std::set<std::string> & RV64IMACFDArch::getHeaders() const
 
 void RV64IMACFDArch::initCodeBlock(etiss::CodeBlock & cb) const
 {
-	cb.fileglobalCode().insert("#include \"Arch/RV64IMACFD/RV64IMACFD.h\"\n");
-	cb.fileglobalCode().insert("#include \"Arch/RV64IMACFD/RV64IMACFDFuncs.h\"\n");
-	cb.functionglobalCode().insert("cpu->exception = 0;\n");
-	cb.functionglobalCode().insert("cpu->return_pending = 0;\n");
-	cb.functionglobalCode().insert("etiss_uint32 mem_ret_code = 0;\n");
+	cb.fileglobalCode().push_back("#include \"Arch/RV64IMACFD/RV64IMACFD.h\"\n");
+	cb.fileglobalCode().push_back("#include \"Arch/RV64IMACFD/RV64IMACFDFuncs.h\"\n");
+	cb.functionglobalCode().push_back("cpu->exception = 0;\n");
+	cb.functionglobalCode().push_back("cpu->return_pending = 0;\n");
+	cb.functionglobalCode().push_back("etiss_uint32 mem_ret_code = 0;\n");
 }
 
 etiss::plugin::gdb::GDBCore & RV64IMACFDArch::getGDBCore()
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
index f8d7b5f674..13b4b9f8e2 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
@@ -10,6 +10,7 @@
 #include "etiss/CPUArch.h"
 #include "etiss/Instruction.h"
 #include "etiss/InterruptVector.h"
+#include "etiss/InterruptEnable.h"
 #include "RV64IMACFD.h"
 #include "RV64IMACFDGDBCore.h"
 
@@ -89,7 +90,8 @@ class RV64IMACFDArch : public etiss::CPUArch {
 	*/
 	virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU * cpu);
 	virtual void deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu);
-
+    virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu);
+    virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu);
 	/**
 		@brief get the GDBcore for RV64IMACFD architecture
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
index 46b6aabefe..f569075400 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -13,6 +13,10 @@
 #include "RV64IMACFDArch.h"
 #include "RV64IMACFDArchSpecificImp.h"
 
+#define ETISS_ARCH_STATIC_FN_ONLY
+extern "C" {
+#include "RV64IMACFDFuncs.h"
+}
 /**
 	@brief This function will be called automatically in order to handling exceptions such as interrupt, system call, illegal instructions
 
@@ -29,13 +33,10 @@
 */
 etiss::int32 RV64IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu)
 {
-	etiss_uint32 handledCause = cause;
-
-	/**************************************************************************
-	*		 Exception handling machanism should be implemented here		  *
-	***************************************************************************/
+	translate_exc_code(cpu, nullptr, nullptr, cause);
+	cpu->instructionPointer = cpu->nextPc;
 
-	return handledCause;
+	return 0;
 }
 
 /**
@@ -122,8 +123,12 @@ error_code += R_error_code_0.read(ba) << 0;
 		cp.code() = std::string("//trap_entry 32\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, (cpu->exception) ? (cpu->exception) : (" + std::to_string(error_code) + "ULL));\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -165,8 +170,12 @@ error_code += R_error_code_0.read(ba) << 0;
 		cp.code() = std::string("//trap_entry 16\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "U);\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, (cpu->exception) ? (cpu->exception) : (" + std::to_string(error_code) + "ULL));\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -344,13 +353,28 @@ etiss::InterruptVector * RV64IMACFDArch::createInterruptVector(ETISS_CPU * cpu)
 	// This is a default vector, implemented to avoid segfaults. Replace
 	// with actual implementation if necessary.
 
-	std::vector<etiss::uint32 *> vec;
-	std::vector<etiss::uint32 *> mask;
+	std::vector<etiss::uint64 *> vec;
+	std::vector<etiss::uint64 *> mask;
+
+	RV64IMACFD* rvcpu = (RV64IMACFD*)cpu;
+
+	vec.push_back(rvcpu->CSR[0x344]);
+	mask.push_back(rvcpu->CSR[0x304]);
 
-	return new etiss::MappedInterruptVector<etiss::uint32>(vec, mask);
+	return new etiss::MappedInterruptVector<etiss::uint64>(vec, mask);
 }
 
 void RV64IMACFDArch::deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu)
 {
 	delete vec;
 }
+
+etiss::InterruptEnable* RV64IMACFDArch::createInterruptEnable(ETISS_CPU* cpu) {
+	RV64IMACFD* rvcpu = (RV64IMACFD*)cpu;
+
+	return new etiss::MappedInterruptEnable<etiss::uint64>(rvcpu->CSR[0x300], 0xf);
+}
+
+void RV64IMACFDArch::deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu) {
+	delete en;
+}
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index fa540047e2..a607eaa47e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Thu, 28 Sep 2023 00:51:23 +0200.
  *
  * This file contains the function macros for the RV64IMACFD core architecture.
  */
@@ -16,305 +16,429 @@
 
 
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern void leave(etiss_int32 priv_lvl);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern void wait(etiss_int32 flag);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
-{
-return (*((RV64IMACFD*)cpu)->CSR[769] >> (extension - 65U)) & 1U;
-}
-#endif
+static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 unbox_s(etiss_uint64);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fclass_s(etiss_uint32);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fget_flags();
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 unbox_d(etiss_uint64);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 fclass_d(etiss_uint64);
-#endif
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
-{
-return (reg & mask) / (mask & ~((mask << 1UL)));
-}
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
-{
-return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1UL)))) & mask));
-}
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_int32 mcause)
-{
-cpu->return_pending = 1;
-etiss_uint64 epc = cpu->instructionPointer;
-if (((RV64IMACFD*)cpu)->PRIV <= 1 && (*((RV64IMACFD*)cpu)->CSR[770] >> mcause) & 1U) {
-cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[261] & -2L);
-*((RV64IMACFD*)cpu)->CSR[321] = epc;
-*((RV64IMACFD*)cpu)->CSR[322] = mcause;
-etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[256];
-s = set_field(s, 32, get_field(s, 2));
-s = set_field(s, 256, ((RV64IMACFD*)cpu)->PRIV);
-s = set_field(s, 2, 0U);
-*((RV64IMACFD*)cpu)->CSR[256] = s;
-((RV64IMACFD*)cpu)->PRIV = (1) & 0x7;
-}
-else {
-cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773] & -2L);
-*((RV64IMACFD*)cpu)->CSR[833] = epc;
-*((RV64IMACFD*)cpu)->CSR[834] = mcause;
-etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[768];
-s = set_field(s, 128, get_field(s, 8));
-s = set_field(s, 6144, ((RV64IMACFD*)cpu)->PRIV);
-s = set_field(s, 8, 0U);
-*((RV64IMACFD*)cpu)->CSR[768] = s;
-((RV64IMACFD*)cpu)->PRIV = (3) & 0x7;
-}
-}
-#endif
-
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
-{
-etiss_int32 code = 0U;
-if (cause == -2147483648) {
-return;
-}
- else if (cause == -5) {
-code = 5;
-}
- else if (cause == -14) {
-code = 13;
-}
- else if (cause == -6) {
-code = 7;
-}
- else if (cause == -15) {
-code = 15;
-}
- else if (cause == -7) {
-code = 1;
-}
-else {
-code = 2;
-}
-cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, code);
-}
-#endif
+extern etiss_int32 ETISS_SIGNAL_MMU(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint64 mmu_signal_);
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 etiss_get_time();
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 extern etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-static inline etiss_uint64 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+static inline etiss_uint64 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+
+static inline etiss_uint64 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+
+static inline etiss_uint64 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
+
+static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val);
+
+extern void etiss_icache_flush(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+
+static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask);
+
+static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
+
+static inline etiss_uint8 ctz(etiss_uint64 val);
+
+static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause);
+
+static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
+
+static inline etiss_uint64 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+
+static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+
+extern etiss_uint8 etiss_semihost_enabled();
+
+extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
+
+static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
 {
-etiss_uint64 mask = 0U;
-if (extension_enabled(cpu, system, plugin_pointers, 83U)) {
-mask = mask | 5767458UL;
-if (extension_enabled(cpu, system, plugin_pointers, 86U)) {
-mask = mask | 1536L;
-}
-if (extension_enabled(cpu, system, plugin_pointers, 70U)) {
-mask = mask | 24576L;
-}
-if (extension_enabled(cpu, system, plugin_pointers, 88U)) {
-mask = mask | 98304L;
-}
-if (0U && get_field(*((RV64IMACFD*)cpu)->CSR[384], 2147483648U) || 1U && get_field(*((RV64IMACFD*)cpu)->CSR[384], 17293822569102704640UL)) {
-mask = mask | 262144L;
-}
+{ // block
+return (*((RV64IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
+} // block
 }
+
+static inline etiss_uint64 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 mask = 0ULL;
+if (extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
+{ // block
+mask = mask | 5767458ULL;
+if (extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
+mask = mask | 1536LL;
+} // conditional
+if (extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
+mask = mask | 24576LL;
+} // conditional
+if (extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
+mask = mask | 98304LL;
+} // conditional
+if ((get_field(*((RV64IMACFD*)cpu)->CSR[384LL], 17293822569102704640ULL))) { // conditional
+mask = mask | 262144LL;
+} // conditional
+} // block
+} // conditional
 return mask;
+} // block
 }
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint64 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
 {
-etiss_uint64 mask = 6280U;
+{ // block
+etiss_uint64 mask = 6280ULL;
 return mask | sstatus_mask(cpu, system, plugin_pointers);
+} // block
 }
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline etiss_uint64 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
 {
-if (csr == 1) {
-return *((RV64IMACFD*)cpu)->CSR[3] & 31UL;
-}
-if (csr == 2) {
-return (*((RV64IMACFD*)cpu)->CSR[3] >> 5UL) & 7U;
-}
-if (csr == 3072) {
+{ // block
+if (csr == 1LL) { // conditional
+return *((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL;
+} // conditional
+if (csr == 2LL) { // conditional
+return (*((RV64IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
+} // conditional
+if (csr == 3072LL) { // conditional
 return etiss_get_cycles(cpu, system, plugin_pointers);
-}
-if (csr == 3200) {
-return etiss_get_cycles(cpu, system, plugin_pointers) >> 32U;
-}
-if (csr == 3073) {
+} // conditional
+if (csr == 3200LL) { // conditional
+return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 3073LL) { // conditional
 return etiss_get_time();
-}
-if (csr == 3201) {
-return etiss_get_time() >> 32U;
-}
-if (csr == 3074) {
+} // conditional
+if (csr == 3201LL) { // conditional
+return etiss_get_time() >> 32ULL;
+} // conditional
+if (csr == 3074LL) { // conditional
 return etiss_get_instret(cpu, system, plugin_pointers);
-}
-if (csr == 3202) {
-return etiss_get_instret(cpu, system, plugin_pointers) >> 32U;
-}
-if (csr == 768 || csr == 256) {
-return *((RV64IMACFD*)cpu)->CSR[768] | 8589934592UL | 34359738368UL;
-}
-if (csr == 769) {
-return (((2U) << 62) | ((((*((RV64IMACFD*)cpu)->CSR[769]) >> (0U)) & 4611686018427387903)));
-}
+} // conditional
+if (csr == 3202LL) { // conditional
+return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 768LL || csr == 256LL) { // conditional
+return *((RV64IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
+} // conditional
+if (csr == 769LL) { // conditional
+return (((2ULL) << 62) | ((((*((RV64IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 4611686018427387903)));
+} // conditional
 return *((RV64IMACFD*)cpu)->CSR[csr];
+} // block
 }
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
 static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val)
 {
-if (csr == 1) {
-*((RV64IMACFD*)cpu)->CSR[3] = (*((RV64IMACFD*)cpu)->CSR[3] & 224UL) | (val & 31UL);
-}
- else if (csr == 2) {
-*((RV64IMACFD*)cpu)->CSR[3] = ((val & 7UL) << 5U) | (*((RV64IMACFD*)cpu)->CSR[3] & 31UL);
-}
- else if (csr == 3) {
-*((RV64IMACFD*)cpu)->CSR[3] = val & 255UL;
-}
- else if (csr == 768) {
-*((RV64IMACFD*)cpu)->CSR[768] = val & mstatus_mask(cpu, system, plugin_pointers);
+{ // block
+if (csr == 1LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[3LL] = (*((RV64IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
+} // conditional
+ else if (csr == 2LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL);
+} // conditional
+ else if (csr == 3LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
+} // conditional
+ else if (csr == 768LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[768LL] = val & mstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr == 256LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[768LL] = val & sstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr != 769LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[csr] = val;
+} // conditional
+if (csr == 384LL) { // conditional
+ETISS_SIGNAL_MMU(cpu, system, plugin_pointers, val);
+} // conditional
+} // block
 }
- else if (csr == 256) {
-*((RV64IMACFD*)cpu)->CSR[768] = val & sstatus_mask(cpu, system, plugin_pointers);
+
+static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
+{
+{ // block
+return (reg & mask) / (mask & ~((mask << 1ULL)));
+} // block
 }
- else if (csr != 769) {
-*((RV64IMACFD*)cpu)->CSR[csr] = val;
+
+static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
+{
+{ // block
+return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
+} // block
 }
+
+static inline etiss_uint8 ctz(etiss_uint64 val)
+{
+{ // block
+if (!(val)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint8 res = 0ULL;
+if ((val << 32ULL) == 0ULL) { // conditional
+{ // block
+res = res + 32ULL;
+val = val >> 32ULL;
+} // block
+} // conditional
+if ((val << 48ULL) == 0ULL) { // conditional
+{ // block
+res = res + 16ULL;
+val = val >> 16ULL;
+} // block
+} // conditional
+if ((val << 56ULL) == 0ULL) { // conditional
+{ // block
+res = res + 8ULL;
+val = val >> 8ULL;
+} // block
+} // conditional
+if ((val << 60ULL) == 0ULL) { // conditional
+{ // block
+res = res + 4ULL;
+val = val >> 4ULL;
+} // block
+} // conditional
+if ((val << 62ULL) == 0ULL) { // conditional
+{ // block
+res = res + 2ULL;
+val = val >> 2ULL;
+} // block
+} // conditional
+if ((val << 63ULL) == 0ULL) { // conditional
+{ // block
+res = res + 1ULL;
+val = val >> 1ULL;
+} // block
+} // conditional
+return res;
+} // block
+}
+
+static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause)
+{
+cpu->return_pending = 1;
+cpu->exception = 0;
+{ // block
+etiss_uint64 epc = cpu->instructionPointer;
+etiss_uint64 deleg = 0ULL;
+etiss_uint64 vector = 0ULL;
+etiss_uint64 bit = mcause;
+etiss_int32 irq2 = (mcause & 9223372036854775808ULL) != 0ULL;
+if (irq2) { // conditional
+{ // block
+deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[771LL]) : (0ULL);
+bit = bit & -9223372036854775809LL;
+} // block
+} // conditional
+else { // conditional
+{ // block
+deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[770LL]) : (0ULL);
+} // block
+} // conditional
+if (((RV64IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
+{ // block
+vector = ((*((RV64IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
+*((RV64IMACFD*)cpu)->CSR[321LL] = epc;
+*((RV64IMACFD*)cpu)->CSR[322LL] = mcause;
+etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 256LL);
+s = set_field(s, 32LL, get_field(s, 2LL));
+s = set_field(s, 256LL, ((RV64IMACFD*)cpu)->PRIV);
+s = set_field(s, 2LL, 0ULL);
+csr_write(cpu, system, plugin_pointers, 256LL, s);
+((RV64IMACFD*)cpu)->PRIV = (1LL) & 0x7;
+} // block
+} // conditional
+else { // conditional
+{ // block
+vector = ((*((RV64IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
+*((RV64IMACFD*)cpu)->CSR[833LL] = epc;
+*((RV64IMACFD*)cpu)->CSR[834LL] = mcause;
+etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 768LL);
+s = set_field(s, 128LL, get_field(s, 8LL));
+s = set_field(s, 6144LL, ((RV64IMACFD*)cpu)->PRIV);
+s = set_field(s, 8LL, 0ULL);
+csr_write(cpu, system, plugin_pointers, 768LL, s);
+((RV64IMACFD*)cpu)->PRIV = (3LL) & 0x7;
+} // block
+} // conditional
+} // block
 }
-#endif
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-extern etiss_uint8 etiss_semihost_enabled();
-#endif
+static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
+{
+{ // block
+etiss_uint64 code = 0ULL;
+if (cause == -2147483648LL) { // conditional
+return;
+} // conditional
+ else if (cause == -5LL) { // conditional
+code = 5LL;
+} // conditional
+ else if (cause == -13LL) { // conditional
+code = 12LL;
+} // conditional
+ else if (cause == -14LL) { // conditional
+code = 13LL;
+} // conditional
+ else if (cause == -6LL) { // conditional
+code = 7LL;
+} // conditional
+ else if (cause == -15LL) { // conditional
+code = 15LL;
+} // conditional
+ else if (cause == -7LL) { // conditional
+code = 1LL;
+} // conditional
+ else if (cause == -9LL) { // conditional
+{ // block
+code = calc_irq_mcause(cpu, system, plugin_pointers);
+if (!(code)) { // conditional
+return;
+} // conditional
+} // block
+} // conditional
+else { // conditional
+code = 2LL;
+} // conditional
+raise(cpu, system, plugin_pointers, 0ULL, code);
+} // block
+}
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
-#endif
-#endif
+static inline etiss_uint64 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 pending_interrupts = *((RV64IMACFD*)cpu)->CSR[772LL] & *((RV64IMACFD*)cpu)->CSR[836LL];
+if (!(pending_interrupts)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint64 mie = get_field(*((RV64IMACFD*)cpu)->CSR[768LL], 8LL);
+etiss_uint64 m_enabled = ((RV64IMACFD*)cpu)->PRIV < 3LL || (((RV64IMACFD*)cpu)->PRIV == 3LL && mie);
+etiss_uint64 enabled_interrupts = pending_interrupts & ~(*((RV64IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
+if (enabled_interrupts == 0ULL) { // conditional
+{ // block
+etiss_uint64 deleg = *((RV64IMACFD*)cpu)->CSR[771LL];
+etiss_uint64 sie = get_field(csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
+etiss_uint64 s_enabled = ((RV64IMACFD*)cpu)->PRIV < 1LL || (((RV64IMACFD*)cpu)->PRIV == 1LL && sie);
+enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
+} // block
+} // conditional
+if (enabled_interrupts) { // conditional
+{ // block
+if (enabled_interrupts >> 12ULL) { // conditional
+enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
+} // conditional
+ else if (enabled_interrupts & 2048LL) { // conditional
+enabled_interrupts = 2048LL;
+} // conditional
+ else if (enabled_interrupts & 8LL) { // conditional
+enabled_interrupts = 8LL;
+} // conditional
+ else if (enabled_interrupts & 128LL) { // conditional
+enabled_interrupts = 128LL;
+} // conditional
+ else if (enabled_interrupts & 512LL) { // conditional
+enabled_interrupts = 512LL;
+} // conditional
+ else if (enabled_interrupts & 2LL) { // conditional
+enabled_interrupts = 2LL;
+} // conditional
+ else if (enabled_interrupts & 32LL) { // conditional
+enabled_interrupts = 32LL;
+} // conditional
+ else if (enabled_interrupts & 8192LL) { // conditional
+enabled_interrupts = 8192LL;
+} // conditional
+ else if (enabled_interrupts & 1024LL) { // conditional
+enabled_interrupts = 1024LL;
+} // conditional
+ else if (enabled_interrupts & 4LL) { // conditional
+enabled_interrupts = 4LL;
+} // conditional
+ else if (enabled_interrupts & 64LL) { // conditional
+enabled_interrupts = 64LL;
+} // conditional
+else { // conditional
+return 0ULL;
+} // conditional
+return 9223372036854775808ULL | ctz(enabled_interrupts);
+} // block
+} // conditional
+return 0ULL;
+} // block
+}
+
+static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 irq_mcause = calc_irq_mcause(cpu, system, plugin_pointers);
+if (irq_mcause) { // conditional
+raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
+} // conditional
+} // block
+}
+#endif
\ No newline at end of file
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index 88b038cde9..a7627c0cad 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
@@ -52,30 +52,42 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOSWAPW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-if ((rd % 32U) != 0U) {
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
+} // conditional
 cp.code() += "etiss_uint32 mem_val_1;\n";
-cp.code() += "mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -158,32 +170,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOADDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -266,32 +290,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOXORW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -374,32 +410,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOANDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -482,32 +530,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOORW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -590,32 +650,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMINW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -698,32 +770,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -806,32 +890,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMINUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res1);\n";
-}
-cp.code() += "etiss_uint32 res2 = (res1 > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res1);\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = (res1 > (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -914,32 +1010,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int32)(res1);\n";
-}
-cp.code() += "etiss_uint32 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res1);\n";
+} // conditional
+cp.code() += "etiss_uint32 res2 = (res1 < (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index 531db0e1df..914491c2eb 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
@@ -48,20 +48,28 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFLD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "U] = res;\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -136,19 +144,27 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFSD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -222,20 +238,28 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CFLDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 64);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -306,19 +330,27 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFSDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 64);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index d158ce3a74..435f4f7a09 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
@@ -46,20 +46,28 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//FLD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -132,19 +140,27 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//FSD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -223,11 +239,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -304,11 +324,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -385,11 +409,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -466,11 +494,15 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -544,11 +576,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -619,11 +655,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -694,11 +734,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMUL_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -769,11 +813,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FDIV_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -841,11 +889,15 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FSQRT_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -910,9 +962,13 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJ_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1)) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1)) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -977,9 +1033,13 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJN_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) >> (63U)) & 1))) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) >> (0U)) & 9223372036854775807)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1))) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1044,9 +1104,13 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJX_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]) & 9223372036854775808UL);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) & 9223372036854775808ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1111,11 +1175,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMIN_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 0U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 0ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1180,11 +1248,15 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMAX_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), 1U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 1ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1249,9 +1321,13 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L + res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL + res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1316,9 +1392,17 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), " + std::to_string(rm) + "ULL);\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1383,18 +1467,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FEQ_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = 0U;\n";
-cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 0U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = 0ULL;\n";
+cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 0ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1456,18 +1544,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLT_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = 0U;\n";
-cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 2U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = 0ULL;\n";
+cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 2ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1529,18 +1621,22 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLE_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = 0U;\n";
-cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U], 1U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = 0ULL;\n";
+cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 1ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1599,12 +1695,16 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCLASS_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1663,18 +1763,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_W_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_int32 res = 0U;\n";
-cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 0U, " + std::to_string(rm) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int32 res = 0ULL;\n";
+cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 0ULL, " + std::to_string(rm) + "ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1736,18 +1840,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_WU_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U], 1U, " + std::to_string(rm) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 1ULL, " + std::to_string(rm) + "ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1809,13 +1917,17 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1877,13 +1989,17 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_WU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index 2bc4ded06c..cc75889376 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
@@ -46,20 +46,32 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//FLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -132,19 +144,27 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//FSW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -223,11 +243,19 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 0U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -304,11 +332,19 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]), 1U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -385,14 +421,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -469,14 +513,22 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "U]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -550,13 +602,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -627,13 +687,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -704,13 +772,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMUL_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -781,13 +857,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FDIV_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -855,12 +939,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FSQRT_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + "U) ? (" + std::to_string(rm) + "U) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -925,11 +1017,19 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJ_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = ((((((frs2) >> (31ULL)) & 1)) << 31) | ((((frs1) >> (0ULL)) & 2147483647)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -994,11 +1094,19 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJN_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31ULL)) & 1))) << 31) | ((((frs1) >> (0ULL)) & 2147483647)));\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1063,11 +1171,19 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJX_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1132,13 +1248,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMIN_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1203,13 +1327,21 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMAX_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1274,19 +1406,27 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_W_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_int32 res = 0U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int32 res = 0ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "res = fcvt_s(frs1, 0ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "} // block\n";
+} // block
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1348,19 +1488,27 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_WU_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "res = fcvt_s(frs1, 1ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "} // block\n";
+} // block
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1422,20 +1570,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FEQ_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "res = fcmp_s(frs1, frs2, 0U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 0ULL);\n";
+cp.code() += "} // block\n";
+} // block
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1497,20 +1653,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLT_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "res = fcmp_s(frs1, frs2, 2U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 2ULL);\n";
+cp.code() += "} // block\n";
+} // block
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1572,20 +1736,28 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLE_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]);\n";
-cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "U]);\n";
-cp.code() += "res = fcmp_s(frs1, frs2, 1U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
+cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
+cp.code() += "res = fcmp_s(frs1, frs2, 1ULL);\n";
+cp.code() += "} // block\n";
+} // block
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1644,16 +1816,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCLASS_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = 0U;\n";
-cp.code() += "res = fclass_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = 0ULL;\n";
+cp.code() += "res = fclass_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1712,13 +1888,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 2U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1780,13 +1964,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_WU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]), 3U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1845,14 +2037,18 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_X_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1908,12 +2104,20 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_W_X\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index 3a680a137d..18815d89dd 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
@@ -49,19 +49,23 @@ imm += R_imm_4.read(ba) << 4;
 		cp.code() = std::string("//CADDI4SPN\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if (imm) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(imm) + "U;\n";
-}
-else {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if (imm) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(imm) + "ULL;\n";
+} // conditional
+else { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -139,20 +143,28 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int32)(mem_val_0);\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int32)(mem_val_0);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -231,20 +243,28 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CSW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -318,15 +338,15 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CADDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if ((rs1 % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if ((rs1 % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -383,7 +403,11 @@ nzimm += R_nzimm_5.read(ba) << 5;
 		cp.code() = std::string("//CNOP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -443,14 +467,18 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -510,18 +538,26 @@ imm += R_imm_17.read(ba) << 17;
 		cp.code() = std::string("//CLUI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if (imm == 0U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm == 0ULL) { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int32)(((etiss_int32)imm) << (14)) >> (14))) + "LL;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -593,19 +629,23 @@ nzimm += R_nzimm_9.read(ba) << 9;
 		cp.code() = std::string("//CADDI16SP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if (nzimm) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[2U] = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n";
-}
-else {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if (nzimm) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[2ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)nzimm) << (6)) >> (6))) + "LL;\n";
+} // conditional
+else { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 64);
-		cp.getAffectedRegisters().add(reg_name[2U], 64);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[2ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -672,9 +712,13 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//__reserved_clui\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -739,13 +783,17 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -801,15 +849,23 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if (shamt) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if (shamt) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -867,13 +923,17 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CANDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] & " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -931,14 +991,18 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CSUB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -994,14 +1058,18 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CXOR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1057,14 +1125,18 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//COR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1120,14 +1192,18 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CAND\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1194,8 +1270,8 @@ imm += R_imm_11.read(ba) << 11;
 		cp.code() = std::string("//CJ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1282,14 +1358,14 @@ imm += R_imm_8.read(ba) << 8;
 		cp.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] == 0UL) {\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
-cp.code() += "}\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] == 0ULL) { // conditional\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
+cp.code() += "} // conditional\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1298,7 +1374,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -1370,14 +1446,14 @@ imm += R_imm_8.read(ba) << 8;
 		cp.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] != 0UL) {\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n";
-cp.code() += "}\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] != 0ULL) { // conditional\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
+cp.code() += "} // conditional\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1386,7 +1462,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -1450,15 +1526,15 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if (nzuimm) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(nzuimm) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if (nzuimm) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(nzuimm) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1518,25 +1594,41 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CLWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if (rd % 32U) {
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if (rd % 32ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res = mem_val_0;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
-}
-else {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1605,15 +1697,15 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CMV\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1666,18 +1758,22 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CJR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if (rs1) {
-cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & -2L;\n";
-}
-else {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if (rs1) { // conditional
+cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & -2LL;\n";
+} // conditional
+else { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1733,9 +1829,13 @@ static InstructionDefinition __reserved_cmv_ (
 		cp.code() = std::string("//__reserved_cmv\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1797,16 +1897,16 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CADD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rd % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1859,15 +1959,19 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CJALR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[1U] = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "cpu->nextPc = new_pc & -2L;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[1U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[1ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1923,9 +2027,13 @@ static InstructionDefinition cebreak_ (
 		cp.code() = std::string("//CEBREAK\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -1989,20 +2097,28 @@ uimm += R_uimm_2.read(ba) << 2;
 		cp.code() = std::string("//CSWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -2063,9 +2179,13 @@ static InstructionDefinition dii_ (
 		cp.code() = std::string("//DII\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index 752d415734..a69a65aef4 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
@@ -43,14 +43,14 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//LUI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -106,14 +106,14 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//AUIPC\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + "LL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -175,21 +175,37 @@ imm += R_imm_20.read(ba) << 20;
 		cp.code() = std::string("//JAL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-}
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+} // conditional
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)(((etiss_int32)imm) << (11)) >> (11))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -263,23 +279,39 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//JALR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2;\n";
-cp.code() += "if (new_pc % 2UL) {\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL) & -2LL;\n";
+cp.code() += "if (new_pc % 2ULL) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-}
-cp.code() += "cpu->nextPc = new_pc & -2L;\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+} // conditional
+cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -356,21 +388,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -379,7 +431,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -453,21 +505,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -476,7 +548,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -550,21 +622,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -573,7 +665,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -647,21 +739,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -670,7 +782,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -744,21 +856,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -767,7 +899,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -841,21 +973,41 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) {\n";
-if (imm % 2U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 0U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+if (imm % 2ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-else {
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n";
-}
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -864,7 +1016,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
@@ -932,23 +1084,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint8 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1019,23 +1179,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint16 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1106,23 +1274,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1193,23 +1369,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LBU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint8 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1280,23 +1464,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LHU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint16 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1369,20 +1561,28 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint8 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1457,20 +1657,28 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint16 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1545,20 +1753,28 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1631,15 +1847,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ADDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1701,15 +1917,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//SLTI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL)) ? (1ULL) : (0ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1771,15 +1987,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//SLTIU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U)) ? (1U) : (0U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL)) ? (1ULL) : (0ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1841,15 +2057,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//XORI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1911,15 +2127,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ORI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1981,15 +2197,15 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ANDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & " + std::to_string((etiss_uint64)((((etiss_int16)((imm) << (4)) >> (4))))) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2051,15 +2267,15 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2121,15 +2337,15 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2191,15 +2407,15 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> " + std::to_string(shamt) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2261,16 +2477,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//ADD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2332,16 +2548,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SUB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2403,16 +2619,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2474,16 +2690,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLT\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (1U) : (0U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (1ULL) : (0ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2545,16 +2761,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLTU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (1U) : (0U);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (1ULL) : (0ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2616,16 +2832,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//XOR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2687,16 +2903,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2758,16 +2974,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRA\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] & 63UL);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2829,16 +3045,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//OR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2900,16 +3116,16 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//AND\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2977,8 +3193,8 @@ fm += R_fm_0.read(ba) << 0;
 		cp.code() = std::string("//FENCE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "((RV64IMACFD*)cpu)->FENCE[0U] = " + std::to_string(pred << 4U | succ) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+cp.code() += "((RV64IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -3016,109 +3232,3 @@ ss << "fence" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std:
 		return ss.str();
 	}
 );
-
-// ECALL -----------------------------------------------------------------------
-static InstructionDefinition ecall_ (
-	ISA32_RV64IMACFD,
-	"ecall",
-	(uint32_t) 0x000073,
-	(uint32_t) 0xffffffff,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//ECALL\n");
-
-// -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 11U);\n";
-cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-	{
-		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
-
-		cp.code() = std::string("//ECALL\n");
-
-// -----------------------------------------------------------------------------
-cp.code() += "return cpu->exception;\n";
-// -----------------------------------------------------------------------------
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "ecall" << " # " << ba << (" []");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
-// WFI -------------------------------------------------------------------------
-static InstructionDefinition wfi_ (
-	ISA32_RV64IMACFD,
-	"wfi",
-	(uint32_t) 0x10500073,
-	(uint32_t) 0xffffffff,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//WFI\n");
-
-// -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "wait(1U);\n";
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "wfi" << " # " << ba << (" []");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index 3fe27802bf..db675bbfca 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
@@ -46,17 +46,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MUL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -118,17 +126,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((res >> 64ULL));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((res >> 64ULL));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -190,17 +206,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULHSU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((res >> 64ULL));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((res >> 64ULL));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -262,17 +286,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULHU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_uint128 res = (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((res >> 64ULL));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint128 res = (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((res >> 64ULL));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -334,27 +366,39 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIV\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
-etiss_uint64 MMIN = 9223372036854775808UL;
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = " + std::to_string(MMIN) + "U;\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1L;\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+etiss_uint64 MMIN = 9223372036854775808ULL;
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(MMIN) + "ULL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -416,21 +460,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIVU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1L;\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -492,27 +544,39 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REM\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
-etiss_uint64 MMIN = 9223372036854775808UL;
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] == " + std::to_string(MMIN) + "U && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = 0UL;\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+etiss_uint64 MMIN = 9223372036854775808ULL;
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0ULL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -574,21 +638,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REMU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index bfeb997b6b..f1e371cdaa 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
@@ -52,30 +52,42 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOSWAPD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-if ((rd % 32U) != 0U) {
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
+} // conditional
 cp.code() += "etiss_uint64 mem_val_1;\n";
-cp.code() += "mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -158,32 +170,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOADDD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int64 res = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
-cp.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
+cp.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -266,32 +290,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOXORD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int64 res = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
-cp.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
+cp.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -374,32 +410,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOANDD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int64 res = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
-cp.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
+cp.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -482,32 +530,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOORD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int64 res = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
-cp.code() += "etiss_uint64 res2 = (((res) << 64) | (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]));\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
+cp.code() += "etiss_uint64 res2 = (((res) << 64) | (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
 cp.code() += "etiss_uint64 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -590,32 +650,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMIND\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int64 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res1;\n";
-}
-cp.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
+} // conditional
+cp.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
 cp.code() += "etiss_uint64 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -698,32 +770,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int64 res = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
-cp.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
+cp.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res);\n";
 cp.code() += "etiss_uint64 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -806,32 +890,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMINUD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint64 res = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
-}
-cp.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
+} // conditional
+cp.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res);\n";
 cp.code() += "etiss_uint64 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -914,32 +1010,44 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXUD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint64 res1 = mem_val_0;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res1);\n";
-}
-cp.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) : (res1);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res1);\n";
+} // conditional
+cp.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
 cp.code() += "etiss_uint64 mem_val_1;\n";
 cp.code() += "mem_val_1 = res2;\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index a83c47f11e..526178367f 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
@@ -46,14 +46,18 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_L_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 0U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0ULL, " + std::to_string(rm) + "ULL);\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -115,14 +119,18 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_LU_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 1U, " + std::to_string(rm) + "U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -184,13 +192,17 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_L\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 2U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -252,13 +264,17 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_LU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 3U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = res;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -317,12 +333,16 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_X_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL];\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -378,12 +398,16 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_D_X\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index f9c135ac82..1bdcd948fb 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
@@ -46,17 +46,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_L_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 0U, " + std::to_string(rm) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0ULL, " + std::to_string(rm) + "ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -118,17 +122,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_LU_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "U]), 1U, " + std::to_string(rm) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
-cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32L) | (flags & 31U);\n";
+cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -190,13 +198,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_L\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 2U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -258,13 +274,21 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_LU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U], 3U, " + std::to_string(rm) + "U);\n";
-cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "U] = -4294967296L | (etiss_uint64)(res);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index c0dce6f47d..617e490e9c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
@@ -45,15 +45,15 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CADDIW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if ((rs1 % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+if ((rs1 % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -113,13 +113,17 @@ nzuimm += R_nzuimm_5.read(ba) << 5;
 		cp.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] >> " + std::to_string(nzuimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(nzuimm) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -179,13 +183,17 @@ shamt += R_shamt_5.read(ba) << 5;
 		cp.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U])) >> " + std::to_string(shamt) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -245,12 +253,20 @@ shamt += R_shamt_5.read(ba) << 5;
 		cp.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-if (rs1 == 0U) {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if (rs1 == 0ULL) { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "U] << " + std::to_string(shamt) + "U;\n";
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -327,20 +343,28 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CLD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_int64)(mem_val_0);\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int64)(mem_val_0);\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -415,20 +439,28 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CSD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -498,15 +530,19 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CSUBW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -562,15 +598,19 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CADDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "U]);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "U] = (etiss_uint64)((etiss_int32)(res));\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8U], 64);
+		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -630,27 +670,39 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CLDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int64 res = mem_val_0;\n";
-if (rd % 32U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = res;\n";
-}
-else {
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2U);\n";
+if (rd % 32ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
+} // conditional
+else { // conditional
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-}
+cp.code() += "} // procedure\n";
+} // procedure
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -721,20 +773,28 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CSDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2U] + " + std::to_string(uimm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index e76dab4e66..08b964c4d5 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
@@ -46,23 +46,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LWU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -133,23 +141,31 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(res);\n";
-}
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -222,20 +238,28 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -308,15 +332,15 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] << " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -378,15 +402,15 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] >> " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -448,15 +472,15 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
+} // conditional
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -518,16 +542,24 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ADDIW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -589,16 +621,24 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SLLIW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) << " + std::to_string(shamt) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) << " + std::to_string(shamt) + "ULL;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -660,16 +700,24 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRLIW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -731,16 +779,24 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRAIW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> " + std::to_string(shamt) + "U;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(sh_val);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(sh_val);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -802,17 +858,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//ADDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -874,17 +938,25 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SUBW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -946,18 +1018,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
-cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) << count;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
+cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) << count;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1019,18 +1099,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
-cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> count;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(sh_val));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
+cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> count;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1092,18 +1180,26 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRAW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) & 31U;\n";
-cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])) >> count;\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(sh_val);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
+cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> count;\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(sh_val);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index f450aca453..7f1a4ba236 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
@@ -46,16 +46,24 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -117,27 +125,39 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIVW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
-etiss_int32 MMIN = 2147483648U;
-cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -2147483648L;\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])));\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1L;\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+etiss_int32 MMIN = 2147483648ULL;
+cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) == " + std::to_string(MMIN) + "LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -2147483648LL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])));\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -199,21 +219,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIVUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) != 0U) {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = -1L;\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) != 0ULL) { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -275,27 +303,39 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REMW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U] != 0UL) {\n";
-etiss_int32 MMIN = 2147483648U;
-cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) == -1) {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = 0UL;\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U])));\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])));\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+etiss_int32 MMIN = 2147483648ULL;
+cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) == " + std::to_string(MMIN) + "LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0ULL;\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])));\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])));\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -357,21 +397,29 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REMUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]) != 0U) {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]))));\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U])));\n";
-cp.code() += "}\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) != 0ULL) { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])));\n";
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index c2a916e9d0..dff65a8b8d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
@@ -47,8 +47,8 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "((RV64IMACFD*)cpu)->FENCE[1U] = " + std::to_string(imm) + "U;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+cp.code() += "((RV64IMACFD*)cpu)->FENCE[1ULL] = " + std::to_string(imm) + "ULL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index 4f38bc7c56..cdf35fc34a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
@@ -46,21 +46,33 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
-else {
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrs1);\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -122,20 +134,24 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRS\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-if (rs1 != 0U) {
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | xrs1);\n";
-}
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+if (rs1 != 0ULL) { // conditional
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
+} // conditional
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -197,20 +213,24 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRC\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-if (rs1 != 0U) {
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & ~(xrs1));\n";
-}
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+if (rs1 != 0ULL) { // conditional
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
+} // conditional
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -272,16 +292,20 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRWI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, " + std::to_string((etiss_uint64)(zimm)) + "U);\n";
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -343,18 +367,22 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRSI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-if (zimm != 0U) {
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd | " + std::to_string((etiss_uint64)(zimm)) + "U);\n";
-}
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+if (zimm != 0ULL) { // conditional
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
+} // conditional
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -416,18 +444,22 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRCI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "U);\n";
-if (zimm != 0U) {
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "U, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "U);\n";
-}
-if ((rd % 32U) != 0U) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = xrd;\n";
-}
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+if (zimm != 0ULL) { // conditional
+cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "ULL);\n";
+} // conditional
+if ((rd % 32ULL) != 0ULL) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index c8b4e1ebb8..f75abdc562 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
@@ -14,6 +14,73 @@ using namespace etiss;
 using namespace etiss::instr;
 
 
+// ECALL -----------------------------------------------------------------------
+static InstructionDefinition ecall_ (
+	ISA32_RV64IMACFD,
+	"ecall",
+	(uint32_t) 0x000073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//ECALL\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";
+cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//ECALL\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "ecall" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
 // MRET ------------------------------------------------------------------------
 static InstructionDefinition mret_ (
 	ISA32_RV64IMACFD,
@@ -37,22 +104,33 @@ static InstructionDefinition mret_ (
 		cp.code() = std::string("//MRET\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < 3) {\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833];\n";
-cp.code() += "etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[768];\n";
-cp.code() += "etiss_uint64 prev_prv = get_field(s, 6144);\n";
-cp.code() += "if (prev_prv != 3L) {\n";
-cp.code() += "s = set_field(s, 131072, 0U);\n";
-cp.code() += "}\n";
-cp.code() += "s = set_field(s, 8, get_field(s, 128));\n";
-cp.code() += "s = set_field(s, 128, 1U);\n";
-cp.code() += "s = set_field(s, 6144, (extension_enabled(cpu, system, plugin_pointers, 85U)) ? (0) : (3));\n";
-cp.code() += "*((RV64IMACFD*)cpu)->CSR[768] = s;\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n";
+cp.code() += "etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 768LL);\n";
+cp.code() += "etiss_uint64 prev_prv = get_field(s, 6144LL);\n";
+cp.code() += "if (prev_prv != 3LL) { // conditional\n";
+cp.code() += "s = set_field(s, 131072LL, 0ULL);\n";
+cp.code() += "} // conditional\n";
+cp.code() += "if (prev_prv != ((RV64IMACFD*)cpu)->PRIV && csr_read(cpu, system, plugin_pointers, 384LL) != 0ULL) { // conditional\n";
+cp.code() += "etiss_icache_flush(cpu, system, plugin_pointers);\n";
+cp.code() += "} // conditional\n";
+cp.code() += "s = set_field(s, 8LL, get_field(s, 128LL));\n";
+cp.code() += "s = set_field(s, 128LL, 1ULL);\n";
+cp.code() += "s = set_field(s, 6144LL, (extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
@@ -85,6 +163,66 @@ ss << "mret" << " # " << ba << (" []");
 	}
 );
 
+// WFI -------------------------------------------------------------------------
+static InstructionDefinition wfi_ (
+	ISA32_RV64IMACFD,
+	"wfi",
+	(uint32_t) 0x10500073,
+	(uint32_t) 0xffffffff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//WFI\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//WFI\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "wfi" << " # " << ba << (" []");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
 // SRET ------------------------------------------------------------------------
 static InstructionDefinition sret_ (
 	ISA32_RV64IMACFD,
@@ -108,19 +246,27 @@ static InstructionDefinition sret_ (
 		cp.code() = std::string("//SRET\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < ((get_field(*((RV64IMACFD*)cpu)->CSR[768], 4194304)) ? (3) : (1))) {\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 2);\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < ((get_field(csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321];\n";
-cp.code() += "etiss_uint64 s = *((RV64IMACFD*)cpu)->CSR[256];\n";
-cp.code() += "etiss_uint64 prev_prv = get_field(s, 256);\n";
-cp.code() += "s = set_field(s, 2, get_field(s, 32));\n";
-cp.code() += "s = set_field(s, 32, 1U);\n";
-cp.code() += "s = set_field(s, 256, 0);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->CSR[768] = s;\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n";
+cp.code() += "etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 256LL);\n";
+cp.code() += "etiss_uint64 prev_prv = get_field(s, 256LL);\n";
+cp.code() += "s = set_field(s, 2LL, get_field(s, 32LL));\n";
+cp.code() += "s = set_field(s, 32LL, 1ULL);\n";
+cp.code() += "s = set_field(s, 256LL, 0LL);\n";
+cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index f8df68b3f4..8123fd5b5a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
@@ -49,24 +49,32 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//LRD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
 cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
-if (rd) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
-}
+if (rd) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -146,27 +154,35 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//SCD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-cp.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+cp.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";
 cp.code() += "etiss_uint64 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-if (rd) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
-}
-cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // conditional\n";
+if (rd) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
+} // conditional
+cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1LL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index 40ba93e2e1..c1424d3a67 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
@@ -49,24 +49,32 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//LRW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
 cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
-if (rd) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = (etiss_int64)(res);\n";
-}
+if (rd) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -146,27 +154,35 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//SCW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "U];\n";
-cp.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
+cp.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "U]);\n";
+cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-if (rd) {
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "U] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
-}
-cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1L;\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
+cp.code() += "} // conditional\n";
+if (rd) { // conditional
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
+} // conditional
+cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1LL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32U], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32U], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32U], 64);
+		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index b088f23676..8967e0696f 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Feb 2023 18:20:18 +0100.
+ * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.
@@ -37,49 +37,89 @@ static InstructionDefinition ebreak_ (
 		cp.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4UL) + "U;\n";
-cp.code() += "if (etiss_semihost_enabled()) {\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "if (etiss_semihost_enabled()) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 mem_val_0;\n";
-cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4UL) + "U, (etiss_uint8*)&mem_val_0, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4ULL) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
 cp.code() += "etiss_uint32 mem_val_1;\n";
-cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0UL) + "U, (etiss_uint8*)&mem_val_1, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0ULL) + "ULL, (etiss_uint8*)&mem_val_1, 4);\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
 cp.code() += "etiss_uint32 mem_val_2;\n";
-cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4UL) + "U, (etiss_uint8*)&mem_val_2, 4);\n";
-cp.code() += "if (cpu->exception) {\n";
+cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4ULL) + "ULL, (etiss_uint8*)&mem_val_2, 4);\n";
+cp.code() += "if (cpu->exception) { // conditional\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
 cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // conditional\n";
 cp.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
-cp.code() += "if (pre == 32509971U && ebreak == 1048691U && post == 1081102355U) {\n";
-cp.code() += "etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10U];\n";
-cp.code() += "etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11U];\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[10U] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64U, operation, parameter));\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3);\n";
+cp.code() += "if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10ULL];\n";
+cp.code() += "etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11ULL];\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[10ULL] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64ULL, operation, parameter));\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
-cp.code() += "}\n";
-cp.code() += "else {\n";
-cp.code() += "cpu->exception = 0; raise(cpu, system, plugin_pointers, 0U, 3);\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "else { // conditional\n";
+{ // block
+cp.code() += "{ // block\n";
+{ // procedure
+cp.code() += "{ // procedure\n";
+cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
-cp.code() += "}\n";
+cp.code() += "} // procedure\n";
+} // procedure
+cp.code() += "} // block\n";
+} // block
+cp.code() += "} // conditional\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[10U], 64);
-		cp.getRegisterDependencies().add(reg_name[11U], 64);
-		cp.getAffectedRegisters().add(reg_name[10U], 64);
+		cp.getRegisterDependencies().add(reg_name[10ULL], 64);
+		cp.getRegisterDependencies().add(reg_name[11ULL], 64);
+		cp.getAffectedRegisters().add(reg_name[10ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -88,7 +128,7 @@ cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 		cp.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + ") return cpu->exception;\n";
+cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
 // -----------------------------------------------------------------------------
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp
new file mode 100644
index 0000000000..f0d767ba53
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp
@@ -0,0 +1,118 @@
+/**
+ * Generated on Wed, 13 Sep 2023 17:04:56 +0200.
+ *
+ * This file contains the instruction behavior models of the tum_sfence
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+
+#define ETISS_ARCH_STATIC_FN_ONLY
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// SFENCE_VMA ------------------------------------------------------------------
+static InstructionDefinition sfence_vma_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"sfence_vma",
+	(uint32_t) 0x12000073,
+	(uint32_t) 0xfe007fff,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//SFENCE_VMA\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "((RV64IMACFD*)cpu)->FENCE[2ULL] = " + std::to_string(rs1) + "ULL;\n";
+cp.code() += "((RV64IMACFD*)cpu)->FENCE[3ULL] = " + std::to_string(rs2) + "ULL;\n";
+cp.code() += "etiss_uint64 vaddr = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "ULL];\n";
+cp.code() += "etiss_uint64 asid = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2) + "ULL];\n";
+if (rs1 == 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+if (rs2 == 0ULL) { // conditional
+cp.code() += "evict_all(cpu, system, plugin_pointers);\n";
+} // conditional
+else { // conditional
+cp.code() += "evict_asid(cpu, system, plugin_pointers, asid);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
+} // conditional
+else { // conditional
+{ // block
+cp.code() += "{ // block\n";
+if (rs2 == 0ULL) { // conditional
+cp.code() += "evict_addr(cpu, system, plugin_pointers, vaddr);\n";
+} // conditional
+else { // conditional
+cp.code() += "evict_addr_asid(cpu, system, plugin_pointers, vaddr, asid);\n";
+} // conditional
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getRegisterDependencies().add(reg_name[rs1], 64);
+		cp.getRegisterDependencies().add(reg_name[rs2], 64);
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+	{
+		CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
+
+		cp.code() = std::string("//SFENCE_VMA\n");
+
+// -----------------------------------------------------------------------------
+cp.code() += "return cpu->exception;\n";
+// -----------------------------------------------------------------------------
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "sfence_vma" << " # " << ba << (" [rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);

From 9de3932b16bb04ada9df462921bec71c05f1ecda Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 19:18:37 +0200
Subject: [PATCH 35/44] Revert "generate error handling pseudo instruction"

This reverts commit 5dc331f81fd1b04f8bdfa07ba193d1ab5819b555.
---
 src/Translation.cpp | 30 +-----------------------------
 1 file changed, 1 insertion(+), 29 deletions(-)

diff --git a/src/Translation.cpp b/src/Translation.cpp
index 686bc55386..9cea220f0a 100644
--- a/src/Translation.cpp
+++ b/src/Translation.cpp
@@ -332,37 +332,9 @@ BlockLink *Translation::getBlock(BlockLink *prev, const etiss::uint64 &instructi
     block.functionglobalCode().push_back("if (cpu->mode != " + toString(cpu_.mode) +
                                       ") return ETISS_RETURNCODE_RELOADCURRENTBLOCK;");
 
-    etiss::int32 transerror = translateBlock(block);
-
-    etiss::instr::InstructionContext err_ctx;
-    etiss::CodeSet err_cs;
-    auto vis = mis_->get(cpu_.mode);
-
-    err_ctx.cf_delay_slot_ = 0;
-    err_ctx.force_block_end_ = false;
-    err_ctx.force_append_next_instr_ = false;
-    err_ctx.force_block_end_ = false;
-    err_ctx.current_address_ = block.endaddress_;
-    err_ctx.current_local_address_ = block.endaddress_ - block.startindex_;
-    err_ctx.instr_width_fully_evaluated_ = true;
-    err_ctx.is_not_default_width_ = false;
-    err_ctx.instr_width_ = vis->width_;
-
-    auto err_ins = &vis->getMain()->getInvalid();
-
-    etiss::instr::BitArray errba(32, 0);
-    errba = etiss::RETURNCODE::ILLEGALINSTRUCTION;
-
-    err_ins->translate(errba, err_cs, err_ctx);
-
-    etiss::RegisterSet dummy;
-    bool err_ok;
-
-    auto err_str = "if (cpu->exception) {\n" + err_cs.toString(dummy, err_ok) + "\n}\n\n";
-
     plugins_initCodeBlock_(plugins_array_, block);
 
-    block.functionglobalCode().insert(block.functionglobalCode().begin(), err_str);
+    etiss::int32 transerror = translateBlock(block);
 
     if (transerror != ETISS_RETURNCODE_NOERROR)
     {

From d7971c8e26ae1857c3f36700daf8ae7e3d64d959 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 19:18:45 +0200
Subject: [PATCH 36/44] Revert "change file/functionglobalcode to vector"

This reverts commit 31758752ec7e5183f9688785bf4f8162937a2c86.
---
 ArchImpl/OR1K/OR1KArch.cpp                                | 4 ++--
 ArchImpl/RISCV/RISCVArch.cpp                              | 2 +-
 ArchImpl/RISCV64/RISCV64Arch.cpp                          | 2 +-
 include/etiss/CodePart.h                                  | 8 ++++----
 src/IntegratedLibrary/InstructionAccurateCallback.cpp     | 2 +-
 .../InstructionSpecificAddressCallback.cpp                | 4 ++--
 src/IntegratedLibrary/PrintInstruction.cpp                | 2 +-
 src/IntegratedLibrary/VariableValueLogger.cpp             | 2 +-
 src/IntegratedLibrary/gdb/GDBServer.cpp                   | 2 +-
 src/Translation.cpp                                       | 6 +++---
 10 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/ArchImpl/OR1K/OR1KArch.cpp b/ArchImpl/OR1K/OR1KArch.cpp
index 32eb84f9e4..f7c2ef9d71 100644
--- a/ArchImpl/OR1K/OR1KArch.cpp
+++ b/ArchImpl/OR1K/OR1KArch.cpp
@@ -389,8 +389,8 @@ void OR1KArch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const
 void OR1KArch::initCodeBlock(etiss::CodeBlock &cb) const
 {
 
-    cb.fileglobalCode().push_back("#include \"Arch/OR1K/OR1K.h\"\n");
-    cb.fileglobalCode().push_back("#include \"etiss/jit/fpu/softfloat.h\"\n");
+    cb.fileglobalCode().insert("#include \"Arch/OR1K/OR1K.h\"\n");
+    cb.fileglobalCode().insert("#include \"etiss/jit/fpu/softfloat.h\"\n");
 }
 
 const std::set<std::string> &OR1KArch::getHeaders() const
diff --git a/ArchImpl/RISCV/RISCVArch.cpp b/ArchImpl/RISCV/RISCVArch.cpp
index 134913e0d1..f359d3394c 100644
--- a/ArchImpl/RISCV/RISCVArch.cpp
+++ b/ArchImpl/RISCV/RISCVArch.cpp
@@ -216,7 +216,7 @@ const std::set<std::string> & RISCVArch::getHeaders() const
 		
 void RISCVArch::initCodeBlock(etiss::CodeBlock & cb) const
 {
-    cb.fileglobalCode().push_back("#include \"Arch/RISCV/RISCV.h\"\n");
+    cb.fileglobalCode().insert("#include \"Arch/RISCV/RISCV.h\"\n");
 }
 
 etiss::plugin::gdb::GDBCore & RISCVArch::getGDBCore()
diff --git a/ArchImpl/RISCV64/RISCV64Arch.cpp b/ArchImpl/RISCV64/RISCV64Arch.cpp
index ae7c15ec69..66864a3021 100644
--- a/ArchImpl/RISCV64/RISCV64Arch.cpp
+++ b/ArchImpl/RISCV64/RISCV64Arch.cpp
@@ -222,7 +222,7 @@ const std::set<std::string> & RISCV64Arch::getHeaders() const
 		
 void RISCV64Arch::initCodeBlock(etiss::CodeBlock & cb) const
 {
-    cb.fileglobalCode().push_back("#include \"Arch/RISCV64/RISCV64.h\"\n");
+    cb.fileglobalCode().insert("#include \"Arch/RISCV64/RISCV64.h\"\n");
 }
 
 etiss::plugin::gdb::GDBCore & RISCV64Arch::getGDBCore()
diff --git a/include/etiss/CodePart.h b/include/etiss/CodePart.h
index af857fccd1..b64e0697ab 100644
--- a/include/etiss/CodePart.h
+++ b/include/etiss/CodePart.h
@@ -600,16 +600,16 @@ class CodeBlock
         return lines_.back();
     }
     inline unsigned length() const { return (unsigned)lines_.size(); }
-    inline std::vector<std::string> &fileglobalCode() { return fileglobal_code; }
-    inline std::vector<std::string> &functionglobalCode() { return functionglobal_code; }
+    inline std::set<std::string> &fileglobalCode() { return fileglobal_code; }
+    inline std::set<std::string> &functionglobalCode() { return functionglobal_code; }
     void toCode(std::stringstream &out, const std::string &funcname, std::set<std::string> *fileglobalcode);
 
   private:
     std::vector<Line> lines_;
     etiss::uint64 startindex_;
     etiss::uint64 endaddress_;
-    std::vector<std::string> fileglobal_code;
-    std::vector<std::string> functionglobal_code;
+    std::set<std::string> fileglobal_code;
+    std::set<std::string> functionglobal_code;
 };
 } // namespace etiss
 #endif
diff --git a/src/IntegratedLibrary/InstructionAccurateCallback.cpp b/src/IntegratedLibrary/InstructionAccurateCallback.cpp
index 668db78ba2..bd07731825 100644
--- a/src/IntegratedLibrary/InstructionAccurateCallback.cpp
+++ b/src/IntegratedLibrary/InstructionAccurateCallback.cpp
@@ -64,7 +64,7 @@ InstructionAccurateCallback::~InstructionAccurateCallback() {}
 
 void InstructionAccurateCallback::initCodeBlock(etiss::CodeBlock &block) const
 {
-    block.fileglobalCode().push_back("extern void etiss_plugin_InstructionAccurateCallback(void *); ");
+    block.fileglobalCode().insert("extern void etiss_plugin_InstructionAccurateCallback(void *); ");
 }
 
 void InstructionAccurateCallback::finalizeInstrSet(etiss::instr::ModedInstructionSet &mis) const
diff --git a/src/IntegratedLibrary/InstructionSpecificAddressCallback.cpp b/src/IntegratedLibrary/InstructionSpecificAddressCallback.cpp
index dc55bf2cc6..e130b971f8 100644
--- a/src/IntegratedLibrary/InstructionSpecificAddressCallback.cpp
+++ b/src/IntegratedLibrary/InstructionSpecificAddressCallback.cpp
@@ -84,8 +84,8 @@ InstructionSpecificAddressCallback::~InstructionSpecificAddressCallback() {}
 
 void InstructionSpecificAddressCallback::initCodeBlock(etiss::CodeBlock &block) const
 {
-    block.fileglobalCode().push_back("extern int InstructionSpecificAddressCallback_callback(void *);\n");
-    block.functionglobalCode().push_back("  if ( (*(uint32_t*)(" + getPointerCode() +
+    block.fileglobalCode().insert("extern int InstructionSpecificAddressCallback_callback(void *);\n");
+    block.functionglobalCode().insert("  if ( (*(uint32_t*)(" + getPointerCode() +
                                       ")) != " + etiss::toString(pluginData_.state_) +
                                       ") return ETISS_RETURNCODE_RELOADCURRENTBLOCK;\n"); // add print function
 }
diff --git a/src/IntegratedLibrary/PrintInstruction.cpp b/src/IntegratedLibrary/PrintInstruction.cpp
index f851d744f4..1e22ad61ff 100644
--- a/src/IntegratedLibrary/PrintInstruction.cpp
+++ b/src/IntegratedLibrary/PrintInstruction.cpp
@@ -62,7 +62,7 @@ using namespace etiss::plugin;
 
 void PrintInstruction::initCodeBlock(etiss::CodeBlock &block) const
 {
-    block.fileglobalCode().push_back("extern void PrintInstruction_print(const char *,uint64_t);"); // add print function
+    block.fileglobalCode().insert("extern void PrintInstruction_print(const char *,uint64_t);"); // add print function
 }
 
 void PrintInstruction::finalizeInstrSet(etiss::instr::ModedInstructionSet &mis) const
diff --git a/src/IntegratedLibrary/VariableValueLogger.cpp b/src/IntegratedLibrary/VariableValueLogger.cpp
index eaa5c35e78..9d64ba1927 100644
--- a/src/IntegratedLibrary/VariableValueLogger.cpp
+++ b/src/IntegratedLibrary/VariableValueLogger.cpp
@@ -76,7 +76,7 @@ VariableValueLogger::VariableValueLogger(
 
 void VariableValueLogger::initCodeBlock(etiss::CodeBlock &block) const
 {
-    block.fileglobalCode().push_back("extern void etiss_plugin_VariableValueLogger(void *); ");
+    block.fileglobalCode().insert("extern void etiss_plugin_VariableValueLogger(void *); ");
 }
 
 void VariableValueLogger::finalizeInstrSet(etiss::instr::ModedInstructionSet &mis) const
diff --git a/src/IntegratedLibrary/gdb/GDBServer.cpp b/src/IntegratedLibrary/gdb/GDBServer.cpp
index 0f903d2679..f706a1246d 100644
--- a/src/IntegratedLibrary/gdb/GDBServer.cpp
+++ b/src/IntegratedLibrary/gdb/GDBServer.cpp
@@ -277,7 +277,7 @@ void Server::finalizeInstrSet(etiss::instr::ModedInstructionSet &mis) const
 void Server::finalizeCodeBlock(etiss::CodeBlock &cb) const
 {
 
-    cb.fileglobalCode().push_back("extern etiss_int32 gdb_pre_instruction(ETISS_CPU * ,ETISS_System * ,void * );extern "
+    cb.fileglobalCode().insert("extern etiss_int32 gdb_pre_instruction(ETISS_CPU * ,ETISS_System * ,void * );extern "
                                "void gdb_pre_instruction_noreturn(ETISS_CPU * ,ETISS_System * ,void * );");
 }
 
diff --git a/src/Translation.cpp b/src/Translation.cpp
index 9cea220f0a..8d726b2607 100644
--- a/src/Translation.cpp
+++ b/src/Translation.cpp
@@ -318,7 +318,7 @@ BlockLink *Translation::getBlock(BlockLink *prev, const etiss::uint64 &instructi
     }
 
     CodeBlock block(instructionindex);
-    block.fileglobalCode().push_back("#include \"etiss/jit/CPU.h\"\n"
+    block.fileglobalCode().insert("#include \"etiss/jit/CPU.h\"\n"
                                   "#include \"etiss/jit/System.h\"\n"
                                   "#include \"etiss/jit/libresources.h\"\n"
                                   "#include \"etiss/jit/libsemihost.h\"\n"
@@ -326,10 +326,10 @@ BlockLink *Translation::getBlock(BlockLink *prev, const etiss::uint64 &instructi
                                   "#include \"etiss/jit/libCSRCounters.h\"\n");
 
     for(auto &it: jitExtHeaders()){
-        if(it != "") block.fileglobalCode().push_back("#include \"" + it + "\"\n");
+        if(it != "") block.fileglobalCode().insert("#include \"" + it + "\"\n");
     }
 
-    block.functionglobalCode().push_back("if (cpu->mode != " + toString(cpu_.mode) +
+    block.functionglobalCode().insert("if (cpu->mode != " + toString(cpu_.mode) +
                                       ") return ETISS_RETURNCODE_RELOADCURRENTBLOCK;");
 
     plugins_initCodeBlock_(plugins_array_, block);

From 61422e72768bbd1a56dec84cf22744e1ef283783 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 29 Sep 2023 19:23:05 +0200
Subject: [PATCH 37/44] update architecture

---
 ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp | 10 +++++-----
 ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
index 23d75ee4d5..fc3a70a5b1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -206,11 +206,11 @@ const std::set<std::string> & RV32IMACFDArch::getHeaders() const
 
 void RV32IMACFDArch::initCodeBlock(etiss::CodeBlock & cb) const
 {
-	cb.fileglobalCode().push_back("#include \"Arch/RV32IMACFD/RV32IMACFD.h\"\n");
-	cb.fileglobalCode().push_back("#include \"Arch/RV32IMACFD/RV32IMACFDFuncs.h\"\n");
-	cb.functionglobalCode().push_back("cpu->exception = 0;\n");
-	cb.functionglobalCode().push_back("cpu->return_pending = 0;\n");
-	cb.functionglobalCode().push_back("etiss_uint32 mem_ret_code = 0;\n");
+	cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFD.h\"\n");
+	cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFDFuncs.h\"\n");
+	cb.functionglobalCode().insert("cpu->exception = 0;\n");
+	cb.functionglobalCode().insert("cpu->return_pending = 0;\n");
+	cb.functionglobalCode().insert("etiss_uint32 mem_ret_code = 0;\n");
 }
 
 etiss::plugin::gdb::GDBCore & RV32IMACFDArch::getGDBCore()
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
index fdb31b5e21..f5fc2d6905 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
@@ -206,11 +206,11 @@ const std::set<std::string> & RV64IMACFDArch::getHeaders() const
 
 void RV64IMACFDArch::initCodeBlock(etiss::CodeBlock & cb) const
 {
-	cb.fileglobalCode().push_back("#include \"Arch/RV64IMACFD/RV64IMACFD.h\"\n");
-	cb.fileglobalCode().push_back("#include \"Arch/RV64IMACFD/RV64IMACFDFuncs.h\"\n");
-	cb.functionglobalCode().push_back("cpu->exception = 0;\n");
-	cb.functionglobalCode().push_back("cpu->return_pending = 0;\n");
-	cb.functionglobalCode().push_back("etiss_uint32 mem_ret_code = 0;\n");
+	cb.fileglobalCode().insert("#include \"Arch/RV64IMACFD/RV64IMACFD.h\"\n");
+	cb.fileglobalCode().insert("#include \"Arch/RV64IMACFD/RV64IMACFDFuncs.h\"\n");
+	cb.functionglobalCode().insert("cpu->exception = 0;\n");
+	cb.functionglobalCode().insert("cpu->return_pending = 0;\n");
+	cb.functionglobalCode().insert("etiss_uint32 mem_ret_code = 0;\n");
 }
 
 etiss::plugin::gdb::GDBCore & RV64IMACFDArch::getGDBCore()

From 2597630e1b568bd5a533db0a964082a4693fb0b0 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Mon, 2 Oct 2023 17:47:15 +0200
Subject: [PATCH 38/44] update architectures, fix rounding mode

---
 ArchImpl/RV32IMACFD/CMakeLists.txt            |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD.h              |  5 ++++-
 ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp        | 10 ++++++++--
 ArchImpl/RV32IMACFD/RV32IMACFDArch.h          |  6 +++---
 ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp     |  2 +-
 .../RV32IMACFD/RV32IMACFDArchSpecificImp.cpp  | 17 +++-------------
 .../RV32IMACFD/RV32IMACFDArchSpecificImp.h    |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         | 19 ++++++++++++++++--
 ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h       |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp       |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp |  2 +-
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp | 20 +++++++++----------
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp | 20 +++++++++----------
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp |  2 +-
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |  2 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    |  2 +-
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    |  2 +-
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |  2 +-
 .../RV32IMACFD_tum_semihostingInstr.cpp       |  2 +-
 ArchImpl/RV64IMACFD/CMakeLists.txt            |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD.h              |  5 ++++-
 ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp        |  8 +++++++-
 ArchImpl/RV64IMACFD/RV64IMACFDArch.h          |  7 ++++---
 ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp     |  2 +-
 .../RV64IMACFD/RV64IMACFDArchSpecificImp.cpp  | 10 +++-------
 .../RV64IMACFD/RV64IMACFDArchSpecificImp.h    |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h         | 19 ++++++++++++++++--
 ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h       |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp       |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp |  2 +-
 .../RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp     |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp | 20 +++++++++----------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp | 20 +++++++++----------
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp |  2 +-
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp |  2 +-
 .../RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp   |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_retInstr.cpp    |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp  |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp    |  2 +-
 .../RV64IMACFD_tum_semihostingInstr.cpp       |  2 +-
 52 files changed, 148 insertions(+), 114 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index 81bb6cd154..81758ec16a 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+# Generated on Mon, 02 Oct 2023 17:35:59 +0200.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD.h b/ArchImpl/RV32IMACFD/RV32IMACFD.h
index c4c8c11cfb..da20647610 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 07 Jun 2022 14:20:49 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the registers for the RV32IMACFD core architecture.
  */
@@ -54,6 +54,9 @@ struct RV32IMACFD {
 	etiss_uint8 PRIV;
 	etiss_uint32 DPC;
 	etiss_uint32 FCSR;
+	etiss_uint32 MSTATUS;
+	etiss_uint32 MIE;
+	etiss_uint32 MIP;
 	etiss_uint32 *CSR[4096];
 	etiss_uint32 ins_CSR[4096];
 	etiss_uint64 F[32];
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
index fc3a70a5b1..1ce16b9873 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 30 Jun 2022 19:52:53 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
@@ -123,6 +123,9 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
 	rv32imacfdcpu->PRIV = 0;
 	rv32imacfdcpu->DPC = 0;
 	rv32imacfdcpu->FCSR = 0;
+	rv32imacfdcpu->MSTATUS = 0;
+	rv32imacfdcpu->MIE = 0;
+	rv32imacfdcpu->MIP = 0;
 	for (int i = 0; i < 32; ++i) {
 		rv32imacfdcpu->F[i] = 0;
 	}
@@ -161,6 +164,9 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
  	rv32imacfdcpu->X[30] = &rv32imacfdcpu->T5;
  	rv32imacfdcpu->X[31] = &rv32imacfdcpu->T6;
  	rv32imacfdcpu->CSR[3] = &rv32imacfdcpu->FCSR;
+ 	rv32imacfdcpu->CSR[768] = &rv32imacfdcpu->MSTATUS;
+ 	rv32imacfdcpu->CSR[772] = &rv32imacfdcpu->MIE;
+ 	rv32imacfdcpu->CSR[836] = &rv32imacfdcpu->MIP;
 
  	rv32imacfdcpu->PRIV = 3;
  	rv32imacfdcpu->DPC = 0;
@@ -259,4 +265,4 @@ etiss::instr::InstructionClass ISA16_RV32IMACFDClass(1, "ISA16_RV32IMACFD", 16,
 etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32);
 etiss::instr::InstructionClass ISA32_RV32IMACFDClass(1, "ISA32_RV32IMACFD", 32, ISA32_RV32IMACFD);
 
-etiss::instr::InstructionCollection RV32IMACFDISA("RV32IMACFDISA", ISA16_RV32IMACFDClass, ISA32_RV32IMACFDClass);
+etiss::instr::InstructionCollection RV32IMACFDISA("RV32IMACFDISA", ISA16_RV32IMACFDClass, ISA32_RV32IMACFDClass);
\ No newline at end of file
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
index 7a772400d4..b16dc782f1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
@@ -90,8 +90,8 @@ class RV32IMACFDArch : public etiss::CPUArch {
 	*/
 	virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU * cpu);
 	virtual void deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu);
-    virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu);
-    virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu);
+	virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu);
+	virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu);
 
 	/**
 		@brief get the GDBcore for RV32IMACFD architecture
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
index 6f4070df85..7e3c4fdbea 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the library interface for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
index 79518de26b..8b1e496118 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -347,20 +347,11 @@ etiss::InterruptVector * RV32IMACFDArch::createInterruptVector(ETISS_CPU * cpu)
 	if (cpu == 0)
 		return 0;
 
-	/**************************************************************************
-	*		            Implementation of interrupt vector              	  *
-	***************************************************************************/
-
-	// This is a default vector, implemented to avoid segfaults. Replace
-	// with actual implementation if necessary.
-
 	std::vector<etiss::uint32 *> vec;
 	std::vector<etiss::uint32 *> mask;
 
-	RV32IMACFD* rvcpu = (RV32IMACFD*)cpu;
-
-	vec.push_back(rvcpu->CSR[0x344]);
-	mask.push_back(rvcpu->CSR[0x304]);
+	vec.push_back(&((RV32IMACFD*)cpu)->MIE);
+	mask.push_back(&((RV32IMACFD*)cpu)->MIP);
 
 	return new etiss::MappedInterruptVector<etiss::uint32>(vec, mask);
 }
@@ -371,9 +362,7 @@ void RV32IMACFDArch::deleteInterruptVector(etiss::InterruptVector * vec, ETISS_C
 }
 
 etiss::InterruptEnable* RV32IMACFDArch::createInterruptEnable(ETISS_CPU* cpu) {
-	RV32IMACFD* rvcpu = (RV32IMACFD*)cpu;
-
-	return new etiss::MappedInterruptEnable<etiss::uint32>(rvcpu->CSR[0x300], 0xf);
+ 	return new etiss::MappedInterruptEnable<etiss::uint32>(&((RV32IMACFD*)cpu)->MSTATUS, 15);
 }
 
 void RV32IMACFDArch::deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu) {
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
index 18b89bed60..68ec2941f8 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the architecture specific header for the RV32IMACFD
  * core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index 6606c8bfa3..f0877dd09c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 29 Sep 2023 16:41:15 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -50,6 +50,8 @@ extern etiss_uint32 fclass_s(etiss_uint32);
 
 extern etiss_uint32 fget_flags();
 
+static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
+
 extern etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
 extern etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
@@ -119,6 +121,19 @@ return (*((RV32IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
 } // block
 }
 
+static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
+{
+{ // block
+if (rm == 7ULL) { // conditional
+rm = ((((((RV32IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7;
+} // conditional
+if (rm > 4ULL) { // conditional
+raise(cpu, system, plugin_pointers, 0ULL, 2LL);
+} // conditional
+return rm;
+} // block
+}
+
 static inline etiss_uint32 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
 {
 { // block
@@ -290,7 +305,7 @@ etiss_int32 irq2 = (mcause & 2147483648ULL) != 0ULL;
 if (irq2) { // conditional
 { // block
 deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[771LL]) : (0ULL);
-bit = bit & -2147483649LL;
+bit = bit & 2147483647ULL;
 } // block
 } // conditional
 else { // conditional
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
index e285113550..2ab06c756d 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the GDBCore adapter for the RV32IMACFD core architecture.
  *
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
index 4a7b6f153c..8fdc4ad2f7 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 16 Nov 2022 11:39:01 +0100.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index ff1f96b480..2c528b65c4 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:47:58 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index 77b997805d..1946b7073c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index 91f090175f..d43a965e28 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -242,7 +242,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -327,7 +327,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -412,7 +412,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -497,7 +497,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -579,7 +579,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -658,7 +658,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -737,7 +737,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -816,7 +816,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -892,7 +892,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index b9802a9911..4c0aeff3e9 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 542e310267..91c2c744d3 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -248,7 +248,7 @@ cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "UL
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -337,7 +337,7 @@ cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "UL
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -429,7 +429,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -521,7 +521,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -609,7 +609,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -694,7 +694,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -779,7 +779,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -864,7 +864,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -945,7 +945,7 @@ cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fsqrt_s(frs1, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index 51d9fdf35f..963db9e17d 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 001772bc09..13bcf30d98 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 25 Sep 2023 14:27:10 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index e0bea58d8c..4e53092361 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index e0797c97e0..72b197e8ee 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index 59e6210750..9030b87f84 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index e6cfe0c4d0..2a7bdadb71 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 25 Sep 2023 14:27:10 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 15fe6ba0ec..88ad6130af 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index 4067f19b1a..f34f5a9ddb 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 19 Sep 2023 16:07:36 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt
index 2c7bc4654f..0a0daa11f3 100644
--- a/ArchImpl/RV64IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV64IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Wed, 13 Sep 2023 20:22:42 +0200.
+# Generated on Mon, 02 Oct 2023 17:35:59 +0200.
 #
 # This file contains the CMake build info for the RV64IMACFD core architecture.
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD.h b/ArchImpl/RV64IMACFD/RV64IMACFD.h
index 46e160dd3a..22b49ee4c5 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the registers for the RV64IMACFD core architecture.
  */
@@ -54,6 +54,9 @@ struct RV64IMACFD {
 	etiss_uint8 PRIV;
 	etiss_uint64 DPC;
 	etiss_uint64 FCSR;
+	etiss_uint64 MSTATUS;
+	etiss_uint64 MIE;
+	etiss_uint64 MIP;
 	etiss_uint64 *CSR[4096];
 	etiss_uint64 ins_CSR[4096];
 	etiss_uint64 F[32];
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
index f5fc2d6905..9f350a6a7a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */
@@ -123,6 +123,9 @@ void RV64IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
 	rv64imacfdcpu->PRIV = 0;
 	rv64imacfdcpu->DPC = 0;
 	rv64imacfdcpu->FCSR = 0;
+	rv64imacfdcpu->MSTATUS = 0;
+	rv64imacfdcpu->MIE = 0;
+	rv64imacfdcpu->MIP = 0;
 	for (int i = 0; i < 32; ++i) {
 		rv64imacfdcpu->F[i] = 0;
 	}
@@ -161,6 +164,9 @@ void RV64IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
  	rv64imacfdcpu->X[30] = &rv64imacfdcpu->T5;
  	rv64imacfdcpu->X[31] = &rv64imacfdcpu->T6;
  	rv64imacfdcpu->CSR[3] = &rv64imacfdcpu->FCSR;
+ 	rv64imacfdcpu->CSR[768] = &rv64imacfdcpu->MSTATUS;
+ 	rv64imacfdcpu->CSR[772] = &rv64imacfdcpu->MIE;
+ 	rv64imacfdcpu->CSR[836] = &rv64imacfdcpu->MIP;
 
  	rv64imacfdcpu->PRIV = 3;
  	rv64imacfdcpu->DPC = 0;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
index 13b4b9f8e2..e65824ea48 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */
@@ -90,8 +90,9 @@ class RV64IMACFDArch : public etiss::CPUArch {
 	*/
 	virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU * cpu);
 	virtual void deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu);
-    virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu);
-    virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu);
+	virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu);
+	virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu);
+
 	/**
 		@brief get the GDBcore for RV64IMACFD architecture
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
index 3a7e52fc2e..d0fb04998c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the library interface for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
index f569075400..22aa33c62e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -356,10 +356,8 @@ etiss::InterruptVector * RV64IMACFDArch::createInterruptVector(ETISS_CPU * cpu)
 	std::vector<etiss::uint64 *> vec;
 	std::vector<etiss::uint64 *> mask;
 
-	RV64IMACFD* rvcpu = (RV64IMACFD*)cpu;
-
-	vec.push_back(rvcpu->CSR[0x344]);
-	mask.push_back(rvcpu->CSR[0x304]);
+	vec.push_back(&((RV64IMACFD*)cpu)->MIE);
+	mask.push_back(&((RV64IMACFD*)cpu)->MIP);
 
 	return new etiss::MappedInterruptVector<etiss::uint64>(vec, mask);
 }
@@ -370,9 +368,7 @@ void RV64IMACFDArch::deleteInterruptVector(etiss::InterruptVector * vec, ETISS_C
 }
 
 etiss::InterruptEnable* RV64IMACFDArch::createInterruptEnable(ETISS_CPU* cpu) {
-	RV64IMACFD* rvcpu = (RV64IMACFD*)cpu;
-
-	return new etiss::MappedInterruptEnable<etiss::uint64>(rvcpu->CSR[0x300], 0xf);
+ 	return new etiss::MappedInterruptEnable<etiss::uint64>(&((RV64IMACFD*)cpu)->MSTATUS, 15);
 }
 
 void RV64IMACFDArch::deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu) {
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
index dda86f3a55..bb61204921 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 12 Oct 2022 12:54:05 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the architecture specific header for the RV64IMACFD
  * core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index a607eaa47e..a278bcc85b 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 28 Sep 2023 00:51:23 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the function macros for the RV64IMACFD core architecture.
  */
@@ -50,6 +50,8 @@ extern etiss_uint32 fclass_s(etiss_uint32);
 
 extern etiss_uint32 fget_flags();
 
+static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
+
 extern etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
 extern etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
@@ -119,6 +121,19 @@ return (*((RV64IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
 } // block
 }
 
+static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
+{
+{ // block
+if (rm == 7ULL) { // conditional
+rm = ((((((RV64IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7;
+} // conditional
+if (rm > 4ULL) { // conditional
+raise(cpu, system, plugin_pointers, 0ULL, 2LL);
+} // conditional
+return rm;
+} // block
+}
+
 static inline etiss_uint64 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
 {
 { // block
@@ -290,7 +305,7 @@ etiss_int32 irq2 = (mcause & 9223372036854775808ULL) != 0ULL;
 if (irq2) { // conditional
 { // block
 deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[771LL]) : (0ULL);
-bit = bit & -9223372036854775809LL;
+bit = bit & 9223372036854775807ULL;
 } // block
 } // conditional
 else { // conditional
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
index 6c526672a8..3bd94d3508 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the GDBCore adapter for the RV64IMACFD core architecture.
  *
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
index 20c12ab196..0ffb7fabe3 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 05 Dec 2022 22:18:34 +0100.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index a7627c0cad..4b144de211 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index 914491c2eb..3ef72ff241 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index 435f4f7a09..f31a426a04 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
@@ -242,7 +242,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -327,7 +327,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -412,7 +412,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -497,7 +497,7 @@ rs3 += R_rs3_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -579,7 +579,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -658,7 +658,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -737,7 +737,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -816,7 +816,7 @@ rs2 += R_rs2_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -892,7 +892,7 @@ rs1 += R_rs1_0.read(ba) << 0;
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index cc75889376..71bc6c0490 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
@@ -248,7 +248,7 @@ cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "UL
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -337,7 +337,7 @@ cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "UL
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -429,7 +429,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -521,7 +521,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -609,7 +609,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -694,7 +694,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -779,7 +779,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -864,7 +864,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -945,7 +945,7 @@ cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7ULL) + "ULL) ? (" + std::to_string(rm) + "ULL) : ((etiss_uint8)(((RV64IMACFD*)cpu)->FCSR)));\n";
+cp.code() += "etiss_uint32 res = fsqrt_s(frs1, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index 18815d89dd..b2d31f8fba 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index a69a65aef4..af9fc6da37 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index db675bbfca..f955c487d9 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index f1e371cdaa..17e77805f4 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index 526178367f..12ce2be11e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index 1bdcd948fb..1de29f3eb6 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index 617e490e9c..e40d21216d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index 08b964c4d5..96eb8e3c6b 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index 7f1a4ba236..946009feba 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index dff65a8b8d..7817a84209 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index cdf35fc34a..6e3cc03f8e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index f75abdc562..c8ec27a368 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index 8123fd5b5a..f7fd43ee15 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index c1424d3a67..9cd99e0fa6 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index 8967e0696f..bc1b776fb1 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 26 Sep 2023 16:46:14 +0200.
+ * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.

From 962df67556eb39255fd2d22bfae825c9b8cd08c3 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Mon, 2 Oct 2023 18:39:55 +0200
Subject: [PATCH 39/44] update architectures

---
 .../RV32IMACFD/RV32IMACFDArchSpecificImp.cpp  |   4 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp |  56 ++++-
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     |  26 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp | 158 ++++++++++--
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     |  26 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp | 158 ++++++++++--
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 182 +++++++++++---
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 230 +++++++++++++++---
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp |  50 +++-
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |   8 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    |  38 ++-
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    |  25 +-
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |  14 +-
 .../RV32IMACFD_tum_semihostingInstr.cpp       |   8 +-
 .../RV64IMACFD/RV64IMACFDArchSpecificImp.cpp  |  11 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp |  56 ++++-
 .../RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp     |  26 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp | 158 ++++++++++--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp | 158 ++++++++++--
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     | 176 +++++++++++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp | 230 +++++++++++++++---
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp |  50 +++-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp |  56 ++++-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp |  38 ++-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp |  26 +-
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     |  62 ++++-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp |  92 +++++--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp |  32 ++-
 .../RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp   |   8 +-
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    |  38 ++-
 .../RV64IMACFD/RV64IMACFD_tum_retInstr.cpp    |  25 +-
 .../RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp  |  14 +-
 .../RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp    |  14 +-
 .../RV64IMACFD_tum_semihostingInstr.cpp       |   8 +-
 34 files changed, 1854 insertions(+), 407 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
index 8b1e496118..100d8bc3fd 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -126,7 +126,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, (cpu->exception) ? (cpu->exception) : (" + std::to_string(error_code) + "ULL));\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -173,7 +173,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, (cpu->exception) ? (cpu->exception) : (" + std::to_string(error_code) + "ULL));\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index 2c528b65c4..d08cab2180 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -52,7 +52,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOSWAPW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -170,7 +174,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOADDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -290,7 +298,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOXORW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -410,7 +422,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOANDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -530,7 +546,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOORW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -650,7 +670,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMINW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -770,7 +794,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -890,7 +918,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMINUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -1010,7 +1042,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index 1946b7073c..a9223c162a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -48,7 +48,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFLD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -144,7 +148,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFSD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -238,7 +246,11 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CFLDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -330,7 +342,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFSDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index d43a965e28..676b53aa6b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -46,7 +46,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//FLD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -140,7 +144,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//FSD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -239,7 +247,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -324,7 +336,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -409,7 +425,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -494,7 +514,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -576,7 +600,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -655,7 +683,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -734,7 +766,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMUL_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -813,7 +849,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FDIV_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -889,7 +929,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FSQRT_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -962,7 +1006,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJ_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n";
@@ -1033,7 +1081,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJN_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n";
@@ -1104,7 +1156,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJX_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) & 9223372036854775808ULL);\n";
@@ -1175,7 +1231,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMIN_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 0ULL);\n";
@@ -1248,7 +1308,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMAX_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 1ULL);\n";
@@ -1321,7 +1385,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], " + std::to_string(rm) + "ULL);\n";
@@ -1392,7 +1460,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), " + std::to_string(rm) + "ULL);\n";
@@ -1467,7 +1539,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FEQ_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = 0ULL;\n";
@@ -1544,7 +1620,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLT_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = 0ULL;\n";
@@ -1621,7 +1701,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLE_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = 0ULL;\n";
@@ -1695,7 +1779,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCLASS_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
@@ -1763,7 +1851,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_W_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_int32 res = 0ULL;\n";
@@ -1840,7 +1932,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_WU_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1917,7 +2013,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
@@ -1989,7 +2089,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_WU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 4c0aeff3e9..91555dca84 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -50,7 +50,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -154,7 +158,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFSW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -250,7 +258,11 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CFLWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -346,7 +358,11 @@ uimm += R_uimm_2.read(ba) << 2;
 		cp.code() = std::string("//CFSWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 91c2c744d3..5098a12777 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -46,7 +46,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//FLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -144,7 +148,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//FSW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -243,7 +251,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -332,7 +344,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -421,7 +437,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -513,7 +533,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -602,7 +626,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -687,7 +715,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -772,7 +804,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMUL_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -857,7 +893,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FDIV_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -939,7 +979,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FSQRT_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1017,7 +1061,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJ_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1094,7 +1142,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJN_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1171,7 +1223,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJX_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1248,7 +1304,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMIN_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1327,7 +1387,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMAX_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1406,7 +1470,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_W_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_int32 res = 0ULL;\n";
@@ -1488,7 +1556,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_WU_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1570,7 +1642,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FEQ_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1653,7 +1729,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLT_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1736,7 +1816,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLE_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1816,7 +1900,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCLASS_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1888,7 +1976,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1964,7 +2056,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_WU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -2037,7 +2133,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_X_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -2104,7 +2204,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_W_X\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index 963db9e17d..35213500f1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -49,7 +49,11 @@ imm += R_imm_4.read(ba) << 4;
 		cp.code() = std::string("//CADDI4SPN\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if (imm) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(imm) + "ULL;\n";
 } // conditional
@@ -143,7 +147,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -243,7 +251,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CSW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -338,7 +350,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CADDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rs1 % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
 } // conditional
@@ -403,7 +419,11 @@ nzimm += R_nzimm_5.read(ba) << 5;
 		cp.code() = std::string("//CNOP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "} // block\n";
@@ -476,7 +496,11 @@ imm += R_imm_11.read(ba) << 11;
 		cp.code() = std::string("//CJAL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV32IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
@@ -564,7 +588,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -635,7 +663,11 @@ imm += R_imm_17.read(ba) << 17;
 		cp.code() = std::string("//CLUI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if (imm == 0ULL) { // conditional
@@ -726,7 +758,11 @@ nzimm += R_nzimm_9.read(ba) << 9;
 		cp.code() = std::string("//CADDI16SP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if (nzimm) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[2ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)nzimm) << (6)) >> (6))) + "LL;\n";
 } // conditional
@@ -809,7 +845,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//__reserved_clui\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // procedure
 cp.code() += "{ // procedure\n";
 cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
@@ -880,7 +920,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
@@ -946,7 +990,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if (shamt) { // conditional
@@ -1020,7 +1068,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CANDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] & " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
@@ -1088,7 +1140,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CSUB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
@@ -1155,7 +1211,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CXOR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
@@ -1222,7 +1282,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//COR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
@@ -1289,7 +1353,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CAND\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
@@ -1367,7 +1435,11 @@ imm += R_imm_11.read(ba) << 11;
 		cp.code() = std::string("//CJ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1455,7 +1527,11 @@ imm += R_imm_8.read(ba) << 8;
 		cp.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] == 0ULL) { // conditional\n";
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
 cp.code() += "} // conditional\n";
@@ -1543,7 +1619,11 @@ imm += R_imm_8.read(ba) << 8;
 		cp.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] != 0ULL) { // conditional\n";
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
 cp.code() += "} // conditional\n";
@@ -1623,7 +1703,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if (nzuimm) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(nzuimm) + "ULL;\n";
 } // conditional
@@ -1691,7 +1775,11 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CLWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if (rd % 32ULL) { // conditional
@@ -1794,7 +1882,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CMV\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -1855,7 +1947,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CJR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if (rs1) { // conditional
 cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & -2LL;\n";
 } // conditional
@@ -1926,7 +2022,11 @@ static InstructionDefinition __reserved_cmv_ (
 		cp.code() = std::string("//__reserved_cmv\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // procedure
 cp.code() += "{ // procedure\n";
 cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
@@ -1994,7 +2094,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CADD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -2056,7 +2160,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CJALR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -2124,7 +2232,11 @@ static InstructionDefinition cebreak_ (
 		cp.code() = std::string("//CEBREAK\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // procedure
 cp.code() += "{ // procedure\n";
 cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
@@ -2194,7 +2306,11 @@ uimm += R_uimm_2.read(ba) << 2;
 		cp.code() = std::string("//CSWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -2276,7 +2392,11 @@ static InstructionDefinition dii_ (
 		cp.code() = std::string("//DII\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // procedure
 cp.code() += "{ // procedure\n";
 cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 13bcf30d98..0b3bce3068 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -43,7 +43,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//LUI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string((etiss_uint32)(((etiss_int32)(imm)))) + "ULL;\n";
 } // conditional
@@ -106,7 +110,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//AUIPC\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + "LL;\n";
 } // conditional
@@ -175,7 +183,11 @@ imm += R_imm_20.read(ba) << 20;
 		cp.code() = std::string("//JAL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if (imm % 2ULL) { // conditional
@@ -279,7 +291,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//JALR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL) & -2LL;\n";
@@ -388,7 +404,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
@@ -505,7 +525,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
@@ -622,7 +646,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
@@ -739,7 +767,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
@@ -856,7 +888,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
@@ -973,7 +1009,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
@@ -1084,7 +1124,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1179,7 +1223,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1274,7 +1322,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1369,7 +1421,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LBU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1464,7 +1520,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LHU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1561,7 +1621,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1657,7 +1721,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1753,7 +1821,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1847,7 +1919,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ADDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 } // conditional
@@ -1917,7 +1993,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//SLTI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL)) ? (1ULL) : (0ULL);\n";
 } // conditional
@@ -1987,7 +2067,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//SLTIU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL)) ? (1ULL) : (0ULL);\n";
 } // conditional
@@ -2057,7 +2141,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//XORI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
 } // conditional
@@ -2127,7 +2215,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ORI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
 } // conditional
@@ -2197,7 +2289,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ANDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
 } // conditional
@@ -2267,7 +2363,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
 } // conditional
@@ -2337,7 +2437,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
 } // conditional
@@ -2407,7 +2511,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> " + std::to_string(shamt) + "ULL;\n";
 } // conditional
@@ -2477,7 +2585,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//ADD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -2548,7 +2660,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SUB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -2619,7 +2735,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n";
 } // conditional
@@ -2690,7 +2810,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLT\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (1ULL) : (0ULL);\n";
 } // conditional
@@ -2761,7 +2885,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLTU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (1ULL) : (0ULL);\n";
 } // conditional
@@ -2832,7 +2960,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//XOR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -2903,7 +3035,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n";
 } // conditional
@@ -2974,7 +3110,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRA\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n";
 } // conditional
@@ -3045,7 +3185,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//OR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -3116,7 +3260,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//AND\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -3193,7 +3341,11 @@ fm += R_fm_0.read(ba) << 0;
 		cp.code() = std::string("//FENCE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "((RV32IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index 4e53092361..b53c36b44f 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
@@ -46,7 +46,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MUL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -126,7 +130,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -206,7 +214,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULHSU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -286,7 +298,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULHU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -366,7 +382,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIV\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -460,7 +480,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIVU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -544,7 +568,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REM\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -638,7 +666,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REMU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index 72b197e8ee..334df36196 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
@@ -47,7 +47,11 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "((RV32IMACFD*)cpu)->FENCE[1ULL] = " + std::to_string(imm) + "ULL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index 9030b87f84..0d19b4f23b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
@@ -46,7 +46,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -134,7 +138,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRS\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
@@ -213,7 +221,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRC\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
@@ -292,7 +304,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRWI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
@@ -367,7 +383,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRSI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
@@ -444,7 +464,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRCI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 2a7bdadb71..858ff8caec 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
@@ -37,10 +37,13 @@ static InstructionDefinition ecall_ (
 		cp.code() = std::string("//ECALL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+{ // block
+cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
 cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n";
@@ -104,7 +107,11 @@ static InstructionDefinition mret_ (
 		cp.code() = std::string("//MRET\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
@@ -186,7 +193,11 @@ static InstructionDefinition wfi_ (
 		cp.code() = std::string("//WFI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "} // block\n";
@@ -246,7 +257,11 @@ static InstructionDefinition sret_ (
 		cp.code() = std::string("//SRET\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((get_field(csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 88ad6130af..eb58af84ed 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -49,7 +49,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//LRW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -154,7 +158,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//SCW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index f34f5a9ddb..a410cf4178 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
@@ -37,7 +37,11 @@ static InstructionDefinition ebreak_ (
 		cp.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (etiss_semihost_enabled()) { // conditional\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
index 22aa33c62e..29ce558a57 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -125,7 +125,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, (cpu->exception) ? (cpu->exception) : (" + std::to_string(error_code) + "ULL));\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -172,7 +172,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, (cpu->exception) ? (cpu->exception) : (" + std::to_string(error_code) + "ULL));\n";
+cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -346,13 +346,6 @@ etiss::InterruptVector * RV64IMACFDArch::createInterruptVector(ETISS_CPU * cpu)
 	if (cpu == 0)
 		return 0;
 
-	/**************************************************************************
-	*		            Implementation of interrupt vector              	  *
-	***************************************************************************/
-
-	// This is a default vector, implemented to avoid segfaults. Replace
-	// with actual implementation if necessary.
-
 	std::vector<etiss::uint64 *> vec;
 	std::vector<etiss::uint64 *> mask;
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index 4b144de211..93fe4cd770 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
@@ -52,7 +52,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOSWAPW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -170,7 +174,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOADDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -290,7 +298,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOXORW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -410,7 +422,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOANDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -530,7 +546,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOORW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -650,7 +670,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMINW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -770,7 +794,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -890,7 +918,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMINUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -1010,7 +1042,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index 3ef72ff241..be8821ff6b 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
@@ -48,7 +48,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFLD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -144,7 +148,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFSD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -238,7 +246,11 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CFLDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -330,7 +342,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CFSDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index f31a426a04..dd3a0c4e08 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
@@ -46,7 +46,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//FLD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -140,7 +144,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//FSD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -239,7 +247,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -324,7 +336,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -409,7 +425,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -494,7 +514,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -576,7 +600,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FADD_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -655,7 +683,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSUB_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -734,7 +766,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMUL_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -813,7 +849,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FDIV_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -889,7 +929,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FSQRT_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
@@ -962,7 +1006,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJ_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1)) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n";
@@ -1033,7 +1081,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJN_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1))) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n";
@@ -1104,7 +1156,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJX_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) & 9223372036854775808ULL);\n";
@@ -1175,7 +1231,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMIN_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 0ULL);\n";
@@ -1248,7 +1308,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMAX_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 1ULL);\n";
@@ -1321,7 +1385,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], " + std::to_string(rm) + "ULL);\n";
@@ -1392,7 +1460,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), " + std::to_string(rm) + "ULL);\n";
@@ -1467,7 +1539,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FEQ_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = 0ULL;\n";
@@ -1544,7 +1620,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLT_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = 0ULL;\n";
@@ -1621,7 +1701,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLE_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = 0ULL;\n";
@@ -1695,7 +1779,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCLASS_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
@@ -1763,7 +1851,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_W_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_int32 res = 0ULL;\n";
@@ -1840,7 +1932,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_WU_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1917,7 +2013,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
@@ -1989,7 +2089,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_WU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index 71bc6c0490..ad21a7950c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
@@ -46,7 +46,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//FLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -144,7 +148,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//FSW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -243,7 +251,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -332,7 +344,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -421,7 +437,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -513,7 +533,11 @@ rs3 += R_rs3_0.read(ba) << 0;
 		cp.code() = std::string("//FNMSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -602,7 +626,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FADD_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -687,7 +715,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSUB_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -772,7 +804,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMUL_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -857,7 +893,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FDIV_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -939,7 +979,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FSQRT_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1017,7 +1061,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJ_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1094,7 +1142,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJN_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1171,7 +1223,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FSGNJX_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1248,7 +1304,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMIN_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1327,7 +1387,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FMAX_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1406,7 +1470,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_W_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_int32 res = 0ULL;\n";
@@ -1488,7 +1556,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_WU_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1570,7 +1642,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FEQ_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1653,7 +1729,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLT_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1736,7 +1816,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//FLE_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1816,7 +1900,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCLASS_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = 0ULL;\n";
@@ -1888,7 +1976,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -1964,7 +2056,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_WU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
@@ -2037,7 +2133,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_X_W\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -2104,7 +2204,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_W_X\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 { // block
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index b2d31f8fba..92a8f8c22b 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
@@ -49,7 +49,11 @@ imm += R_imm_4.read(ba) << 4;
 		cp.code() = std::string("//CADDI4SPN\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if (imm) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(imm) + "ULL;\n";
 } // conditional
@@ -143,7 +147,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -243,7 +251,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CSW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -338,7 +350,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CADDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rs1 % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
 } // conditional
@@ -403,7 +419,11 @@ nzimm += R_nzimm_5.read(ba) << 5;
 		cp.code() = std::string("//CNOP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "} // block\n";
@@ -467,7 +487,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -538,7 +562,11 @@ imm += R_imm_17.read(ba) << 17;
 		cp.code() = std::string("//CLUI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if (imm == 0ULL) { // conditional
@@ -629,7 +657,11 @@ nzimm += R_nzimm_9.read(ba) << 9;
 		cp.code() = std::string("//CADDI16SP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if (nzimm) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[2ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)nzimm) << (6)) >> (6))) + "LL;\n";
 } // conditional
@@ -712,7 +744,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//__reserved_clui\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // procedure
 cp.code() += "{ // procedure\n";
 cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
@@ -783,7 +819,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
@@ -849,7 +889,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if (shamt) { // conditional
@@ -923,7 +967,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CANDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] & " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
@@ -991,7 +1039,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CSUB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
@@ -1058,7 +1110,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CXOR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
@@ -1125,7 +1181,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//COR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
@@ -1192,7 +1252,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CAND\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
@@ -1270,7 +1334,11 @@ imm += R_imm_11.read(ba) << 11;
 		cp.code() = std::string("//CJ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
@@ -1358,7 +1426,11 @@ imm += R_imm_8.read(ba) << 8;
 		cp.code() = std::string("//CBEQZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] == 0ULL) { // conditional\n";
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
 cp.code() += "} // conditional\n";
@@ -1446,7 +1518,11 @@ imm += R_imm_8.read(ba) << 8;
 		cp.code() = std::string("//CBNEZ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] != 0ULL) { // conditional\n";
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
 cp.code() += "} // conditional\n";
@@ -1526,7 +1602,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if (nzuimm) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(nzuimm) + "ULL;\n";
 } // conditional
@@ -1594,7 +1674,11 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CLWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if (rd % 32ULL) { // conditional
@@ -1697,7 +1781,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CMV\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -1758,7 +1846,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CJR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if (rs1) { // conditional
 cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & -2LL;\n";
 } // conditional
@@ -1829,7 +1921,11 @@ static InstructionDefinition __reserved_cmv_ (
 		cp.code() = std::string("//__reserved_cmv\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // procedure
 cp.code() += "{ // procedure\n";
 cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
@@ -1897,7 +1993,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CADD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -1959,7 +2059,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//CJALR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -2027,7 +2131,11 @@ static InstructionDefinition cebreak_ (
 		cp.code() = std::string("//CEBREAK\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // procedure
 cp.code() += "{ // procedure\n";
 cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
@@ -2097,7 +2205,11 @@ uimm += R_uimm_2.read(ba) << 2;
 		cp.code() = std::string("//CSWSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -2179,7 +2291,11 @@ static InstructionDefinition dii_ (
 		cp.code() = std::string("//DII\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // procedure
 cp.code() += "{ // procedure\n";
 cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index af9fc6da37..bfc7137909 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
@@ -43,7 +43,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//LUI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + "ULL;\n";
 } // conditional
@@ -106,7 +110,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//AUIPC\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + "LL;\n";
 } // conditional
@@ -175,7 +183,11 @@ imm += R_imm_20.read(ba) << 20;
 		cp.code() = std::string("//JAL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if (imm % 2ULL) { // conditional
@@ -279,7 +291,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//JALR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL) & -2LL;\n";
@@ -388,7 +404,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BEQ\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
@@ -505,7 +525,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BNE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
@@ -622,7 +646,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BLT\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
@@ -739,7 +767,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BGE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
@@ -856,7 +888,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BLTU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
@@ -973,7 +1009,11 @@ imm += R_imm_12.read(ba) << 12;
 		cp.code() = std::string("//BGEU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
@@ -1084,7 +1124,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1179,7 +1223,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1274,7 +1322,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1369,7 +1421,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LBU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1464,7 +1520,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LHU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1561,7 +1621,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1657,7 +1721,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1753,7 +1821,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -1847,7 +1919,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ADDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
 } // conditional
@@ -1917,7 +1993,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//SLTI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL)) ? (1ULL) : (0ULL);\n";
 } // conditional
@@ -1987,7 +2067,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//SLTIU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL)) ? (1ULL) : (0ULL);\n";
 } // conditional
@@ -2057,7 +2141,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//XORI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
 } // conditional
@@ -2127,7 +2215,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ORI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
 } // conditional
@@ -2197,7 +2289,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ANDI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
 } // conditional
@@ -2267,7 +2363,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
 } // conditional
@@ -2337,7 +2437,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
 } // conditional
@@ -2407,7 +2511,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> " + std::to_string(shamt) + "ULL;\n";
 } // conditional
@@ -2477,7 +2585,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//ADD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -2548,7 +2660,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SUB\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -2619,7 +2735,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
 } // conditional
@@ -2690,7 +2810,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLT\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (1ULL) : (0ULL);\n";
 } // conditional
@@ -2761,7 +2885,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLTU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (1ULL) : (0ULL);\n";
 } // conditional
@@ -2832,7 +2960,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//XOR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -2903,7 +3035,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
 } // conditional
@@ -2974,7 +3110,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRA\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
 } // conditional
@@ -3045,7 +3185,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//OR\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -3116,7 +3260,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//AND\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
 } // conditional
@@ -3193,7 +3341,11 @@ fm += R_fm_0.read(ba) << 0;
 		cp.code() = std::string("//FENCE\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "((RV64IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index f955c487d9..2c10477152 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
@@ -46,7 +46,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MUL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -126,7 +130,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULH\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -206,7 +214,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULHSU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -286,7 +298,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULHU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -366,7 +382,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIV\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -460,7 +480,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIVU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -544,7 +568,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REM\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -638,7 +666,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REMU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index 17e77805f4..fcddf4c96e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
@@ -52,7 +52,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOSWAPD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -170,7 +174,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOADDD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -290,7 +298,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOXORD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -410,7 +422,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOANDD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -530,7 +546,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOORD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -650,7 +670,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMIND\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -770,7 +794,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -890,7 +918,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMINUD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -1010,7 +1042,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//AMOMAXUD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index 12ce2be11e..445b15d5fa 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
@@ -46,7 +46,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_L_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0ULL, " + std::to_string(rm) + "ULL);\n";
@@ -119,7 +123,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_LU_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
@@ -192,7 +200,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_L\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
@@ -264,7 +276,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_D_LU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
@@ -333,7 +349,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_X_D\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL];\n";
@@ -398,7 +418,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FMV_D_X\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index 1de29f3eb6..78a817d4c0 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
@@ -46,7 +46,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_L_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0ULL, " + std::to_string(rm) + "ULL);\n";
@@ -122,7 +126,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_LU_S\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
@@ -198,7 +206,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_L\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
@@ -274,7 +286,11 @@ rs1 += R_rs1_0.read(ba) << 0;
 		cp.code() = std::string("//FCVT_S_LU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index e40d21216d..69e3970b24 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
@@ -45,7 +45,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//CADDIW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rs1 % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
 } // conditional
@@ -113,7 +117,11 @@ nzuimm += R_nzuimm_5.read(ba) << 5;
 		cp.code() = std::string("//CSRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(nzuimm) + "ULL;\n";
@@ -183,7 +191,11 @@ shamt += R_shamt_5.read(ba) << 5;
 		cp.code() = std::string("//CSRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
@@ -253,7 +265,11 @@ shamt += R_shamt_5.read(ba) << 5;
 		cp.code() = std::string("//CSLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if (rs1 == 0ULL) { // conditional
@@ -343,7 +359,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CLD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -439,7 +459,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CSD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -530,7 +554,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CSUBW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
@@ -598,7 +626,11 @@ rd += R_rd_0.read(ba) << 0;
 		cp.code() = std::string("//CADDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
@@ -670,7 +702,11 @@ uimm += R_uimm_5.read(ba) << 5;
 		cp.code() = std::string("//CLDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
@@ -773,7 +809,11 @@ uimm += R_uimm_3.read(ba) << 3;
 		cp.code() = std::string("//CSDSP\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index 96eb8e3c6b..fe012773a4 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
@@ -46,7 +46,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LWU\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -141,7 +145,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//LD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -238,7 +246,11 @@ imm += R_imm_5.read(ba) << 5;
 		cp.code() = std::string("//SD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
@@ -332,7 +344,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SLLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
 } // conditional
@@ -402,7 +418,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRLI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
 } // conditional
@@ -472,7 +492,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRAI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
 } // conditional
@@ -542,7 +566,11 @@ imm += R_imm_0.read(ba) << 0;
 		cp.code() = std::string("//ADDIW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -621,7 +649,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SLLIW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -700,7 +732,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRLIW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -779,7 +815,11 @@ shamt += R_shamt_0.read(ba) << 0;
 		cp.code() = std::string("//SRAIW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -858,7 +898,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//ADDW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -938,7 +982,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SUBW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -1018,7 +1066,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SLLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -1099,7 +1151,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRLW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -1180,7 +1236,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//SRAW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index 946009feba..cf31ae2833 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
@@ -46,7 +46,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//MULW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -125,7 +129,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIVW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -219,7 +227,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//DIVUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -303,7 +315,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REMW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
@@ -397,7 +413,11 @@ rs2 += R_rs2_0.read(ba) << 0;
 		cp.code() = std::string("//REMUW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index 7817a84209..512b18d804 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
@@ -47,7 +47,11 @@ imm += R_imm_0.read(ba) << 0;
 
 // -----------------------------------------------------------------------------
 cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 cp.code() += "((RV64IMACFD*)cpu)->FENCE[1ULL] = " + std::to_string(imm) + "ULL;\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index 6e3cc03f8e..a54d8f21f1 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
@@ -46,7 +46,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -134,7 +138,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRS\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
@@ -213,7 +221,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRC\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
@@ -292,7 +304,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRWI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
@@ -367,7 +383,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRSI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
@@ -444,7 +464,11 @@ csr += R_csr_0.read(ba) << 0;
 		cp.code() = std::string("//CSRRCI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index c8ec27a368..7cd6f43751 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
@@ -37,10 +37,13 @@ static InstructionDefinition ecall_ (
 		cp.code() = std::string("//ECALL\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+{ // block
+cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
 cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";
@@ -104,7 +107,11 @@ static InstructionDefinition mret_ (
 		cp.code() = std::string("//MRET\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
@@ -186,7 +193,11 @@ static InstructionDefinition wfi_ (
 		cp.code() = std::string("//WFI\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "} // block\n";
@@ -246,7 +257,11 @@ static InstructionDefinition sret_ (
 		cp.code() = std::string("//SRET\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < ((get_field(csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index f7fd43ee15..2a4ae1423c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
@@ -49,7 +49,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//LRD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -154,7 +158,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//SCD\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index 9cd99e0fa6..f330465196 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
@@ -49,7 +49,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//LRW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
@@ -154,7 +158,11 @@ aq += R_aq_0.read(ba) << 0;
 		cp.code() = std::string("//SCW\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index bc1b776fb1..ca63c88d40 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.
@@ -37,7 +37,11 @@ static InstructionDefinition ebreak_ (
 		cp.code() = std::string("//EBREAK\n");
 
 // -----------------------------------------------------------------------------
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "if (etiss_semihost_enabled()) { // conditional\n";

From 843a6c7b5c34a29d74bdb798b7a547448c6aab69 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Mon, 2 Oct 2023 19:04:25 +0200
Subject: [PATCH 40/44] update architectures

---
 ArchImpl/RV32IMACFD/CMakeLists.txt                   |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD.h                     |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp               |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArch.h                 |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp            |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h      |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h                | 12 +-----------
 ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h              |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp              |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp        |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp       |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp        |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp       |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp        |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp       |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp        |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp        |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp     |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp      |  2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp      |  5 +----
 ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp      |  2 +-
 .../RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp   |  2 +-
 ArchImpl/RV64IMACFD/CMakeLists.txt                   |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD.h                     |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp               |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArch.h                 |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp            |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h      |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h                | 12 +-----------
 ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h              |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp              |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp        |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp       |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp        |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp        |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp       |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp        |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp        |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp        |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp        |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp        |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp       |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp        |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp        |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp     |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp      |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp      |  5 +----
 ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp    |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp      |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp   |  2 +-
 50 files changed, 50 insertions(+), 76 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index 81758ec16a..d879229ee0 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+# Generated on Mon, 02 Oct 2023 18:56:15 +0200.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD.h b/ArchImpl/RV32IMACFD/RV32IMACFD.h
index da20647610..a11f9b4860 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the registers for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
index 1ce16b9873..a9526b644e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
index b16dc782f1..0684724910 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
index 7e3c4fdbea..1d13aad6a0 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the library interface for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
index 68ec2941f8..558a1ab560 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the architecture specific header for the RV32IMACFD
  * core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index f0877dd09c..db0f8900c5 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */
@@ -78,8 +78,6 @@ extern etiss_uint64 unbox_d(etiss_uint64);
 
 extern etiss_uint64 fclass_d(etiss_uint64);
 
-extern etiss_int32 ETISS_SIGNAL_MMU(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 mmu_signal_);
-
 extern etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
 extern etiss_uint64 etiss_get_time();
@@ -94,8 +92,6 @@ static inline etiss_uint32 csr_read(ETISS_CPU * const cpu, ETISS_System * const
 
 static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val);
 
-extern void etiss_icache_flush(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
-
 static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask);
 
 static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
@@ -225,9 +221,6 @@ if (csr == 1LL) { // conditional
  else if (csr != 769LL) { // conditional
 *((RV32IMACFD*)cpu)->CSR[csr] = val;
 } // conditional
-if (csr == 384LL) { // conditional
-ETISS_SIGNAL_MMU(cpu, system, plugin_pointers, val);
-} // conditional
 } // block
 }
 
@@ -353,9 +346,6 @@ return;
 } // conditional
  else if (cause == -5LL) { // conditional
 code = 5LL;
-} // conditional
- else if (cause == -13LL) { // conditional
-code = 12LL;
 } // conditional
  else if (cause == -14LL) { // conditional
 code = 13LL;
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
index 2ab06c756d..bb5746e691 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the GDBCore adapter for the RV32IMACFD core architecture.
  *
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
index 8fdc4ad2f7..95800ae5b6 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index d08cab2180..e4d2fada57 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index a9223c162a..50aeab6a5f 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index 676b53aa6b..307c7ad932 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 91555dca84..b0d4ae3ae8 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 5098a12777..1ca433e84e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index 35213500f1..b557a7efed 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 0b3bce3068..a5e5e81eda 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index b53c36b44f..ad27c75c6f 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index 334df36196..c191dd8dcb 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index 0d19b4f23b..efaa46c518 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 858ff8caec..2800806791 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
@@ -128,9 +128,6 @@ cp.code() += "etiss_uint32 prev_prv = get_field(s, 6144LL);\n";
 cp.code() += "if (prev_prv != 3LL) { // conditional\n";
 cp.code() += "s = set_field(s, 131072LL, 0ULL);\n";
 cp.code() += "} // conditional\n";
-cp.code() += "if (prev_prv != ((RV32IMACFD*)cpu)->PRIV && csr_read(cpu, system, plugin_pointers, 384LL) != 0ULL) { // conditional\n";
-cp.code() += "etiss_icache_flush(cpu, system, plugin_pointers);\n";
-cp.code() += "} // conditional\n";
 cp.code() += "s = set_field(s, 8LL, get_field(s, 128LL));\n";
 cp.code() += "s = set_field(s, 128LL, 1ULL);\n";
 cp.code() += "s = set_field(s, 6144LL, (extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index eb58af84ed..c70a999ee9 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index a410cf4178..937b42b853 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt
index 0a0daa11f3..5293cbb995 100644
--- a/ArchImpl/RV64IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV64IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+# Generated on Mon, 02 Oct 2023 18:56:15 +0200.
 #
 # This file contains the CMake build info for the RV64IMACFD core architecture.
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD.h b/ArchImpl/RV64IMACFD/RV64IMACFD.h
index 22b49ee4c5..d88be9a2d7 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the registers for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
index 9f350a6a7a..3876c0ec1f 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
index e65824ea48..5abf67a078 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
index d0fb04998c..ae653db6e9 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the library interface for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
index bb61204921..64d12881f8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the architecture specific header for the RV64IMACFD
  * core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index a278bcc85b..3b12f9da7a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the function macros for the RV64IMACFD core architecture.
  */
@@ -78,8 +78,6 @@ extern etiss_uint64 unbox_d(etiss_uint64);
 
 extern etiss_uint64 fclass_d(etiss_uint64);
 
-extern etiss_int32 ETISS_SIGNAL_MMU(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint64 mmu_signal_);
-
 extern etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
 extern etiss_uint64 etiss_get_time();
@@ -94,8 +92,6 @@ static inline etiss_uint64 csr_read(ETISS_CPU * const cpu, ETISS_System * const
 
 static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val);
 
-extern void etiss_icache_flush(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
-
 static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask);
 
 static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
@@ -225,9 +221,6 @@ if (csr == 1LL) { // conditional
  else if (csr != 769LL) { // conditional
 *((RV64IMACFD*)cpu)->CSR[csr] = val;
 } // conditional
-if (csr == 384LL) { // conditional
-ETISS_SIGNAL_MMU(cpu, system, plugin_pointers, val);
-} // conditional
 } // block
 }
 
@@ -353,9 +346,6 @@ return;
 } // conditional
  else if (cause == -5LL) { // conditional
 code = 5LL;
-} // conditional
- else if (cause == -13LL) { // conditional
-code = 12LL;
 } // conditional
  else if (cause == -14LL) { // conditional
 code = 13LL;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
index 3bd94d3508..8c02edac5a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the GDBCore adapter for the RV64IMACFD core architecture.
  *
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
index 0ffb7fabe3..b77ca4ea85 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 17:35:59 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index 93fe4cd770..72ea281665 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index be8821ff6b..067fef8148 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index dd3a0c4e08..c80ccdbc43 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index ad21a7950c..0e5cc3d896 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index 92a8f8c22b..591abb85e2 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index bfc7137909..1b509c4f87 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index 2c10477152..0db1774da2 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index fcddf4c96e..09d9058afd 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index 445b15d5fa..d872ad74af 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index 78a817d4c0..56cef4419c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index 69e3970b24..001bc40ec8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index fe012773a4..84117122b4 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index cf31ae2833..6592d82d62 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index 512b18d804..6f36370cf3 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index a54d8f21f1..5365987992 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index 7cd6f43751..1ab82edbc1 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
@@ -128,9 +128,6 @@ cp.code() += "etiss_uint64 prev_prv = get_field(s, 6144LL);\n";
 cp.code() += "if (prev_prv != 3LL) { // conditional\n";
 cp.code() += "s = set_field(s, 131072LL, 0ULL);\n";
 cp.code() += "} // conditional\n";
-cp.code() += "if (prev_prv != ((RV64IMACFD*)cpu)->PRIV && csr_read(cpu, system, plugin_pointers, 384LL) != 0ULL) { // conditional\n";
-cp.code() += "etiss_icache_flush(cpu, system, plugin_pointers);\n";
-cp.code() += "} // conditional\n";
 cp.code() += "s = set_field(s, 8LL, get_field(s, 128LL));\n";
 cp.code() += "s = set_field(s, 128LL, 1ULL);\n";
 cp.code() += "s = set_field(s, 6144LL, (extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index 2a4ae1423c..3d11719e72 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index f330465196..0703c53bc2 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index ca63c88d40..7dbfd5c58e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:26:51 +0200.
+ * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.

From 1fc7c1fdb91e0b5d3b476ccacfa9f2ba4cccc588 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Wed, 4 Oct 2023 17:05:00 +0200
Subject: [PATCH 41/44] don't use affected regs

---
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp | 29 +------
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     |  6 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp | 12 +--
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     |  6 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp | 14 +---
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     | 48 +----------
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp | 83 +------------------
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp | 26 +-----
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |  2 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    | 11 +--
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    |  2 +-
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |  7 +-
 .../RV32IMACFD_tum_semihostingInstr.cpp       |  5 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h         |  2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp | 29 +------
 .../RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp     |  6 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp | 12 +--
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp | 14 +---
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     | 47 +----------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp | 83 +------------------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp | 26 +-----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp | 29 +------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp |  8 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp |  6 +-
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     | 24 +-----
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp | 37 +--------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp | 17 +---
 .../RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp   |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    | 11 +--
 .../RV64IMACFD/RV64IMACFD_tum_retInstr.cpp    |  2 +-
 .../RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp  |  7 +-
 .../RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp    |  7 +-
 .../RV64IMACFD_tum_semihostingInstr.cpp       |  5 +-
 33 files changed, 33 insertions(+), 592 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index e4d2fada57..20c7af819a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
@@ -89,9 +89,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -213,9 +210,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -337,9 +331,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -461,9 +452,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -585,9 +573,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -709,9 +694,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -833,9 +815,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -957,9 +936,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1081,9 +1057,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index 50aeab6a5f..c7ddf3544f 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
@@ -73,7 +73,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -172,7 +171,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -271,7 +269,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -366,7 +363,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index 307c7ad932..cff92b29bc 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
@@ -71,7 +71,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -168,7 +167,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1558,7 +1556,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1639,7 +1636,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1720,7 +1716,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1792,7 +1787,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1870,7 +1864,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1951,7 +1944,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2027,7 +2019,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2103,7 +2094,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index b0d4ae3ae8..66e2f948c1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
@@ -79,7 +79,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -182,7 +181,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -287,7 +285,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -382,7 +379,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 1ca433e84e..46c8d33eaa 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
@@ -75,7 +75,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -172,7 +171,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1494,7 +1492,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1580,7 +1577,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1667,7 +1663,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1754,7 +1749,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1841,7 +1835,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1917,7 +1910,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1994,7 +1986,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2074,7 +2065,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2148,7 +2138,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2221,7 +2210,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index b557a7efed..c5a9542d72 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
@@ -68,8 +68,6 @@ cp.code() += "} // procedure\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -171,8 +169,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -275,8 +271,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -361,8 +355,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -510,7 +502,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[1ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -603,7 +594,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -686,7 +676,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -777,8 +766,6 @@ cp.code() += "} // procedure\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[2ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -933,8 +920,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1009,8 +994,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1081,8 +1064,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1153,9 +1134,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1224,9 +1202,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1295,9 +1270,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1366,9 +1338,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1538,7 +1507,6 @@ cp.code() += "} // conditional\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1630,7 +1598,6 @@ cp.code() += "} // conditional\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1714,8 +1681,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1813,7 +1778,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1893,8 +1857,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1966,7 +1928,6 @@ cp.code() += "} // procedure\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -2105,9 +2066,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2175,8 +2133,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[1ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -2330,8 +2286,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index a5e5e81eda..5e286283c2 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
@@ -54,7 +54,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = "
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -121,7 +120,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = "
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -217,7 +215,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -326,8 +323,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -441,8 +436,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -562,8 +555,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -683,8 +674,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -804,8 +793,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -925,8 +912,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1046,8 +1031,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1151,8 +1134,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1250,8 +1231,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1349,8 +1328,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1448,8 +1425,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1547,8 +1522,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1645,8 +1618,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1745,8 +1716,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1845,8 +1814,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1930,8 +1897,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2004,8 +1969,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2078,8 +2041,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2152,8 +2113,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2226,8 +2185,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2300,8 +2257,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2374,8 +2329,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2448,8 +2401,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2522,8 +2473,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (e
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2596,9 +2545,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2671,9 +2617,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2746,9 +2689,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2821,9 +2761,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2896,9 +2833,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2971,9 +2905,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -3046,9 +2977,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -3121,9 +3049,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (e
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -3196,9 +3121,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -3271,9 +3193,6 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index ad27c75c6f..18d4ba3e48 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
@@ -66,9 +66,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -150,9 +147,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -234,9 +228,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -318,9 +309,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -416,9 +404,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -504,9 +489,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -602,9 +584,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -690,9 +669,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index c191dd8dcb..069792cd9b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index efaa46c518..c045d9ea3c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
@@ -75,8 +75,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -158,8 +156,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -241,8 +237,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -321,7 +315,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -402,7 +395,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -483,7 +475,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 2800806791..06f64048f1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index c70a999ee9..363476b4df 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
@@ -77,8 +77,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -188,9 +186,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index 937b42b853..2aceb3f379 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
@@ -121,9 +121,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[10ULL], 32);
-		cp.getRegisterDependencies().add(reg_name[11ULL], 32);
-		cp.getAffectedRegisters().add(reg_name[10ULL], 32);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index 3b12f9da7a..097e662ebe 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the function macros for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index 72ea281665..da84440926 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
@@ -89,9 +89,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -213,9 +210,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -337,9 +331,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -461,9 +452,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -585,9 +573,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -709,9 +694,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -833,9 +815,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -957,9 +936,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1081,9 +1057,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index 067fef8148..730817c49a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
@@ -73,7 +73,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -172,7 +171,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -271,7 +269,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -366,7 +363,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index c80ccdbc43..060dbc736a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
@@ -71,7 +71,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -168,7 +167,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1558,7 +1556,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1639,7 +1636,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1720,7 +1716,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1792,7 +1787,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1870,7 +1864,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1951,7 +1944,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2027,7 +2019,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2103,7 +2094,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index 0e5cc3d896..7e677499c6 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
@@ -75,7 +75,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -172,7 +171,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1494,7 +1492,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1580,7 +1577,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1667,7 +1663,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1754,7 +1749,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1841,7 +1835,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1917,7 +1910,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1994,7 +1986,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2074,7 +2065,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2148,7 +2138,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2221,7 +2210,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index 591abb85e2..793a1824a8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
@@ -68,8 +68,6 @@ cp.code() += "} // procedure\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -171,8 +169,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -275,8 +271,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -361,8 +355,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -502,7 +494,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -585,7 +576,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -676,8 +666,6 @@ cp.code() += "} // procedure\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[2ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -832,8 +820,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -908,8 +894,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -980,8 +964,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1052,9 +1034,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1123,9 +1102,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1194,9 +1170,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1265,9 +1238,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1437,7 +1407,6 @@ cp.code() += "} // conditional\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1529,7 +1498,6 @@ cp.code() += "} // conditional\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1613,8 +1581,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1712,7 +1678,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1792,8 +1757,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1865,7 +1828,6 @@ cp.code() += "} // procedure\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -2004,9 +1966,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2074,8 +2033,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[1ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -2229,8 +2186,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index 1b509c4f87..896c5c5410 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
@@ -54,7 +54,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = "
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -121,7 +120,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = "
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -217,7 +215,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -326,8 +323,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -441,8 +436,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -562,8 +555,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -683,8 +674,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -804,8 +793,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -925,8 +912,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1046,8 +1031,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1151,8 +1134,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1250,8 +1231,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1349,8 +1328,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1448,8 +1425,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1547,8 +1522,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1645,8 +1618,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1745,8 +1716,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1845,8 +1814,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1930,8 +1897,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2004,8 +1969,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2078,8 +2041,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2152,8 +2113,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2226,8 +2185,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2300,8 +2257,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2374,8 +2329,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2448,8 +2401,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2522,8 +2473,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (e
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2596,9 +2545,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2671,9 +2617,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2746,9 +2689,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2821,9 +2761,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2896,9 +2833,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -2971,9 +2905,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -3046,9 +2977,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -3121,9 +3049,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (e
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -3196,9 +3121,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -3271,9 +3193,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index 0db1774da2..79f04bfe79 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
@@ -66,9 +66,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -150,9 +147,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -234,9 +228,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -318,9 +309,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -416,9 +404,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -504,9 +489,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -602,9 +584,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -690,9 +669,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index 09d9058afd..1b8c32f1a0 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
@@ -89,9 +89,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -213,9 +210,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -337,9 +331,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -461,9 +452,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -585,9 +573,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -709,9 +694,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -833,9 +815,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -957,9 +936,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -1081,9 +1057,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index d872ad74af..670c5e31c0 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
@@ -61,7 +61,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -138,7 +137,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -214,7 +212,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -290,7 +287,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -362,7 +358,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -431,7 +426,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index 56cef4419c..fb8dabf30a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
@@ -64,7 +64,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -144,7 +143,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -224,7 +222,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -304,7 +301,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index 001bc40ec8..fe07364274 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
@@ -56,8 +56,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = (
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -130,8 +128,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -204,8 +200,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -286,8 +280,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1], 64);
-		cp.getAffectedRegisters().add(reg_name[rs1], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -383,8 +375,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -483,8 +473,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 + 8ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -568,9 +556,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -640,9 +625,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rd + 8ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 + 8ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd + 8ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -737,8 +719,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -833,8 +813,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[2ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index 84117122b4..8b2f4f27b3 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
@@ -73,8 +73,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -172,8 +170,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -270,8 +266,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -355,8 +349,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -429,8 +421,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *(
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -503,8 +493,6 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -586,8 +574,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -669,8 +655,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -752,8 +736,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -835,8 +817,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -918,9 +898,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1002,9 +979,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1087,9 +1061,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1172,9 +1143,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -1257,9 +1225,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index 6592d82d62..5219edcc02 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
@@ -65,9 +65,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -163,9 +160,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -251,9 +245,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -349,9 +340,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -437,9 +425,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index 6f36370cf3..fdfc3c104f 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index 5365987992..ed80d4ea58 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
@@ -75,8 +75,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -158,8 +156,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -241,8 +237,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -321,7 +315,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -402,7 +395,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
@@ -483,7 +475,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index 1ab82edbc1..ae78dee27e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index 3d11719e72..51497c6228 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
@@ -77,8 +77,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -188,9 +186,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index 0703c53bc2..41a384c539 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
@@ -77,8 +77,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
@@ -188,9 +186,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[rs1 % 32ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[rs2 % 32ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[rd % 32ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index 7dbfd5c58e..adfedfbfa0 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.
@@ -121,9 +121,6 @@ cp.code() += "} // block\n";
 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
 // -----------------------------------------------------------------------------
-		cp.getRegisterDependencies().add(reg_name[10ULL], 64);
-		cp.getRegisterDependencies().add(reg_name[11ULL], 64);
-		cp.getAffectedRegisters().add(reg_name[10ULL], 64);
 		cp.getAffectedRegisters().add("instructionPointer", 32);
 	}
 	{

From 2a29d8e605d0031c960fbb59cf379de54ff614c3 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Fri, 3 Nov 2023 16:31:32 +0100
Subject: [PATCH 42/44] update arch

---
 ArchImpl/RV32IMACFD/CMakeLists.txt            |   3 +-
 ArchImpl/RV32IMACFD/RV32IMACFD.h              |   2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp        |   4 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArch.h          |   2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp     |   2 +-
 .../RV32IMACFD/RV32IMACFDArchSpecificImp.cpp  |  11 +-
 .../RV32IMACFD/RV32IMACFDArchSpecificImp.h    |   2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c         | 344 ++++++++++++++
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h         | 443 +++---------------
 ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h       |   2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp       |   4 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp |  40 +-
 .../RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp     |  12 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp |  26 +-
 .../RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp     |  12 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp |  26 +-
 .../RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp     |  30 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp |  36 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp |   4 +-
 .../RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp   |   4 +-
 .../RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp    |  30 +-
 .../RV32IMACFD/RV32IMACFD_tum_retInstr.cpp    |  38 +-
 .../RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp    |   8 +-
 .../RV32IMACFD_tum_semihostingInstr.cpp       |  14 +-
 ArchImpl/RV64IMACFD/CMakeLists.txt            |   4 +-
 ArchImpl/RV64IMACFD/RV64IMACFD.h              |   2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp        |   4 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArch.h          |   2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp     |   2 +-
 .../RV64IMACFD/RV64IMACFDArchSpecificImp.cpp  |  14 +-
 .../RV64IMACFD/RV64IMACFDArchSpecificImp.h    |   2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c         | 368 +++++++++++++++
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h         | 443 +++---------------
 ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h       |   2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp       |   4 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp |  40 +-
 .../RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp     |  12 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp |  26 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp |  26 +-
 .../RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp     |  30 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp |  36 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp | 328 +------------
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp |  40 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp |   4 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp |   4 +-
 .../RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp     |  16 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp |  10 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp |   4 +-
 .../RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp   |   4 +-
 .../RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp    |  30 +-
 .../RV64IMACFD/RV64IMACFD_tum_retInstr.cpp    |  38 +-
 .../RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp  |   8 +-
 .../RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp    |   8 +-
 .../RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp    | 334 +++++++++++++
 .../RV64IMACFD_tum_semihostingInstr.cpp       |  14 +-
 .../RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp |   2 +
 56 files changed, 1475 insertions(+), 1485 deletions(-)
 create mode 100644 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c
 create mode 100644 ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp

diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index d879229ee0..b39a43b380 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+# Generated on Fri, 03 Nov 2023 13:22:23 +0100.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
@@ -11,6 +11,7 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFDArch.cpp
 	RV32IMACFDArchLib.cpp
 	RV32IMACFDArchSpecificImp.cpp
+	RV32IMACFDFuncs.c
 	RV32IMACFDInstr.cpp
 	RV32IMACFD_RV32IInstr.cpp
 	RV32IMACFD_RV32ICInstr.cpp
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD.h b/ArchImpl/RV32IMACFD/RV32IMACFD.h
index a11f9b4860..82269635a2 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the registers for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
index a9526b644e..45ac32cd06 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
@@ -35,8 +35,6 @@
  *********************************************************************************************************************************/
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 #define RV32IMACFD_DEBUG_CALL 0
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
index 0684724910..f985a923fc 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
index 1d13aad6a0..83c9616a9a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the library interface for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
index 100d8bc3fd..7d9cccec47 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -12,11 +12,7 @@
 
 #include "RV32IMACFDArch.h"
 #include "RV32IMACFDArchSpecificImp.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
-extern "C" {
 #include "RV32IMACFDFuncs.h"
-}
 
 /**
 	@brief This function will be called automatically in order to handling exceptions such as interrupt, system call, illegal instructions
@@ -34,9 +30,8 @@ extern "C" {
 */
 etiss::int32 RV32IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu)
 {
-    translate_exc_code(cpu, nullptr, nullptr, cause);
+	RV32IMACFD_translate_exc_code(cpu, nullptr, nullptr, cause);
 	cpu->instructionPointer = cpu->nextPc;
-
 	return 0;
 }
 
@@ -126,7 +121,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -173,7 +168,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
index 558a1ab560..eb94b75582 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture specific header for the RV32IMACFD
  * core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c
new file mode 100644
index 0000000000..bf638e23ba
--- /dev/null
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c
@@ -0,0 +1,344 @@
+/**
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ *
+ * This file contains the function implementations for the RV32IMACFD core architecture.
+ */
+
+#include "RV32IMACFDFuncs.h"
+
+etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
+{
+{ // block
+return (*((RV32IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
+} // block
+}
+
+etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
+{
+{ // block
+if (rm == 7ULL) { // conditional
+rm = ((((((RV32IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7;
+} // conditional
+if (rm > 4ULL) { // conditional
+RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);
+} // conditional
+return rm;
+} // block
+}
+
+etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 mask = 0ULL;
+if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
+{ // block
+mask = mask | 5767458ULL;
+if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
+mask = mask | 1536LL;
+} // conditional
+if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
+mask = mask | 24576LL;
+} // conditional
+if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
+mask = mask | 98304LL;
+} // conditional
+if ((RV32IMACFD_get_field(*((RV32IMACFD*)cpu)->CSR[384LL], 2147483648ULL))) { // conditional
+mask = mask | 262144LL;
+} // conditional
+} // block
+} // conditional
+return mask;
+} // block
+}
+
+etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 mask = 6280ULL;
+return mask | RV32IMACFD_sstatus_mask(cpu, system, plugin_pointers);
+} // block
+}
+
+etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
+{
+{ // block
+if (csr == 1LL) { // conditional
+return *((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL;
+} // conditional
+if (csr == 2LL) { // conditional
+return (*((RV32IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
+} // conditional
+if (csr == 3072LL) { // conditional
+return etiss_get_cycles(cpu, system, plugin_pointers);
+} // conditional
+if (csr == 3200LL) { // conditional
+return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 3073LL) { // conditional
+return etiss_get_time();
+} // conditional
+if (csr == 3201LL) { // conditional
+return etiss_get_time() >> 32ULL;
+} // conditional
+if (csr == 3074LL) { // conditional
+return etiss_get_instret(cpu, system, plugin_pointers);
+} // conditional
+if (csr == 3202LL) { // conditional
+return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 768LL || csr == 256LL) { // conditional
+return *((RV32IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
+} // conditional
+if (csr == 769LL) { // conditional
+return (((1ULL) << 30) | ((((*((RV32IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 1073741823)));
+} // conditional
+return *((RV32IMACFD*)cpu)->CSR[csr];
+} // block
+}
+
+void RV32IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
+{
+{ // block
+if (csr == 1LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[3LL] = (*((RV32IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
+} // conditional
+ else if (csr == 2LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL);
+} // conditional
+ else if (csr == 3LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
+} // conditional
+ else if (csr == 768LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[768LL] = val & RV32IMACFD_mstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr == 256LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[768LL] = val & RV32IMACFD_sstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr != 769LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[csr] = val;
+} // conditional
+} // block
+}
+
+etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
+{
+{ // block
+return (reg & mask) / (mask & ~((mask << 1ULL)));
+} // block
+}
+
+etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
+{
+{ // block
+return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
+} // block
+}
+
+etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val)
+{
+{ // block
+if (!(val)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint8 res = 0ULL;
+if ((val << 32ULL) == 0ULL) { // conditional
+{ // block
+res = res + 32ULL;
+val = val >> 32ULL;
+} // block
+} // conditional
+if ((val << 48ULL) == 0ULL) { // conditional
+{ // block
+res = res + 16ULL;
+val = val >> 16ULL;
+} // block
+} // conditional
+if ((val << 56ULL) == 0ULL) { // conditional
+{ // block
+res = res + 8ULL;
+val = val >> 8ULL;
+} // block
+} // conditional
+if ((val << 60ULL) == 0ULL) { // conditional
+{ // block
+res = res + 4ULL;
+val = val >> 4ULL;
+} // block
+} // conditional
+if ((val << 62ULL) == 0ULL) { // conditional
+{ // block
+res = res + 2ULL;
+val = val >> 2ULL;
+} // block
+} // conditional
+if ((val << 63ULL) == 0ULL) { // conditional
+{ // block
+res = res + 1ULL;
+val = val >> 1ULL;
+} // block
+} // conditional
+return res;
+} // block
+}
+
+void RV32IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause)
+{
+cpu->return_pending = 1;
+cpu->exception = 0;
+{ // block
+etiss_uint32 epc = cpu->instructionPointer;
+etiss_uint32 deleg = 0ULL;
+etiss_uint32 vector = 0ULL;
+etiss_uint32 bit = mcause;
+etiss_int32 irq2 = (mcause & 2147483648ULL) != 0ULL;
+if (irq2) { // conditional
+{ // block
+deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[771LL]) : (0ULL);
+bit = bit & 2147483647ULL;
+} // block
+} // conditional
+else { // conditional
+{ // block
+deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[770LL]) : (0ULL);
+} // block
+} // conditional
+if (((RV32IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
+{ // block
+vector = ((*((RV32IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
+*((RV32IMACFD*)cpu)->CSR[321LL] = epc;
+*((RV32IMACFD*)cpu)->CSR[322LL] = mcause;
+etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);
+s = RV32IMACFD_set_field(s, 32LL, RV32IMACFD_get_field(s, 2LL));
+s = RV32IMACFD_set_field(s, 256LL, ((RV32IMACFD*)cpu)->PRIV);
+s = RV32IMACFD_set_field(s, 2LL, 0ULL);
+RV32IMACFD_csr_write(cpu, system, plugin_pointers, 256LL, s);
+((RV32IMACFD*)cpu)->PRIV = (1LL) & 0x7;
+} // block
+} // conditional
+else { // conditional
+{ // block
+vector = ((*((RV32IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
+*((RV32IMACFD*)cpu)->CSR[833LL] = epc;
+*((RV32IMACFD*)cpu)->CSR[834LL] = mcause;
+etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);
+s = RV32IMACFD_set_field(s, 128LL, RV32IMACFD_get_field(s, 8LL));
+s = RV32IMACFD_set_field(s, 6144LL, ((RV32IMACFD*)cpu)->PRIV);
+s = RV32IMACFD_set_field(s, 8LL, 0ULL);
+RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);
+((RV32IMACFD*)cpu)->PRIV = (3LL) & 0x7;
+} // block
+} // conditional
+} // block
+}
+
+void RV32IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
+{
+{ // block
+etiss_uint32 code = 0ULL;
+if (cause == -2147483648LL) { // conditional
+return;
+} // conditional
+ else if (cause == -5LL) { // conditional
+code = 5LL;
+} // conditional
+ else if (cause == -14LL) { // conditional
+code = 13LL;
+} // conditional
+ else if (cause == -6LL) { // conditional
+code = 7LL;
+} // conditional
+ else if (cause == -15LL) { // conditional
+code = 15LL;
+} // conditional
+ else if (cause == -7LL) { // conditional
+code = 1LL;
+} // conditional
+ else if (cause == -9LL) { // conditional
+{ // block
+code = RV32IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
+if (!(code)) { // conditional
+return;
+} // conditional
+} // block
+} // conditional
+else { // conditional
+code = 2LL;
+} // conditional
+RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, code);
+} // block
+}
+
+etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 pending_interrupts = *((RV32IMACFD*)cpu)->CSR[772LL] & *((RV32IMACFD*)cpu)->CSR[836LL];
+if (!(pending_interrupts)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint32 mie = RV32IMACFD_get_field(*((RV32IMACFD*)cpu)->CSR[768LL], 8LL);
+etiss_uint32 m_enabled = ((RV32IMACFD*)cpu)->PRIV < 3LL || (((RV32IMACFD*)cpu)->PRIV == 3LL && mie);
+etiss_uint32 enabled_interrupts = pending_interrupts & ~(*((RV32IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
+if (enabled_interrupts == 0ULL) { // conditional
+{ // block
+etiss_uint32 deleg = *((RV32IMACFD*)cpu)->CSR[771LL];
+etiss_uint32 sie = RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
+etiss_uint32 s_enabled = ((RV32IMACFD*)cpu)->PRIV < 1LL || (((RV32IMACFD*)cpu)->PRIV == 1LL && sie);
+enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
+} // block
+} // conditional
+if (enabled_interrupts) { // conditional
+{ // block
+if (enabled_interrupts >> 12ULL) { // conditional
+enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
+} // conditional
+ else if (enabled_interrupts & 2048LL) { // conditional
+enabled_interrupts = 2048LL;
+} // conditional
+ else if (enabled_interrupts & 8LL) { // conditional
+enabled_interrupts = 8LL;
+} // conditional
+ else if (enabled_interrupts & 128LL) { // conditional
+enabled_interrupts = 128LL;
+} // conditional
+ else if (enabled_interrupts & 512LL) { // conditional
+enabled_interrupts = 512LL;
+} // conditional
+ else if (enabled_interrupts & 2LL) { // conditional
+enabled_interrupts = 2LL;
+} // conditional
+ else if (enabled_interrupts & 32LL) { // conditional
+enabled_interrupts = 32LL;
+} // conditional
+ else if (enabled_interrupts & 8192LL) { // conditional
+enabled_interrupts = 8192LL;
+} // conditional
+ else if (enabled_interrupts & 1024LL) { // conditional
+enabled_interrupts = 1024LL;
+} // conditional
+ else if (enabled_interrupts & 4LL) { // conditional
+enabled_interrupts = 4LL;
+} // conditional
+ else if (enabled_interrupts & 64LL) { // conditional
+enabled_interrupts = 64LL;
+} // conditional
+else { // conditional
+return 0ULL;
+} // conditional
+return 2147483648ULL | RV32IMACFD_ctz(enabled_interrupts);
+} // block
+} // conditional
+return 0ULL;
+} // block
+}
+
+void RV32IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 irq_mcause = RV32IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
+if (irq_mcause) { // conditional
+RV32IMACFD_raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
+} // conditional
+} // block
+}
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index db0f8900c5..f3384d6883 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,449 +1,118 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
- * This file contains the function macros for the RV32IMACFD core architecture.
+ * This file contains the function prototypes for the RV32IMACFD core architecture.
  */
 
 #ifndef __RV32IMACFD_FUNCS_H
 #define __RV32IMACFD_FUNCS_H
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-#include "Arch/RV32IMACFD/RV32IMACFD.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "RV32IMACFD.h"
 #include "etiss/jit/CPU.h"
 #include "etiss/jit/System.h"
 #include "etiss/jit/ReturnCode.h"
-#endif
-
-
-
-extern void leave(etiss_int32 priv_lvl);
-
-extern void wait(etiss_int32 flag);
-
-static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
-
-extern etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
-
-extern etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
-
-extern etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
-
-extern etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
-
-extern etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
-
-extern etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
-extern etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
+void leave(etiss_int32 priv_lvl);
 
-extern etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
+void wait(etiss_int32 flag);
 
-extern etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
 
-extern etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 unbox_s(etiss_uint64);
+etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fclass_s(etiss_uint32);
+etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fget_flags();
+etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
+etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
-extern etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
-extern etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
+etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
+etiss_uint32 unbox_s(etiss_uint64);
 
-extern etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
+etiss_uint32 fclass_s(etiss_uint32);
 
-extern etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint32 fget_flags();
 
-extern etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
+etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
 
-extern etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
+etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 unbox_d(etiss_uint64);
+etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fclass_d(etiss_uint64);
+etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 etiss_get_time();
+etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
 
-static inline etiss_uint32 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
 
-static inline etiss_uint32 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
 
-static inline etiss_uint32 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
+etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
 
-static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val);
+etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
 
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask);
+etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
 
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
+etiss_uint64 unbox_d(etiss_uint64);
 
-static inline etiss_uint8 ctz(etiss_uint64 val);
+etiss_uint64 fclass_d(etiss_uint64);
 
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause);
+etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
+etiss_uint64 etiss_get_time();
 
-static inline etiss_uint32 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-extern etiss_uint8 etiss_semihost_enabled();
+etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
+etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
 
-static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
-{
-{ // block
-return (*((RV32IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
-} // block
-}
+void RV32IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val);
 
-static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
-{
-{ // block
-if (rm == 7ULL) { // conditional
-rm = ((((((RV32IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7;
-} // conditional
-if (rm > 4ULL) { // conditional
-raise(cpu, system, plugin_pointers, 0ULL, 2LL);
-} // conditional
-return rm;
-} // block
-}
+etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask);
 
-static inline etiss_uint32 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint32 mask = 0ULL;
-if (extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
-{ // block
-mask = mask | 5767458ULL;
-if (extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
-mask = mask | 1536LL;
-} // conditional
-if (extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
-mask = mask | 24576LL;
-} // conditional
-if (extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
-mask = mask | 98304LL;
-} // conditional
-if ((get_field(*((RV32IMACFD*)cpu)->CSR[384LL], 2147483648ULL))) { // conditional
-mask = mask | 262144LL;
-} // conditional
-} // block
-} // conditional
-return mask;
-} // block
-}
+etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
 
-static inline etiss_uint32 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint32 mask = 6280ULL;
-return mask | sstatus_mask(cpu, system, plugin_pointers);
-} // block
-}
+etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val);
 
-static inline etiss_uint32 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
-{
-{ // block
-if (csr == 1LL) { // conditional
-return *((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL;
-} // conditional
-if (csr == 2LL) { // conditional
-return (*((RV32IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
-} // conditional
-if (csr == 3072LL) { // conditional
-return etiss_get_cycles(cpu, system, plugin_pointers);
-} // conditional
-if (csr == 3200LL) { // conditional
-return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
-} // conditional
-if (csr == 3073LL) { // conditional
-return etiss_get_time();
-} // conditional
-if (csr == 3201LL) { // conditional
-return etiss_get_time() >> 32ULL;
-} // conditional
-if (csr == 3074LL) { // conditional
-return etiss_get_instret(cpu, system, plugin_pointers);
-} // conditional
-if (csr == 3202LL) { // conditional
-return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
-} // conditional
-if (csr == 768LL || csr == 256LL) { // conditional
-return *((RV32IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
-} // conditional
-if (csr == 769LL) { // conditional
-return (((1ULL) << 30) | ((((*((RV32IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 1073741823)));
-} // conditional
-return *((RV32IMACFD*)cpu)->CSR[csr];
-} // block
-}
-
-static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
-{
-{ // block
-if (csr == 1LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[3LL] = (*((RV32IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
-} // conditional
- else if (csr == 2LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL);
-} // conditional
- else if (csr == 3LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
-} // conditional
- else if (csr == 768LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[768LL] = val & mstatus_mask(cpu, system, plugin_pointers);
-} // conditional
- else if (csr == 256LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[768LL] = val & sstatus_mask(cpu, system, plugin_pointers);
-} // conditional
- else if (csr != 769LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[csr] = val;
-} // conditional
-} // block
-}
+void RV32IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause);
 
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
-{
-{ // block
-return (reg & mask) / (mask & ~((mask << 1ULL)));
-} // block
-}
+void RV32IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
 
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
-{
-{ // block
-return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
-} // block
-}
+etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline etiss_uint8 ctz(etiss_uint64 val)
-{
-{ // block
-if (!(val)) { // conditional
-return 0ULL;
-} // conditional
-etiss_uint8 res = 0ULL;
-if ((val << 32ULL) == 0ULL) { // conditional
-{ // block
-res = res + 32ULL;
-val = val >> 32ULL;
-} // block
-} // conditional
-if ((val << 48ULL) == 0ULL) { // conditional
-{ // block
-res = res + 16ULL;
-val = val >> 16ULL;
-} // block
-} // conditional
-if ((val << 56ULL) == 0ULL) { // conditional
-{ // block
-res = res + 8ULL;
-val = val >> 8ULL;
-} // block
-} // conditional
-if ((val << 60ULL) == 0ULL) { // conditional
-{ // block
-res = res + 4ULL;
-val = val >> 4ULL;
-} // block
-} // conditional
-if ((val << 62ULL) == 0ULL) { // conditional
-{ // block
-res = res + 2ULL;
-val = val >> 2ULL;
-} // block
-} // conditional
-if ((val << 63ULL) == 0ULL) { // conditional
-{ // block
-res = res + 1ULL;
-val = val >> 1ULL;
-} // block
-} // conditional
-return res;
-} // block
-}
+void RV32IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause)
-{
-cpu->return_pending = 1;
-cpu->exception = 0;
-{ // block
-etiss_uint32 epc = cpu->instructionPointer;
-etiss_uint32 deleg = 0ULL;
-etiss_uint32 vector = 0ULL;
-etiss_uint32 bit = mcause;
-etiss_int32 irq2 = (mcause & 2147483648ULL) != 0ULL;
-if (irq2) { // conditional
-{ // block
-deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[771LL]) : (0ULL);
-bit = bit & 2147483647ULL;
-} // block
-} // conditional
-else { // conditional
-{ // block
-deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[770LL]) : (0ULL);
-} // block
-} // conditional
-if (((RV32IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
-{ // block
-vector = ((*((RV32IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
-cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
-*((RV32IMACFD*)cpu)->CSR[321LL] = epc;
-*((RV32IMACFD*)cpu)->CSR[322LL] = mcause;
-etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 256LL);
-s = set_field(s, 32LL, get_field(s, 2LL));
-s = set_field(s, 256LL, ((RV32IMACFD*)cpu)->PRIV);
-s = set_field(s, 2LL, 0ULL);
-csr_write(cpu, system, plugin_pointers, 256LL, s);
-((RV32IMACFD*)cpu)->PRIV = (1LL) & 0x7;
-} // block
-} // conditional
-else { // conditional
-{ // block
-vector = ((*((RV32IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
-cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
-*((RV32IMACFD*)cpu)->CSR[833LL] = epc;
-*((RV32IMACFD*)cpu)->CSR[834LL] = mcause;
-etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 768LL);
-s = set_field(s, 128LL, get_field(s, 8LL));
-s = set_field(s, 6144LL, ((RV32IMACFD*)cpu)->PRIV);
-s = set_field(s, 8LL, 0ULL);
-csr_write(cpu, system, plugin_pointers, 768LL, s);
-((RV32IMACFD*)cpu)->PRIV = (3LL) & 0x7;
-} // block
-} // conditional
-} // block
-}
+etiss_uint8 etiss_semihost_enabled();
 
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
-{
-{ // block
-etiss_uint32 code = 0ULL;
-if (cause == -2147483648LL) { // conditional
-return;
-} // conditional
- else if (cause == -5LL) { // conditional
-code = 5LL;
-} // conditional
- else if (cause == -14LL) { // conditional
-code = 13LL;
-} // conditional
- else if (cause == -6LL) { // conditional
-code = 7LL;
-} // conditional
- else if (cause == -15LL) { // conditional
-code = 15LL;
-} // conditional
- else if (cause == -7LL) { // conditional
-code = 1LL;
-} // conditional
- else if (cause == -9LL) { // conditional
-{ // block
-code = calc_irq_mcause(cpu, system, plugin_pointers);
-if (!(code)) { // conditional
-return;
-} // conditional
-} // block
-} // conditional
-else { // conditional
-code = 2LL;
-} // conditional
-raise(cpu, system, plugin_pointers, 0ULL, code);
-} // block
-}
+etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
 
-static inline etiss_uint32 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint32 pending_interrupts = *((RV32IMACFD*)cpu)->CSR[772LL] & *((RV32IMACFD*)cpu)->CSR[836LL];
-if (!(pending_interrupts)) { // conditional
-return 0ULL;
-} // conditional
-etiss_uint32 mie = get_field(*((RV32IMACFD*)cpu)->CSR[768LL], 8LL);
-etiss_uint32 m_enabled = ((RV32IMACFD*)cpu)->PRIV < 3LL || (((RV32IMACFD*)cpu)->PRIV == 3LL && mie);
-etiss_uint32 enabled_interrupts = pending_interrupts & ~(*((RV32IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
-if (enabled_interrupts == 0ULL) { // conditional
-{ // block
-etiss_uint32 deleg = *((RV32IMACFD*)cpu)->CSR[771LL];
-etiss_uint32 sie = get_field(csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
-etiss_uint32 s_enabled = ((RV32IMACFD*)cpu)->PRIV < 1LL || (((RV32IMACFD*)cpu)->PRIV == 1LL && sie);
-enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
-} // block
-} // conditional
-if (enabled_interrupts) { // conditional
-{ // block
-if (enabled_interrupts >> 12ULL) { // conditional
-enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
-} // conditional
- else if (enabled_interrupts & 2048LL) { // conditional
-enabled_interrupts = 2048LL;
-} // conditional
- else if (enabled_interrupts & 8LL) { // conditional
-enabled_interrupts = 8LL;
-} // conditional
- else if (enabled_interrupts & 128LL) { // conditional
-enabled_interrupts = 128LL;
-} // conditional
- else if (enabled_interrupts & 512LL) { // conditional
-enabled_interrupts = 512LL;
-} // conditional
- else if (enabled_interrupts & 2LL) { // conditional
-enabled_interrupts = 2LL;
-} // conditional
- else if (enabled_interrupts & 32LL) { // conditional
-enabled_interrupts = 32LL;
-} // conditional
- else if (enabled_interrupts & 8192LL) { // conditional
-enabled_interrupts = 8192LL;
-} // conditional
- else if (enabled_interrupts & 1024LL) { // conditional
-enabled_interrupts = 1024LL;
-} // conditional
- else if (enabled_interrupts & 4LL) { // conditional
-enabled_interrupts = 4LL;
-} // conditional
- else if (enabled_interrupts & 64LL) { // conditional
-enabled_interrupts = 64LL;
-} // conditional
-else { // conditional
-return 0ULL;
-} // conditional
-return 2147483648ULL | ctz(enabled_interrupts);
-} // block
-} // conditional
-return 0ULL;
-} // block
+#ifdef __cplusplus
 }
+#endif
 
-static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint32 irq_mcause = calc_irq_mcause(cpu, system, plugin_pointers);
-if (irq_mcause) { // conditional
-raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
-} // conditional
-} // block
-}
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
index bb5746e691..1e42f39f63 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the GDBCore adapter for the RV32IMACFD core architecture.
  *
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
index 95800ae5b6..60576e12cf 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index 20c7af819a..d8a50954a9 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -66,7 +64,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -79,7 +77,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -184,7 +182,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -200,7 +198,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -305,7 +303,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -321,7 +319,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -426,7 +424,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -442,7 +440,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -547,7 +545,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -563,7 +561,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -668,7 +666,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -684,7 +682,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -789,7 +787,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -805,7 +803,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -910,7 +908,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -926,7 +924,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1031,7 +1029,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1047,7 +1045,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index c7ddf3544f..a1acf2aa56 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -61,7 +59,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -161,7 +159,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -257,7 +255,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -353,7 +351,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index cff92b29bc..8434b8ecec 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -59,7 +57,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -157,7 +155,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -252,7 +250,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -341,7 +339,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -430,7 +428,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -519,7 +517,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -605,7 +603,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -688,7 +686,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -771,7 +769,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -854,7 +852,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -934,7 +932,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 66e2f948c1..863c4896c6 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -63,7 +61,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -171,7 +169,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -269,7 +267,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -369,7 +367,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 46c8d33eaa..b6b3fd8fb2 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -59,7 +57,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -161,7 +159,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -258,7 +256,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -351,7 +349,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -447,7 +445,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -543,7 +541,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -635,7 +633,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -724,7 +722,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -813,7 +811,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -902,7 +900,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -987,7 +985,7 @@ cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsqrt_s(frs1, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fsqrt_s(frs1, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index c5a9542d72..4dd344a5a1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -60,7 +58,7 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -158,7 +156,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -261,7 +259,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_ad
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -663,7 +661,7 @@ cp.code() += "{ // block\n";
 if (imm == 0ULL) { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -758,7 +756,7 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[2ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " +
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -839,7 +837,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1755,7 +1753,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32I
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1768,7 +1766,7 @@ cp.code() += "} // block\n";
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1920,7 +1918,7 @@ cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32UL
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1990,7 +1988,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2195,7 +2193,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2276,7 +2274,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2353,7 +2351,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 5e286283c2..a99c4d2e67 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -193,7 +191,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -301,7 +299,7 @@ cp.code() += "if (new_pc % 2ULL) { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -414,7 +412,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -533,7 +531,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -652,7 +650,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -771,7 +769,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -890,7 +888,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1009,7 +1007,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1120,7 +1118,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1217,7 +1215,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1314,7 +1312,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1411,7 +1409,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1508,7 +1506,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1608,7 +1606,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1706,7 +1704,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1804,7 +1802,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index 18d4ba3e48..15bfe3c3bb 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index 069792cd9b..f33616333d 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index c045d9ea3c..4fb08933b4 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -57,8 +55,8 @@ cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1
 if ((rd % 32ULL) != 0ULL) { // conditional
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
 cp.code() += "} // block\n";
 } // block
@@ -66,7 +64,7 @@ cp.code() += "} // block\n";
 else { // conditional
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
 cp.code() += "} // block\n";
 } // block
 } // conditional
@@ -143,10 +141,10 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 if (rs1 != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -224,10 +222,10 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 if (rs1 != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -305,8 +303,8 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
 } // conditional
@@ -383,9 +381,9 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 if (zimm != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -463,9 +461,9 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 if (zimm != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "ULL);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "ULL);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 06f64048f1..4dc2310a0b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -46,7 +44,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -117,21 +115,21 @@ cp.code() += "{ // block\n";
 cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
 cp.code() += "} // conditional\n";
 cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833LL];\n";
-cp.code() += "etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 768LL);\n";
-cp.code() += "etiss_uint32 prev_prv = get_field(s, 6144LL);\n";
+cp.code() += "etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";
+cp.code() += "etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 6144LL);\n";
 cp.code() += "if (prev_prv != 3LL) { // conditional\n";
-cp.code() += "s = set_field(s, 131072LL, 0ULL);\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 131072LL, 0ULL);\n";
 cp.code() += "} // conditional\n";
-cp.code() += "s = set_field(s, 8LL, get_field(s, 128LL));\n";
-cp.code() += "s = set_field(s, 128LL, 1ULL);\n";
-cp.code() += "s = set_field(s, 6144LL, (extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 8LL, RV32IMACFD_get_field(s, 128LL));\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 128LL, 1ULL);\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 6144LL, (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
 cp.code() += "} // block\n";
 } // block
@@ -261,21 +259,21 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((get_field(csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
+cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
 cp.code() += "} // conditional\n";
 cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321LL];\n";
-cp.code() += "etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 256LL);\n";
-cp.code() += "etiss_uint32 prev_prv = get_field(s, 256LL);\n";
-cp.code() += "s = set_field(s, 2LL, get_field(s, 32LL));\n";
-cp.code() += "s = set_field(s, 32LL, 1ULL);\n";
-cp.code() += "s = set_field(s, 256LL, 0LL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
+cp.code() += "etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";
+cp.code() += "etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 256LL);\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 2LL, RV32IMACFD_get_field(s, 32LL));\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 32LL, 1ULL);\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 256LL, 0LL);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
 cp.code() += "} // block\n";
 } // block
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 363476b4df..dced7d903e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -62,7 +60,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -171,7 +169,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index 2aceb3f379..bb39c1fec5 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -52,7 +50,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -63,7 +61,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -74,7 +72,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -94,7 +92,7 @@ cp.code() += "else { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -109,7 +107,7 @@ cp.code() += "else { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt
index 5293cbb995..3a43d02b6e 100644
--- a/ArchImpl/RV64IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV64IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+# Generated on Fri, 03 Nov 2023 13:22:23 +0100.
 #
 # This file contains the CMake build info for the RV64IMACFD core architecture.
 
@@ -11,6 +11,7 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV64IMACFDArch.cpp
 	RV64IMACFDArchLib.cpp
 	RV64IMACFDArchSpecificImp.cpp
+	RV64IMACFDFuncs.c
 	RV64IMACFDInstr.cpp
 	RV64IMACFD_RV32IInstr.cpp
 	RV64IMACFD_RV64IInstr.cpp
@@ -30,6 +31,7 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV64IMACFD_tum_retInstr.cpp
 	RV64IMACFD_tum_rvaInstr.cpp
 	RV64IMACFD_tum_rva64Instr.cpp
+	RV64IMACFD_tum_rvmInstr.cpp
 	RV64IMACFD_tum_semihostingInstr.cpp
 )
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD.h b/ArchImpl/RV64IMACFD/RV64IMACFD.h
index d88be9a2d7..13349104f5 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the registers for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
index 3876c0ec1f..a2292b9aa8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */
@@ -35,8 +35,6 @@
  *********************************************************************************************************************************/
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 #define RV64IMACFD_DEBUG_CALL 0
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
index 5abf67a078..461a1d6b1b 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
index ae653db6e9..1c05bd91d9 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the library interface for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
index 29ce558a57..0a32ab8dd8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture specific implementation for the RV64IMACFD
  * core architecture.
@@ -12,11 +12,8 @@
 
 #include "RV64IMACFDArch.h"
 #include "RV64IMACFDArchSpecificImp.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
-extern "C" {
 #include "RV64IMACFDFuncs.h"
-}
+
 /**
 	@brief This function will be called automatically in order to handling exceptions such as interrupt, system call, illegal instructions
 
@@ -33,9 +30,8 @@ extern "C" {
 */
 etiss::int32 RV64IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu)
 {
-	translate_exc_code(cpu, nullptr, nullptr, cause);
+	RV64IMACFD_translate_exc_code(cpu, nullptr, nullptr, cause);
 	cpu->instructionPointer = cpu->nextPc;
-
 	return 0;
 }
 
@@ -125,7 +121,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -172,7 +168,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
index 64d12881f8..8b94f7a27d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture specific header for the RV64IMACFD
  * core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c
new file mode 100644
index 0000000000..d42498b9b2
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c
@@ -0,0 +1,368 @@
+/**
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ *
+ * This file contains the function implementations for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDFuncs.h"
+
+etiss_uint8 RV64IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
+{
+{ // block
+return (*((RV64IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
+} // block
+}
+
+etiss_uint8 RV64IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
+{
+{ // block
+if (rm == 7ULL) { // conditional
+rm = ((((((RV64IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7;
+} // conditional
+if (rm > 4ULL) { // conditional
+RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);
+} // conditional
+return rm;
+} // block
+}
+
+etiss_uint64 RV64IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 mask = 0ULL;
+if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
+{ // block
+mask = mask | 5767458ULL;
+if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
+mask = mask | 1536LL;
+} // conditional
+if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
+mask = mask | 24576LL;
+} // conditional
+if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
+mask = mask | 98304LL;
+} // conditional
+if ((RV64IMACFD_get_field(*((RV64IMACFD*)cpu)->CSR[384LL], 17293822569102704640ULL))) { // conditional
+mask = mask | 262144LL;
+} // conditional
+} // block
+} // conditional
+return mask;
+} // block
+}
+
+etiss_uint64 RV64IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 mask = 6280ULL;
+return mask | RV64IMACFD_sstatus_mask(cpu, system, plugin_pointers);
+} // block
+}
+
+etiss_uint64 RV64IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
+{
+{ // block
+if (csr == 1LL) { // conditional
+return *((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL;
+} // conditional
+if (csr == 2LL) { // conditional
+return (*((RV64IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
+} // conditional
+if (csr == 3072LL) { // conditional
+return etiss_get_cycles(cpu, system, plugin_pointers);
+} // conditional
+if (csr == 3200LL) { // conditional
+return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 3073LL) { // conditional
+return etiss_get_time();
+} // conditional
+if (csr == 3201LL) { // conditional
+return etiss_get_time() >> 32ULL;
+} // conditional
+if (csr == 3074LL) { // conditional
+return etiss_get_instret(cpu, system, plugin_pointers);
+} // conditional
+if (csr == 3202LL) { // conditional
+return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 768LL || csr == 256LL) { // conditional
+return *((RV64IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
+} // conditional
+if (csr == 769LL) { // conditional
+return (((2ULL) << 62) | ((((*((RV64IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 4611686018427387903)));
+} // conditional
+return *((RV64IMACFD*)cpu)->CSR[csr];
+} // block
+}
+
+void RV64IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val)
+{
+{ // block
+if (csr == 1LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[3LL] = (*((RV64IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
+} // conditional
+ else if (csr == 2LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL);
+} // conditional
+ else if (csr == 3LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
+} // conditional
+ else if (csr == 768LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[768LL] = val & RV64IMACFD_mstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr == 256LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[768LL] = val & RV64IMACFD_sstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr != 769LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[csr] = val;
+} // conditional
+} // block
+}
+
+etiss_uint64 RV64IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
+{
+{ // block
+return (reg & mask) / (mask & ~((mask << 1ULL)));
+} // block
+}
+
+etiss_uint64 RV64IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
+{
+{ // block
+return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
+} // block
+}
+
+etiss_uint8 RV64IMACFD_ctz(etiss_uint64 val)
+{
+{ // block
+if (!(val)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint8 res = 0ULL;
+if ((val << 32ULL) == 0ULL) { // conditional
+{ // block
+res = res + 32ULL;
+val = val >> 32ULL;
+} // block
+} // conditional
+if ((val << 48ULL) == 0ULL) { // conditional
+{ // block
+res = res + 16ULL;
+val = val >> 16ULL;
+} // block
+} // conditional
+if ((val << 56ULL) == 0ULL) { // conditional
+{ // block
+res = res + 8ULL;
+val = val >> 8ULL;
+} // block
+} // conditional
+if ((val << 60ULL) == 0ULL) { // conditional
+{ // block
+res = res + 4ULL;
+val = val >> 4ULL;
+} // block
+} // conditional
+if ((val << 62ULL) == 0ULL) { // conditional
+{ // block
+res = res + 2ULL;
+val = val >> 2ULL;
+} // block
+} // conditional
+if ((val << 63ULL) == 0ULL) { // conditional
+{ // block
+res = res + 1ULL;
+val = val >> 1ULL;
+} // block
+} // conditional
+return res;
+} // block
+}
+
+void RV64IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause)
+{
+cpu->return_pending = 1;
+cpu->exception = 0;
+{ // block
+etiss_uint64 epc = cpu->instructionPointer;
+etiss_uint64 deleg = 0ULL;
+etiss_uint64 vector = 0ULL;
+etiss_uint64 bit = mcause;
+etiss_int32 irq2 = (mcause & 9223372036854775808ULL) != 0ULL;
+if (irq2) { // conditional
+{ // block
+deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[771LL]) : (0ULL);
+bit = bit & 9223372036854775807ULL;
+} // block
+} // conditional
+else { // conditional
+{ // block
+deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[770LL]) : (0ULL);
+} // block
+} // conditional
+if (((RV64IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
+{ // block
+vector = ((*((RV64IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
+*((RV64IMACFD*)cpu)->CSR[321LL] = epc;
+*((RV64IMACFD*)cpu)->CSR[322LL] = mcause;
+etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);
+s = RV64IMACFD_set_field(s, 32LL, RV64IMACFD_get_field(s, 2LL));
+s = RV64IMACFD_set_field(s, 256LL, ((RV64IMACFD*)cpu)->PRIV);
+s = RV64IMACFD_set_field(s, 2LL, 0ULL);
+RV64IMACFD_csr_write(cpu, system, plugin_pointers, 256LL, s);
+((RV64IMACFD*)cpu)->PRIV = (1LL) & 0x7;
+} // block
+} // conditional
+else { // conditional
+{ // block
+vector = ((*((RV64IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
+*((RV64IMACFD*)cpu)->CSR[833LL] = epc;
+*((RV64IMACFD*)cpu)->CSR[834LL] = mcause;
+etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);
+s = RV64IMACFD_set_field(s, 128LL, RV64IMACFD_get_field(s, 8LL));
+s = RV64IMACFD_set_field(s, 6144LL, ((RV64IMACFD*)cpu)->PRIV);
+s = RV64IMACFD_set_field(s, 8LL, 0ULL);
+RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);
+((RV64IMACFD*)cpu)->PRIV = (3LL) & 0x7;
+} // block
+} // conditional
+} // block
+}
+
+void RV64IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
+{
+{ // block
+etiss_uint64 code = 0ULL;
+if (cause == -2147483648LL) { // conditional
+return;
+} // conditional
+ else if (cause == -5LL) { // conditional
+code = 5LL;
+} // conditional
+ else if (cause == -14LL) { // conditional
+code = 13LL;
+} // conditional
+ else if (cause == -6LL) { // conditional
+code = 7LL;
+} // conditional
+ else if (cause == -15LL) { // conditional
+code = 15LL;
+} // conditional
+ else if (cause == -7LL) { // conditional
+code = 1LL;
+} // conditional
+ else if (cause == -9LL) { // conditional
+{ // block
+code = RV64IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
+if (!(code)) { // conditional
+return;
+} // conditional
+} // block
+} // conditional
+else { // conditional
+code = 2LL;
+} // conditional
+RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, code);
+} // block
+}
+
+etiss_uint64 RV64IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 pending_interrupts = *((RV64IMACFD*)cpu)->CSR[772LL] & *((RV64IMACFD*)cpu)->CSR[836LL];
+if (!(pending_interrupts)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint64 mie = RV64IMACFD_get_field(*((RV64IMACFD*)cpu)->CSR[768LL], 8LL);
+etiss_uint64 m_enabled = ((RV64IMACFD*)cpu)->PRIV < 3LL || (((RV64IMACFD*)cpu)->PRIV == 3LL && mie);
+etiss_uint64 enabled_interrupts = pending_interrupts & ~(*((RV64IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
+if (enabled_interrupts == 0ULL) { // conditional
+{ // block
+etiss_uint64 deleg = *((RV64IMACFD*)cpu)->CSR[771LL];
+etiss_uint64 sie = RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
+etiss_uint64 s_enabled = ((RV64IMACFD*)cpu)->PRIV < 1LL || (((RV64IMACFD*)cpu)->PRIV == 1LL && sie);
+enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
+} // block
+} // conditional
+if (enabled_interrupts) { // conditional
+{ // block
+if (enabled_interrupts >> 12ULL) { // conditional
+enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
+} // conditional
+ else if (enabled_interrupts & 2048LL) { // conditional
+enabled_interrupts = 2048LL;
+} // conditional
+ else if (enabled_interrupts & 8LL) { // conditional
+enabled_interrupts = 8LL;
+} // conditional
+ else if (enabled_interrupts & 128LL) { // conditional
+enabled_interrupts = 128LL;
+} // conditional
+ else if (enabled_interrupts & 512LL) { // conditional
+enabled_interrupts = 512LL;
+} // conditional
+ else if (enabled_interrupts & 2LL) { // conditional
+enabled_interrupts = 2LL;
+} // conditional
+ else if (enabled_interrupts & 32LL) { // conditional
+enabled_interrupts = 32LL;
+} // conditional
+ else if (enabled_interrupts & 8192LL) { // conditional
+enabled_interrupts = 8192LL;
+} // conditional
+ else if (enabled_interrupts & 1024LL) { // conditional
+enabled_interrupts = 1024LL;
+} // conditional
+ else if (enabled_interrupts & 4LL) { // conditional
+enabled_interrupts = 4LL;
+} // conditional
+ else if (enabled_interrupts & 64LL) { // conditional
+enabled_interrupts = 64LL;
+} // conditional
+else { // conditional
+return 0ULL;
+} // conditional
+return 9223372036854775808ULL | RV64IMACFD_ctz(enabled_interrupts);
+} // block
+} // conditional
+return 0ULL;
+} // block
+}
+
+void RV64IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 irq_mcause = RV64IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
+if (irq_mcause) { // conditional
+RV64IMACFD_raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
+} // conditional
+} // block
+}
+
+etiss_int64 RV64IMACFD_mulh(etiss_int64 x, etiss_int64 y)
+{
+{ // block
+etiss_int128 res = (etiss_int128)(x) * (etiss_int128)(y);
+return (etiss_int64)((res >> 64ULL));
+} // block
+}
+
+etiss_int64 RV64IMACFD_mulhsu(etiss_int64 x, etiss_uint64 y)
+{
+{ // block
+etiss_int128 res = (etiss_int128)(x) * (etiss_uint128)(y);
+return (etiss_int64)((res >> 64ULL));
+} // block
+}
+
+etiss_uint64 RV64IMACFD_mulhu(etiss_uint64 x, etiss_uint64 y)
+{
+{ // block
+etiss_uint128 res = (etiss_uint128)(x) * (etiss_uint128)(y);
+return (etiss_uint64)((res >> 64ULL));
+} // block
+}
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index 097e662ebe..93fec02cf9 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,449 +1,124 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
- * This file contains the function macros for the RV64IMACFD core architecture.
+ * This file contains the function prototypes for the RV64IMACFD core architecture.
  */
 
 #ifndef __RV64IMACFD_FUNCS_H
 #define __RV64IMACFD_FUNCS_H
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-#include "Arch/RV64IMACFD/RV64IMACFD.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "RV64IMACFD.h"
 #include "etiss/jit/CPU.h"
 #include "etiss/jit/System.h"
 #include "etiss/jit/ReturnCode.h"
-#endif
 
 
+void leave(etiss_int32 priv_lvl);
 
-extern void leave(etiss_int32 priv_lvl);
+void wait(etiss_int32 flag);
 
-extern void wait(etiss_int32 flag);
+etiss_uint8 RV64IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
 
-static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
+etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
-extern etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
+etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
+etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
-extern etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
+etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint32 unbox_s(etiss_uint64);
 
-extern etiss_uint32 unbox_s(etiss_uint64);
+etiss_uint32 fclass_s(etiss_uint32);
 
-extern etiss_uint32 fclass_s(etiss_uint32);
+etiss_uint32 fget_flags();
 
-extern etiss_uint32 fget_flags();
+etiss_uint8 RV64IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
 
-static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
+etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
 
-extern etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
+etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
+etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
 
-extern etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
+etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
 
-extern etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
+etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
+etiss_uint64 unbox_d(etiss_uint64);
 
-extern etiss_uint64 unbox_d(etiss_uint64);
+etiss_uint64 fclass_d(etiss_uint64);
 
-extern etiss_uint64 fclass_d(etiss_uint64);
+etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-extern etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 etiss_get_time();
 
-extern etiss_uint64 etiss_get_time();
+etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-extern etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 RV64IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline etiss_uint64 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 RV64IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline etiss_uint64 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 RV64IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
 
-static inline etiss_uint64 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
+void RV64IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val);
 
-static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val);
+etiss_uint64 RV64IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask);
 
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask);
+etiss_uint64 RV64IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
 
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
+etiss_uint8 RV64IMACFD_ctz(etiss_uint64 val);
 
-static inline etiss_uint8 ctz(etiss_uint64 val);
+void RV64IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause);
 
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause);
+void RV64IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
 
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
+etiss_uint64 RV64IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline etiss_uint64 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+void RV64IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_int64 RV64IMACFD_mulh(etiss_int64 x, etiss_int64 y);
 
-extern etiss_uint8 etiss_semihost_enabled();
+etiss_int64 RV64IMACFD_mulhsu(etiss_int64 x, etiss_uint64 y);
 
-extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
+etiss_uint64 RV64IMACFD_mulhu(etiss_uint64 x, etiss_uint64 y);
 
-static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
-{
-{ // block
-return (*((RV64IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
-} // block
-}
+etiss_uint8 etiss_semihost_enabled();
 
-static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
-{
-{ // block
-if (rm == 7ULL) { // conditional
-rm = ((((((RV64IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7;
-} // conditional
-if (rm > 4ULL) { // conditional
-raise(cpu, system, plugin_pointers, 0ULL, 2LL);
-} // conditional
-return rm;
-} // block
-}
-
-static inline etiss_uint64 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint64 mask = 0ULL;
-if (extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
-{ // block
-mask = mask | 5767458ULL;
-if (extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
-mask = mask | 1536LL;
-} // conditional
-if (extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
-mask = mask | 24576LL;
-} // conditional
-if (extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
-mask = mask | 98304LL;
-} // conditional
-if ((get_field(*((RV64IMACFD*)cpu)->CSR[384LL], 17293822569102704640ULL))) { // conditional
-mask = mask | 262144LL;
-} // conditional
-} // block
-} // conditional
-return mask;
-} // block
-}
-
-static inline etiss_uint64 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint64 mask = 6280ULL;
-return mask | sstatus_mask(cpu, system, plugin_pointers);
-} // block
-}
-
-static inline etiss_uint64 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
-{
-{ // block
-if (csr == 1LL) { // conditional
-return *((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL;
-} // conditional
-if (csr == 2LL) { // conditional
-return (*((RV64IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
-} // conditional
-if (csr == 3072LL) { // conditional
-return etiss_get_cycles(cpu, system, plugin_pointers);
-} // conditional
-if (csr == 3200LL) { // conditional
-return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
-} // conditional
-if (csr == 3073LL) { // conditional
-return etiss_get_time();
-} // conditional
-if (csr == 3201LL) { // conditional
-return etiss_get_time() >> 32ULL;
-} // conditional
-if (csr == 3074LL) { // conditional
-return etiss_get_instret(cpu, system, plugin_pointers);
-} // conditional
-if (csr == 3202LL) { // conditional
-return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
-} // conditional
-if (csr == 768LL || csr == 256LL) { // conditional
-return *((RV64IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
-} // conditional
-if (csr == 769LL) { // conditional
-return (((2ULL) << 62) | ((((*((RV64IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 4611686018427387903)));
-} // conditional
-return *((RV64IMACFD*)cpu)->CSR[csr];
-} // block
-}
-
-static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val)
-{
-{ // block
-if (csr == 1LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[3LL] = (*((RV64IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
-} // conditional
- else if (csr == 2LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL);
-} // conditional
- else if (csr == 3LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
-} // conditional
- else if (csr == 768LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[768LL] = val & mstatus_mask(cpu, system, plugin_pointers);
-} // conditional
- else if (csr == 256LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[768LL] = val & sstatus_mask(cpu, system, plugin_pointers);
-} // conditional
- else if (csr != 769LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[csr] = val;
-} // conditional
-} // block
-}
+etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
 
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
-{
-{ // block
-return (reg & mask) / (mask & ~((mask << 1ULL)));
-} // block
-}
-
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
-{
-{ // block
-return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
-} // block
-}
-
-static inline etiss_uint8 ctz(etiss_uint64 val)
-{
-{ // block
-if (!(val)) { // conditional
-return 0ULL;
-} // conditional
-etiss_uint8 res = 0ULL;
-if ((val << 32ULL) == 0ULL) { // conditional
-{ // block
-res = res + 32ULL;
-val = val >> 32ULL;
-} // block
-} // conditional
-if ((val << 48ULL) == 0ULL) { // conditional
-{ // block
-res = res + 16ULL;
-val = val >> 16ULL;
-} // block
-} // conditional
-if ((val << 56ULL) == 0ULL) { // conditional
-{ // block
-res = res + 8ULL;
-val = val >> 8ULL;
-} // block
-} // conditional
-if ((val << 60ULL) == 0ULL) { // conditional
-{ // block
-res = res + 4ULL;
-val = val >> 4ULL;
-} // block
-} // conditional
-if ((val << 62ULL) == 0ULL) { // conditional
-{ // block
-res = res + 2ULL;
-val = val >> 2ULL;
-} // block
-} // conditional
-if ((val << 63ULL) == 0ULL) { // conditional
-{ // block
-res = res + 1ULL;
-val = val >> 1ULL;
-} // block
-} // conditional
-return res;
-} // block
-}
-
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause)
-{
-cpu->return_pending = 1;
-cpu->exception = 0;
-{ // block
-etiss_uint64 epc = cpu->instructionPointer;
-etiss_uint64 deleg = 0ULL;
-etiss_uint64 vector = 0ULL;
-etiss_uint64 bit = mcause;
-etiss_int32 irq2 = (mcause & 9223372036854775808ULL) != 0ULL;
-if (irq2) { // conditional
-{ // block
-deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[771LL]) : (0ULL);
-bit = bit & 9223372036854775807ULL;
-} // block
-} // conditional
-else { // conditional
-{ // block
-deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[770LL]) : (0ULL);
-} // block
-} // conditional
-if (((RV64IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
-{ // block
-vector = ((*((RV64IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
-cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
-*((RV64IMACFD*)cpu)->CSR[321LL] = epc;
-*((RV64IMACFD*)cpu)->CSR[322LL] = mcause;
-etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 256LL);
-s = set_field(s, 32LL, get_field(s, 2LL));
-s = set_field(s, 256LL, ((RV64IMACFD*)cpu)->PRIV);
-s = set_field(s, 2LL, 0ULL);
-csr_write(cpu, system, plugin_pointers, 256LL, s);
-((RV64IMACFD*)cpu)->PRIV = (1LL) & 0x7;
-} // block
-} // conditional
-else { // conditional
-{ // block
-vector = ((*((RV64IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
-cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
-*((RV64IMACFD*)cpu)->CSR[833LL] = epc;
-*((RV64IMACFD*)cpu)->CSR[834LL] = mcause;
-etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 768LL);
-s = set_field(s, 128LL, get_field(s, 8LL));
-s = set_field(s, 6144LL, ((RV64IMACFD*)cpu)->PRIV);
-s = set_field(s, 8LL, 0ULL);
-csr_write(cpu, system, plugin_pointers, 768LL, s);
-((RV64IMACFD*)cpu)->PRIV = (3LL) & 0x7;
-} // block
-} // conditional
-} // block
-}
-
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
-{
-{ // block
-etiss_uint64 code = 0ULL;
-if (cause == -2147483648LL) { // conditional
-return;
-} // conditional
- else if (cause == -5LL) { // conditional
-code = 5LL;
-} // conditional
- else if (cause == -14LL) { // conditional
-code = 13LL;
-} // conditional
- else if (cause == -6LL) { // conditional
-code = 7LL;
-} // conditional
- else if (cause == -15LL) { // conditional
-code = 15LL;
-} // conditional
- else if (cause == -7LL) { // conditional
-code = 1LL;
-} // conditional
- else if (cause == -9LL) { // conditional
-{ // block
-code = calc_irq_mcause(cpu, system, plugin_pointers);
-if (!(code)) { // conditional
-return;
-} // conditional
-} // block
-} // conditional
-else { // conditional
-code = 2LL;
-} // conditional
-raise(cpu, system, plugin_pointers, 0ULL, code);
-} // block
-}
-
-static inline etiss_uint64 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint64 pending_interrupts = *((RV64IMACFD*)cpu)->CSR[772LL] & *((RV64IMACFD*)cpu)->CSR[836LL];
-if (!(pending_interrupts)) { // conditional
-return 0ULL;
-} // conditional
-etiss_uint64 mie = get_field(*((RV64IMACFD*)cpu)->CSR[768LL], 8LL);
-etiss_uint64 m_enabled = ((RV64IMACFD*)cpu)->PRIV < 3LL || (((RV64IMACFD*)cpu)->PRIV == 3LL && mie);
-etiss_uint64 enabled_interrupts = pending_interrupts & ~(*((RV64IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
-if (enabled_interrupts == 0ULL) { // conditional
-{ // block
-etiss_uint64 deleg = *((RV64IMACFD*)cpu)->CSR[771LL];
-etiss_uint64 sie = get_field(csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
-etiss_uint64 s_enabled = ((RV64IMACFD*)cpu)->PRIV < 1LL || (((RV64IMACFD*)cpu)->PRIV == 1LL && sie);
-enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
-} // block
-} // conditional
-if (enabled_interrupts) { // conditional
-{ // block
-if (enabled_interrupts >> 12ULL) { // conditional
-enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
-} // conditional
- else if (enabled_interrupts & 2048LL) { // conditional
-enabled_interrupts = 2048LL;
-} // conditional
- else if (enabled_interrupts & 8LL) { // conditional
-enabled_interrupts = 8LL;
-} // conditional
- else if (enabled_interrupts & 128LL) { // conditional
-enabled_interrupts = 128LL;
-} // conditional
- else if (enabled_interrupts & 512LL) { // conditional
-enabled_interrupts = 512LL;
-} // conditional
- else if (enabled_interrupts & 2LL) { // conditional
-enabled_interrupts = 2LL;
-} // conditional
- else if (enabled_interrupts & 32LL) { // conditional
-enabled_interrupts = 32LL;
-} // conditional
- else if (enabled_interrupts & 8192LL) { // conditional
-enabled_interrupts = 8192LL;
-} // conditional
- else if (enabled_interrupts & 1024LL) { // conditional
-enabled_interrupts = 1024LL;
-} // conditional
- else if (enabled_interrupts & 4LL) { // conditional
-enabled_interrupts = 4LL;
-} // conditional
- else if (enabled_interrupts & 64LL) { // conditional
-enabled_interrupts = 64LL;
-} // conditional
-else { // conditional
-return 0ULL;
-} // conditional
-return 9223372036854775808ULL | ctz(enabled_interrupts);
-} // block
-} // conditional
-return 0ULL;
-} // block
+#ifdef __cplusplus
 }
+#endif
 
-static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint64 irq_mcause = calc_irq_mcause(cpu, system, plugin_pointers);
-if (irq_mcause) { // conditional
-raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
-} // conditional
-} // block
-}
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
index 8c02edac5a..f79dde2c44 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the GDBCore adapter for the RV64IMACFD core architecture.
  *
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
index b77ca4ea85..8340256cd6 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index da84440926..f57eeab8ee 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -66,7 +64,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -79,7 +77,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -184,7 +182,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -200,7 +198,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -305,7 +303,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -321,7 +319,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -426,7 +424,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -442,7 +440,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -547,7 +545,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -563,7 +561,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -668,7 +666,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -684,7 +682,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -789,7 +787,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -805,7 +803,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -910,7 +908,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -926,7 +924,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1031,7 +1029,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1047,7 +1045,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index 730817c49a..de251037ca 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -61,7 +59,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -161,7 +159,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -257,7 +255,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -353,7 +351,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index 060dbc736a..e06dbae1e5 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -59,7 +57,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -157,7 +155,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -252,7 +250,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -341,7 +339,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -430,7 +428,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -519,7 +517,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -605,7 +603,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -688,7 +686,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -771,7 +769,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -854,7 +852,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -934,7 +932,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index 7e677499c6..b6bbefeb4e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -59,7 +57,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -161,7 +159,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -258,7 +256,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -351,7 +349,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -447,7 +445,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -543,7 +541,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -635,7 +633,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -724,7 +722,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -813,7 +811,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -902,7 +900,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -987,7 +985,7 @@ cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsqrt_s(frs1, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fsqrt_s(frs1, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index 793a1824a8..f0994449c2 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -60,7 +58,7 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -158,7 +156,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -261,7 +259,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_ad
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -563,7 +561,7 @@ cp.code() += "{ // block\n";
 if (imm == 0ULL) { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -658,7 +656,7 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[2ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " +
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -739,7 +737,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1655,7 +1653,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64I
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1668,7 +1666,7 @@ cp.code() += "} // block\n";
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1820,7 +1818,7 @@ cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32UL
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1890,7 +1888,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2095,7 +2093,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2176,7 +2174,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2253,7 +2251,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index 896c5c5410..d1bbd833c5 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -193,7 +191,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -301,7 +299,7 @@ cp.code() += "if (new_pc % 2ULL) { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -414,7 +412,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -533,7 +531,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -652,7 +650,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -771,7 +769,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -890,7 +888,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1009,7 +1007,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1120,7 +1118,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1217,7 +1215,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1314,7 +1312,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1411,7 +1409,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1508,7 +1506,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1608,7 +1606,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1706,7 +1704,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1804,7 +1802,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index 79f04bfe79..cae51b79ef 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,343 +1,17 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
 using namespace etiss::instr;
 
 
-// MUL -------------------------------------------------------------------------
-static InstructionDefinition mul_rd_rs1_rs2 (
-	ISA32_RV64IMACFD,
-	"mul",
-	(uint32_t) 0x2000033,
-	(uint32_t) 0xfe00707f,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//MUL\n");
-
-// -----------------------------------------------------------------------------
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
-cp.code() += "} // block\n";
-} // block
-{ // block
-cp.code() += "{ // block\n";
-if ((rd % 32ULL) != 0ULL) { // conditional
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
-cp.code() += "} // block\n";
-} // block
-} // conditional
-cp.code() += "} // block\n";
-} // block
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
-// MULH ------------------------------------------------------------------------
-static InstructionDefinition mulh_rd_rs1_rs2 (
-	ISA32_RV64IMACFD,
-	"mulh",
-	(uint32_t) 0x2001033,
-	(uint32_t) 0xfe00707f,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//MULH\n");
-
-// -----------------------------------------------------------------------------
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
-cp.code() += "} // block\n";
-} // block
-{ // block
-cp.code() += "{ // block\n";
-if ((rd % 32ULL) != 0ULL) { // conditional
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((res >> 64ULL));\n";
-cp.code() += "} // block\n";
-} // block
-} // conditional
-cp.code() += "} // block\n";
-} // block
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
-// MULHSU ----------------------------------------------------------------------
-static InstructionDefinition mulhsu_rd_rs1_rs2 (
-	ISA32_RV64IMACFD,
-	"mulhsu",
-	(uint32_t) 0x2002033,
-	(uint32_t) 0xfe00707f,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//MULHSU\n");
-
-// -----------------------------------------------------------------------------
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
-cp.code() += "} // block\n";
-} // block
-{ // block
-cp.code() += "{ // block\n";
-if ((rd % 32ULL) != 0ULL) { // conditional
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((res >> 64ULL));\n";
-cp.code() += "} // block\n";
-} // block
-} // conditional
-cp.code() += "} // block\n";
-} // block
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
-// MULHU -----------------------------------------------------------------------
-static InstructionDefinition mulhu_rd_rs1_rs2 (
-	ISA32_RV64IMACFD,
-	"mulhu",
-	(uint32_t) 0x2003033,
-	(uint32_t) 0xfe00707f,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//MULHU\n");
-
-// -----------------------------------------------------------------------------
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
-cp.code() += "} // block\n";
-} // block
-{ // block
-cp.code() += "{ // block\n";
-if ((rd % 32ULL) != 0ULL) { // conditional
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "etiss_uint128 res = (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((res >> 64ULL));\n";
-cp.code() += "} // block\n";
-} // block
-} // conditional
-cp.code() += "} // block\n";
-} // block
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
 // DIV -------------------------------------------------------------------------
 static InstructionDefinition div_rd_rs1_rs2 (
 	ISA32_RV64IMACFD,
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index 1b8c32f1a0..85c896f448 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -66,7 +64,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -79,7 +77,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -184,7 +182,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -200,7 +198,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -305,7 +303,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -321,7 +319,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -426,7 +424,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -442,7 +440,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -547,7 +545,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -563,7 +561,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -668,7 +666,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -684,7 +682,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -789,7 +787,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -805,7 +803,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -910,7 +908,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -926,7 +924,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1031,7 +1029,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1047,7 +1045,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index 670c5e31c0..b27658a401 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index fb8dabf30a..cc9507bb95 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index fe07364274..86711c098e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -269,7 +267,7 @@ cp.code() += "{ // block\n";
 if (rs1 == 0ULL) { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -364,7 +362,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -463,7 +461,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -697,7 +695,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -709,7 +707,7 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = re
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -803,7 +801,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index 8b2f4f27b3..90b1f0d9e6 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -59,7 +57,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -156,7 +154,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -256,7 +254,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index 5219edcc02..8c4709b017 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index fdfc3c104f..1b0a8ad3bb 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index ed80d4ea58..9e12a54e3c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -57,8 +55,8 @@ cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1
 if ((rd % 32ULL) != 0ULL) { // conditional
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
 cp.code() += "} // block\n";
 } // block
@@ -66,7 +64,7 @@ cp.code() += "} // block\n";
 else { // conditional
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
 cp.code() += "} // block\n";
 } // block
 } // conditional
@@ -143,10 +141,10 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 if (rs1 != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -224,10 +222,10 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 if (rs1 != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -305,8 +303,8 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
 } // conditional
@@ -383,9 +381,9 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 if (zimm != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -463,9 +461,9 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 if (zimm != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "ULL);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "ULL);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index ae78dee27e..66eea9bce8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -46,7 +44,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -117,21 +115,21 @@ cp.code() += "{ // block\n";
 cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
 cp.code() += "} // conditional\n";
 cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n";
-cp.code() += "etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 768LL);\n";
-cp.code() += "etiss_uint64 prev_prv = get_field(s, 6144LL);\n";
+cp.code() += "etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";
+cp.code() += "etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 6144LL);\n";
 cp.code() += "if (prev_prv != 3LL) { // conditional\n";
-cp.code() += "s = set_field(s, 131072LL, 0ULL);\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 131072LL, 0ULL);\n";
 cp.code() += "} // conditional\n";
-cp.code() += "s = set_field(s, 8LL, get_field(s, 128LL));\n";
-cp.code() += "s = set_field(s, 128LL, 1ULL);\n";
-cp.code() += "s = set_field(s, 6144LL, (extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 8LL, RV64IMACFD_get_field(s, 128LL));\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 128LL, 1ULL);\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 6144LL, (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
 cp.code() += "} // block\n";
 } // block
@@ -261,21 +259,21 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < ((get_field(csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
+cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < ((RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
 cp.code() += "} // conditional\n";
 cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n";
-cp.code() += "etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 256LL);\n";
-cp.code() += "etiss_uint64 prev_prv = get_field(s, 256LL);\n";
-cp.code() += "s = set_field(s, 2LL, get_field(s, 32LL));\n";
-cp.code() += "s = set_field(s, 32LL, 1ULL);\n";
-cp.code() += "s = set_field(s, 256LL, 0LL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
+cp.code() += "etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";
+cp.code() += "etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 256LL);\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 2LL, RV64IMACFD_get_field(s, 32LL));\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 32LL, 1ULL);\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 256LL, 0LL);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
 cp.code() += "} // block\n";
 } // block
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index 51497c6228..2afa8ca8f1 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -62,7 +60,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -171,7 +169,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index 41a384c539..6cdfbc4415 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -62,7 +60,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -171,7 +169,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp
new file mode 100644
index 0000000000..0779aebade
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp
@@ -0,0 +1,334 @@
+/**
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ *
+ * This file contains the instruction behavior models of the tum_rvm
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// MUL -------------------------------------------------------------------------
+static InstructionDefinition mul_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mul",
+	(uint32_t) 0x2000033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//MUL\n");
+
+// -----------------------------------------------------------------------------
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int64 res = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// MULH ------------------------------------------------------------------------
+static InstructionDefinition mulh_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mulh",
+	(uint32_t) 0x2001033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//MULH\n");
+
+// -----------------------------------------------------------------------------
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulh((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// MULHSU ----------------------------------------------------------------------
+static InstructionDefinition mulhsu_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mulhsu",
+	(uint32_t) 0x2002033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//MULHSU\n");
+
+// -----------------------------------------------------------------------------
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhsu((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// MULHU -----------------------------------------------------------------------
+static InstructionDefinition mulhu_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mulhu",
+	(uint32_t) 0x2003033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//MULHU\n");
+
+// -----------------------------------------------------------------------------
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhu(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index adfedfbfa0..d83bdba121 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -52,7 +50,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -63,7 +61,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -74,7 +72,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -94,7 +92,7 @@ cp.code() += "else { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -109,7 +107,7 @@ cp.code() += "else { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp
index f0d767ba53..6cbe14b891 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp
@@ -8,7 +8,9 @@
 #include "RV64IMACFDArch.h"
 
 #define ETISS_ARCH_STATIC_FN_ONLY
+extern "C" {
 #include "RV64IMACFDFuncs.h"
+}
 
 using namespace etiss;
 using namespace etiss::instr;

From f97939edfca79c25164337eebd74b40916b84374 Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Tue, 28 Nov 2023 09:51:15 +0100
Subject: [PATCH 43/44] fix irq vector swapped, div / 0 error

---
 ArchImpl/RV32IMACFD/CMakeLists.txt                      | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD.h                        | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp                  | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArch.h                    | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp               | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp       | 4 ++--
 ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h         | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c                   | 5 ++++-
 ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h                   | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h                 | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp                 | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp           | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp          | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp           | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp          | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp           | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp          | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp           | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp           | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp        | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp         | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp         | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp         | 2 +-
 ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp | 2 +-
 ArchImpl/RV64IMACFD/CMakeLists.txt                      | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD.h                        | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp                  | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArch.h                    | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp               | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp       | 4 ++--
 ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h         | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c                   | 5 ++++-
 ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h                   | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h                 | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp                 | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp           | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp          | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp           | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp           | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp          | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp           | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp           | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp           | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp           | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp           | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp          | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp           | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp           | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp        | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp         | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp         | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp       | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp         | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp         | 2 +-
 ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp | 2 +-
 55 files changed, 63 insertions(+), 57 deletions(-)

diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index b39a43b380..54e8a034bb 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+# Generated on Tue, 28 Nov 2023 09:45:19 +0100.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD.h b/ArchImpl/RV32IMACFD/RV32IMACFD.h
index 82269635a2..538b4eb029 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the registers for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
index 45ac32cd06..710bc07ae9 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
index f985a923fc..6ff28c4c5c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
index 83c9616a9a..be7a1cf73a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the library interface for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
index 7d9cccec47..5568acf9e2 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -345,8 +345,8 @@ etiss::InterruptVector * RV32IMACFDArch::createInterruptVector(ETISS_CPU * cpu)
 	std::vector<etiss::uint32 *> vec;
 	std::vector<etiss::uint32 *> mask;
 
-	vec.push_back(&((RV32IMACFD*)cpu)->MIE);
-	mask.push_back(&((RV32IMACFD*)cpu)->MIP);
+	vec.push_back(&((RV32IMACFD*)cpu)->MIP);
+	mask.push_back(&((RV32IMACFD*)cpu)->MIE);
 
 	return new etiss::MappedInterruptVector<etiss::uint32>(vec, mask);
 }
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
index eb94b75582..e9a4e1636b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the architecture specific header for the RV32IMACFD
  * core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c
index bf638e23ba..3164715eaa 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the function implementations for the RV32IMACFD core architecture.
  */
@@ -123,6 +123,9 @@ if (csr == 1LL) { // conditional
 etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
 {
 { // block
+if (!(mask)) { // conditional
+return 0ULL;
+} // conditional
 return (reg & mask) / (mask & ~((mask << 1ULL)));
 } // block
 }
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index f3384d6883..36a55fb202 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the function prototypes for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
index 1e42f39f63..e90ad6f481 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the GDBCore adapter for the RV32IMACFD core architecture.
  *
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
index 60576e12cf..59dd686e5d 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index d8a50954a9..5985fe8db7 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index a1acf2aa56..4b201ed078 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index 8434b8ecec..694895002b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 863c4896c6..1ec5f74e3d 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index b6b3fd8fb2..b1bce66baf 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index 4dd344a5a1..a3cad942da 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index a99c4d2e67..26692b7a72 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index 15bfe3c3bb..a432f45b19 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index f33616333d..7184a81933 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index 4fb08933b4..6353420428 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 4dc2310a0b..3d2db2cc7e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index dced7d903e..279e076b1c 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index bb39c1fec5..601cc97f27 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt
index 3a43d02b6e..fb9c4ad8f5 100644
--- a/ArchImpl/RV64IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV64IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+# Generated on Tue, 28 Nov 2023 09:45:19 +0100.
 #
 # This file contains the CMake build info for the RV64IMACFD core architecture.
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD.h b/ArchImpl/RV64IMACFD/RV64IMACFD.h
index 13349104f5..a2dc8d0d68 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the registers for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
index a2292b9aa8..b1796a3f0a 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
index 461a1d6b1b..3a025aeb06 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
index 1c05bd91d9..3c7ce23eb8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the library interface for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
index 0a32ab8dd8..7be16f264d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -345,8 +345,8 @@ etiss::InterruptVector * RV64IMACFDArch::createInterruptVector(ETISS_CPU * cpu)
 	std::vector<etiss::uint64 *> vec;
 	std::vector<etiss::uint64 *> mask;
 
-	vec.push_back(&((RV64IMACFD*)cpu)->MIE);
-	mask.push_back(&((RV64IMACFD*)cpu)->MIP);
+	vec.push_back(&((RV64IMACFD*)cpu)->MIP);
+	mask.push_back(&((RV64IMACFD*)cpu)->MIE);
 
 	return new etiss::MappedInterruptVector<etiss::uint64>(vec, mask);
 }
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
index 8b94f7a27d..f3a623cc27 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the architecture specific header for the RV64IMACFD
  * core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c
index d42498b9b2..927e9a00f0 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the function implementations for the RV64IMACFD core architecture.
  */
@@ -123,6 +123,9 @@ if (csr == 1LL) { // conditional
 etiss_uint64 RV64IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
 {
 { // block
+if (!(mask)) { // conditional
+return 0ULL;
+} // conditional
 return (reg & mask) / (mask & ~((mask << 1ULL)));
 } // block
 }
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index 93fec02cf9..98d356fbcd 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the function prototypes for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
index f79dde2c44..be39a0aacb 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the GDBCore adapter for the RV64IMACFD core architecture.
  *
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
index 8340256cd6..49c27e824f 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index f57eeab8ee..23e3ebdc0b 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index de251037ca..e0548e4ebd 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index e06dbae1e5..820fa7ad60 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index b6bbefeb4e..e8b6879aba 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index f0994449c2..645c92c559 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index d1bbd833c5..8a365f76ae 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index cae51b79ef..eceb074ea4 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index 85c896f448..6cf1c75bf7 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index b27658a401..87e5e07efa 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index cc9507bb95..9eb52e39db 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index 86711c098e..9e2d0d1304 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index 90b1f0d9e6..1137b30d09 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index 8c4709b017..996f9f6d13 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index 1b0a8ad3bb..ac7eed9354 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index 9e12a54e3c..a245b49a9d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index 66eea9bce8..c1813f9847 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index 2afa8ca8f1..a363147790 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index 6cdfbc4415..9465934072 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp
index 0779aebade..9079620b69 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the tum_rvm
  * instruction set for the RV64IMACFD core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index d83bdba121..0020b56c47 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ * Generated on Tue, 28 Nov 2023 09:45:19 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.

From cb8951223b2a749c488a395ad310c431ff1b617d Mon Sep 17 00:00:00 2001
From: wysiwyng <4764286+wysiwyng@users.noreply.github.com>
Date: Tue, 28 Nov 2023 09:51:33 +0100
Subject: [PATCH 44/44] use ETISS_BINARY_DIR

---
 src/jitlibs/semihost/CMakeLists.txt | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/jitlibs/semihost/CMakeLists.txt b/src/jitlibs/semihost/CMakeLists.txt
index 8fa0b41383..9ae2fc0b01 100644
--- a/src/jitlibs/semihost/CMakeLists.txt
+++ b/src/jitlibs/semihost/CMakeLists.txt
@@ -11,11 +11,11 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 
 add_custom_command(
   TARGET ${PROJECT_NAME} POST_BUILD VERBATIM
-  COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_BINARY_DIR}/include/jit/etiss/jit/
-  COMMAND ${CMAKE_COMMAND} -E copy "$<TARGET_FILE:${PROJECT_NAME}>" ${CMAKE_BINARY_DIR}/include/jit/etiss/jit/
+  COMMAND ${CMAKE_COMMAND} -E make_directory ${ETISS_BINARY_DIR}/include/jit/etiss/jit/
+  COMMAND ${CMAKE_COMMAND} -E copy "$<TARGET_FILE:${PROJECT_NAME}>" ${ETISS_BINARY_DIR}/include/jit/etiss/jit/
 )
 
-  
+
 TARGET_LINK_LIBRARIES(${PROJECT_NAME} PUBLIC ETISS)
 
 INSTALL(FILES