From 03fa0dbda6d8d5d731a96950db570aca6b178854 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 12 May 2023 14:06:44 -0700 Subject: [PATCH] Bump to latest rocket-chip --- fpga/fpga-shells | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/Cospike.scala | 19 ++++++++++--------- .../chipyard/src/main/scala/SpikeTile.scala | 1 + .../main/scala/clocking/ClockBinders.scala | 6 +++--- .../main/scala/clocking/TileClockGater.scala | 2 +- .../main/scala/clocking/TileResetSetter.scala | 2 +- .../src/main/scala/example/FlatChipTop.scala | 8 ++++---- .../chipyard/src/main/scala/example/GCD.scala | 6 +++--- .../src/main/scala/example/InitZero.scala | 2 +- .../src/main/scala/example/TutorialTile.scala | 1 + .../scala/example/dsptools/GenericFIR.scala | 2 +- .../dsptools/StreamingPassthrough.scala | 2 +- generators/cva6 | 2 +- generators/fft-generator | 2 +- generators/ibex | 2 +- generators/icenet | 2 +- generators/nvdla | 2 +- generators/riscv-sodor | 2 +- generators/rocket-chip | 2 +- generators/testchipip | 2 +- sims/firesim | 2 +- 22 files changed, 38 insertions(+), 35 deletions(-) diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 9f4c6ac571..d650f81c07 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 9f4c6ac5719b03ded61022dc3767e750872d0535 +Subproject commit d650f81c0728f3108719d37396c2a651a7463520 diff --git a/generators/boom b/generators/boom index 679f358755..f732ceb602 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 679f358755c57524f18cf46b72fc3fc1ac67f127 +Subproject commit f732ceb602bcccd4adb6a5f7137c7c0bea08be9d diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala index cee2341336..de04b032f4 100644 --- a/generators/chipyard/src/main/scala/Cospike.scala +++ b/generators/chipyard/src/main/scala/Cospike.scala @@ -72,17 +72,18 @@ object SpikeCosim }) cosim.io.hartid := hartid.U for (i <- 0 until trace.numInsns) { - cosim.io.trace(i).valid := trace.insns(i).valid + val insn = trace.trace.insns(i) + cosim.io.trace(i).valid := insn.valid val signed = Wire(SInt(64.W)) - signed := trace.insns(i).iaddr.asSInt + signed := insn.iaddr.asSInt cosim.io.trace(i).iaddr := signed.asUInt - cosim.io.trace(i).insn := trace.insns(i).insn - cosim.io.trace(i).exception := trace.insns(i).exception - cosim.io.trace(i).interrupt := trace.insns(i).interrupt - cosim.io.trace(i).cause := trace.insns(i).cause - cosim.io.trace(i).has_wdata := trace.insns(i).wdata.isDefined.B - cosim.io.trace(i).wdata := trace.insns(i).wdata.getOrElse(0.U) - cosim.io.trace(i).priv := trace.insns(i).priv + cosim.io.trace(i).insn := insn.insn + cosim.io.trace(i).exception := insn.exception + cosim.io.trace(i).interrupt := insn.interrupt + cosim.io.trace(i).cause := insn.cause + cosim.io.trace(i).has_wdata := insn.wdata.isDefined.B + cosim.io.trace(i).wdata := insn.wdata.getOrElse(0.U) + cosim.io.trace(i).priv := insn.priv } } } diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index c6ec13aea8..fc822c2272 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -62,6 +62,7 @@ case class SpikeCoreParams() extends CoreParams { val useBitManipCrypto = false val useCryptoNIST = false val useCryptoSM = false + val useConditionalZero = false override def vLen = 128 override def vMemDataBits = 128 diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 5a53051e73..181209aa2b 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } - tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() } - tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() } - tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() } + tlbus.coupleTo("clock-div-ctrl") { clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } + tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } + tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala index 23d525a65d..0c4e8b1194 100644 --- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala +++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala @@ -49,7 +49,7 @@ class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, va object TileClockGater { def apply(address: BigInt, tlbus: TLBusWrapper)(implicit p: Parameters, v: ValName) = { val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes)) - tlbus.toVariableWidthSlave(Some("clock-gater")) { gater.tlNode := TLBuffer() } + tlbus.coupleTo("clock-gater") { gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } gater.clockNode } } diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala index 9ea4bfd5bc..60bfe34379 100644 --- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala +++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala @@ -67,7 +67,7 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i object TileResetSetter { def apply(address: BigInt, tlbus: TLBusWrapper, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters, v: ValName) = { val setter = LazyModule(new TileResetSetter(address, tlbus.beatBytes, tileNames, initResetHarts)) - tlbus.toVariableWidthSlave(Some("tile-reset-setter")) { setter.tlNode := TLBuffer() } + tlbus.coupleTo("tile-reset-setter") { setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } setter.clockNode } } diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index c10baab454..b960251d94 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug} -import freechips.rocketchip.tilelink.{TLBuffer} +import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter} import chipyard.{BuildSystem, DigitalTop} import chipyard.clocking._ import chipyard.iobinders.{IOCellKey, JTAGChipIO} @@ -33,9 +33,9 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } - tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() } - tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() } - tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() } + tlbus.coupleTo("clock-div-ctrl") { clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } + tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } + tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index bf05ba9c9e..5e6c5d67cd 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -165,17 +165,17 @@ trait CanHavePeripheryGCD { this: BaseSubsystem => case Some(params) => { if (params.useAXI4) { val gcd = LazyModule(new GCDAXI4(params, pbus.beatBytes)(p)) - pbus.toSlave(Some(portName)) { + pbus.coupleTo(portName) { gcd.node := AXI4Buffer () := TLToAXI4 () := // toVariableWidthSlave doesn't use holdFirstDeny, which TLToAXI4() needsx - TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true) + TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true) := _ } Some(gcd) } else { val gcd = LazyModule(new GCDTL(params, pbus.beatBytes)(p)) - pbus.toVariableWidthSlave(Some(portName)) { gcd.node } + pbus.coupleTo(portName) { gcd.node := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } Some(gcd) } } diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala index bb6ecd72a7..78237eca77 100644 --- a/generators/chipyard/src/main/scala/example/InitZero.scala +++ b/generators/chipyard/src/main/scala/example/InitZero.scala @@ -62,7 +62,7 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem => p(InitZeroKey) .map { k => val initZero = LazyModule(new InitZero()(p)) - fbus.fromPort(Some("init-zero"))() := initZero.node + fbus.coupleFrom("init-zero") { _ := initZero.node } } } diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 1a9114b9b4..38c8577ad6 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -67,6 +67,7 @@ case class MyCoreParams( val useCryptoNIST: Boolean = false val useCryptoSM: Boolean = false val traceHasWdata: Boolean = false + val useConditionalZero = false } // DOC include start: CanAttachTile diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index 15dfb99246..3e315e654c 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -203,7 +203,7 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem { genOut = FixedPoint(8.W, 3.BP), coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)), params = params)) - pbus.toVariableWidthSlave(Some("streamingFIR")) { streamingFIR.mem.get := TLFIFOFixer() } + pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } Some(streamingFIR) } case None => None diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index 2846277cc9..45e05fc253 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -132,7 +132,7 @@ trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => val passthrough = p(StreamingPassthroughKey) match { case Some(params) => { val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) - pbus.toVariableWidthSlave(Some("streamingPassthrough")) { streamingPassthroughChain.mem.get := TLFIFOFixer() } + pbus.coupleTo("streamingPassthrough") { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } Some(streamingPassthroughChain) } case None => None diff --git a/generators/cva6 b/generators/cva6 index 0011494bb7..5bb6d6a7ae 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 0011494bb70d2327ab4d6b0258f5073f137927ee +Subproject commit 5bb6d6a7ae0a0e17e253996386823a5b540da28c diff --git a/generators/fft-generator b/generators/fft-generator index be8ab768bd..f598d0c359 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit be8ab768bd15824c69531df632478e4429078b94 +Subproject commit f598d0c359c896e7853c8ef01c39ebecdd48b344 diff --git a/generators/ibex b/generators/ibex index 916fb7a6ff..66ec6e56ed 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 916fb7a6ff4a65f989279bcc082676a565beee0c +Subproject commit 66ec6e56ed69df4e4af5383128cf21adf88b08fc diff --git a/generators/icenet b/generators/icenet index ce1ec55c1f..68b4c7f30f 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit ce1ec55c1fd9c4339e7c0eec3a82d86041fa5d20 +Subproject commit 68b4c7f30f0119fe5cfab7ea99fb6927a563e112 diff --git a/generators/nvdla b/generators/nvdla index 7130a5c0f7..730fad4360 160000 --- a/generators/nvdla +++ b/generators/nvdla @@ -1 +1 @@ -Subproject commit 7130a5c0f7016cd177ec9cf908a18edd668660d1 +Subproject commit 730fad4360e67b14b1a4656ac58aaa40cfd4fe6b diff --git a/generators/riscv-sodor b/generators/riscv-sodor index c051956d3b..b1b70b6584 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit c051956d3be3269c4ed9fcbb6afe920a6f54fd32 +Subproject commit b1b70b65848d56a381043a80666afe3d79ef5a67 diff --git a/generators/rocket-chip b/generators/rocket-chip index 25e2c63567..8c42f403f2 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 25e2c63567689ebe1fc5e60fdfe3375a8dba071c +Subproject commit 8c42f403f218d3bad4b323a9ad6e70fad034dc4e diff --git a/generators/testchipip b/generators/testchipip index ebf61569c5..d5126c17d4 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ebf61569c5a65ff46ac3ee77fcc3a8404441ab9d +Subproject commit d5126c17d4e8d9119bb8068b520208ded4c7951e diff --git a/sims/firesim b/sims/firesim index 966e09907c..8666b25a31 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 966e09907cde52f0ce68eb654bf6020b5b97a6c3 +Subproject commit 8666b25a31575027e409b3836ce080e6b70e3a46