From 0adfb8b9a7ac75cf284ff4155c763ecc3ac8f950 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Apr 2024 19:46:53 -0700 Subject: [PATCH 01/10] Remove FixedPoint fallback to SFC (Fixed types aren't generated anymore) --- common.mk | 9 ++++----- docs/Customization/Firrtl-Transforms.rst | 2 +- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/common.mk b/common.mk index ea5811acd9..beb3c1734b 100644 --- a/common.mk +++ b/common.mk @@ -198,19 +198,18 @@ MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVa # DOC include start: FirrtlCompiler # There are two possible cases for this step. In the first case, SFC # compiles Chisel to CHIRRTL, and MFC compiles CHIRRTL to Verilog. Otherwise, -# when custom FIRRTL transforms are included or if a Fixed type is used within -# the dut, SFC compiles Chisel to LowFIRRTL and MFC compiles it to Verilog. +# when custom FIRRTL transforms are included +# SFC compiles Chisel to LowFIRRTL and MFC compiles it to Verilog. # Users can indicate to the Makefile of custom FIRRTL transforms by setting the # "ENABLE_CUSTOM_FIRRTL_PASS" variable. # -# hack: lower to low firrtl if Fixed types are found # hack: when using dontTouch, io.cpu annotations are not removed by SFC, # hence we remove them manually by using jq before passing them to firtool $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) &: $(FIRRTL_FILE) ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) - echo $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none) > $(SFC_LEVEL) - echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), "$(SFC_REPL_SEQ_MEM)",) > $(EXTRA_FIRRTL_OPTIONS) + echo none > $(SFC_LEVEL) + echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" > $(EXTRA_FIRRTL_OPTIONS) else echo low > $(SFC_LEVEL) echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" "$(SFC_REPL_SEQ_MEM)" > $(EXTRA_FIRRTL_OPTIONS) diff --git a/docs/Customization/Firrtl-Transforms.rst b/docs/Customization/Firrtl-Transforms.rst index 7de7aadbd4..2c552e7580 100644 --- a/docs/Customization/Firrtl-Transforms.rst +++ b/docs/Customization/Firrtl-Transforms.rst @@ -12,7 +12,7 @@ The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler ------------------------------------------------------ In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler (SFC) and the MLIR FIRRTL compiler (MFC). They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster (the generated Verilog will be different). In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will -compile CHIRRTL into Verilog (as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value, +compile CHIRRTL into Verilog. By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value, we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied. For more information on MLIR FIRRTL Compiler, please visit https://mlir.llvm.org/ and https://circt.llvm.org/. From bd7f82f353ca8ef6057620ecee8d25b1651b524c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Apr 2024 19:48:27 -0700 Subject: [PATCH 02/10] Remove CUSTOM_FIRRTL_PASS support, SFC passes are discouraged --- common.mk | 8 -------- docs/Customization/Firrtl-Transforms.rst | 3 +-- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/common.mk b/common.mk index beb3c1734b..7a7a3292c4 100644 --- a/common.mk +++ b/common.mk @@ -16,7 +16,6 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ " EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ -" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \ " ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_BASE_FIRRTL_OPTIONS = additional options to pass to the Scala FIRRTL compiler" \ @@ -200,20 +199,13 @@ MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVa # compiles Chisel to CHIRRTL, and MFC compiles CHIRRTL to Verilog. Otherwise, # when custom FIRRTL transforms are included # SFC compiles Chisel to LowFIRRTL and MFC compiles it to Verilog. -# Users can indicate to the Makefile of custom FIRRTL transforms by setting the -# "ENABLE_CUSTOM_FIRRTL_PASS" variable. # # hack: when using dontTouch, io.cpu annotations are not removed by SFC, # hence we remove them manually by using jq before passing them to firtool $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) &: $(FIRRTL_FILE) -ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) echo none > $(SFC_LEVEL) echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" > $(EXTRA_FIRRTL_OPTIONS) -else - echo low > $(SFC_LEVEL) - echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" "$(SFC_REPL_SEQ_MEM)" > $(EXTRA_FIRRTL_OPTIONS) -endif $(MFC_LOWERING_OPTIONS): mkdir -p $(dir $@) diff --git a/docs/Customization/Firrtl-Transforms.rst b/docs/Customization/Firrtl-Transforms.rst index 2c552e7580..5de6ecb3ba 100644 --- a/docs/Customization/Firrtl-Transforms.rst +++ b/docs/Customization/Firrtl-Transforms.rst @@ -12,8 +12,7 @@ The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler ------------------------------------------------------ In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler (SFC) and the MLIR FIRRTL compiler (MFC). They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster (the generated Verilog will be different). In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will -compile CHIRRTL into Verilog. By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value, -we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied. +compile CHIRRTL into Verilog. For more information on MLIR FIRRTL Compiler, please visit https://mlir.llvm.org/ and https://circt.llvm.org/. From 7d8a76ccc909094c6a380f131cba8f18c98d9a06 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Apr 2024 19:50:31 -0700 Subject: [PATCH 03/10] Remove SFC_LEVEL --- common.mk | 15 ++++----------- variables.mk | 1 - 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/common.mk b/common.mk index 7a7a3292c4..6bb9dce75e 100644 --- a/common.mk +++ b/common.mk @@ -203,8 +203,7 @@ MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVa # hack: when using dontTouch, io.cpu annotations are not removed by SFC, # hence we remove them manually by using jq before passing them to firtool -$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) &: $(FIRRTL_FILE) - echo none > $(SFC_LEVEL) +$(EXTRA_FIRRTL_OPTIONS) &: $(FIRRTL_FILE) echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" > $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS): @@ -215,13 +214,11 @@ else echo "$(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays" > $@ endif -$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(SFC_LEVEL) - if [ $(shell cat $(SFC_LEVEL)) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $@; fi - if [ $(shell cat $(SFC_LEVEL)) = none ]; then cat $(EXTRA_ANNO_FILE) > $@; fi +$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) + cat $(EXTRA_ANNO_FILE) > $@ touch $@ -$(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX) -$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) +$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) rm -rf $(GEN_COLLATERAL_DIR) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.transforms.GenerateModelStageMain,\ --no-dedup \ @@ -232,12 +229,8 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F --annotation-file $(FINAL_ANNO_FILE) \ --log-level $(FIRRTL_LOGLEVEL) \ --allow-unrecognized-annotations \ - -X $(shell cat $(SFC_LEVEL)) \ $(shell cat $(EXTRA_FIRRTL_OPTIONS))) -mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL - @if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json; fi - @if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi - @if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json && rm $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi firtool \ --format=fir \ --export-module-hierarchy \ diff --git a/variables.mk b/variables.mk index 3bebdb1acb..ec1ceb94e3 100644 --- a/variables.mk +++ b/variables.mk @@ -228,7 +228,6 @@ sim_files ?= $(build_dir)/sim_files.f # single file that contains all files needed for VCS or Verilator simulation (unique and without .h's) sim_common_files ?= $(build_dir)/sim_files.common.f -SFC_LEVEL ?= $(build_dir)/.sfc_level EXTRA_FIRRTL_OPTIONS ?= $(build_dir)/.extra_firrtl_options MFC_LOWERING_OPTIONS ?= $(build_dir)/.mfc_lowering_options From f85b4bb9dcc16cf80f98c0bc9ea4d7f508bf37fe Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Apr 2024 19:51:57 -0700 Subject: [PATCH 04/10] Remove EXTRA_FIRRTL_OPTIONS ; using sfc is discouraged --- common.mk | 17 ++--------------- variables.mk | 1 - 2 files changed, 2 insertions(+), 16 deletions(-) diff --git a/common.mk b/common.mk index 6bb9dce75e..e3c325adbe 100644 --- a/common.mk +++ b/common.mk @@ -18,7 +18,6 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ -" EXTRA_BASE_FIRRTL_OPTIONS = additional options to pass to the Scala FIRRTL compiler" \ " MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \ " ASPECTS = comma separated list of Chisel aspect flows to run (e.x. chipyard.upf.ChipTopUPFAspect)" @@ -195,17 +194,6 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket # DOC include start: FirrtlCompiler -# There are two possible cases for this step. In the first case, SFC -# compiles Chisel to CHIRRTL, and MFC compiles CHIRRTL to Verilog. Otherwise, -# when custom FIRRTL transforms are included -# SFC compiles Chisel to LowFIRRTL and MFC compiles it to Verilog. -# -# hack: when using dontTouch, io.cpu annotations are not removed by SFC, -# hence we remove them manually by using jq before passing them to firtool - -$(EXTRA_FIRRTL_OPTIONS) &: $(FIRRTL_FILE) - echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" > $(EXTRA_FIRRTL_OPTIONS) - $(MFC_LOWERING_OPTIONS): mkdir -p $(dir $@) ifeq (,$(ENABLE_YOSYS_FLOW)) @@ -218,7 +206,7 @@ $(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) cat $(EXTRA_ANNO_FILE) > $@ touch $@ -$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) +$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) rm -rf $(GEN_COLLATERAL_DIR) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.transforms.GenerateModelStageMain,\ --no-dedup \ @@ -228,8 +216,7 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F --input-file $(FIRRTL_FILE) \ --annotation-file $(FINAL_ANNO_FILE) \ --log-level $(FIRRTL_LOGLEVEL) \ - --allow-unrecognized-annotations \ - $(shell cat $(EXTRA_FIRRTL_OPTIONS))) + --allow-unrecognized-annotations) -mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL firtool \ --format=fir \ diff --git a/variables.mk b/variables.mk index ec1ceb94e3..ae076c3ac0 100644 --- a/variables.mk +++ b/variables.mk @@ -228,7 +228,6 @@ sim_files ?= $(build_dir)/sim_files.f # single file that contains all files needed for VCS or Verilator simulation (unique and without .h's) sim_common_files ?= $(build_dir)/sim_files.common.f -EXTRA_FIRRTL_OPTIONS ?= $(build_dir)/.extra_firrtl_options MFC_LOWERING_OPTIONS ?= $(build_dir)/.mfc_lowering_options ######################################################################################### From e0c367ecabc383c0e0f701c20d87eebf4e1b242f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Apr 2024 19:52:47 -0700 Subject: [PATCH 05/10] Remove lofirrtl handling --- common.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/common.mk b/common.mk index e3c325adbe..c10e1c415a 100644 --- a/common.mk +++ b/common.mk @@ -217,7 +217,6 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F --annotation-file $(FINAL_ANNO_FILE) \ --log-level $(FIRRTL_LOGLEVEL) \ --allow-unrecognized-annotations) - -mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL firtool \ --format=fir \ --export-module-hierarchy \ From c96ffb630474eeb627932371506eeacdc1e935f6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Apr 2024 19:55:12 -0700 Subject: [PATCH 06/10] Remove SFC_EXTRA_ANNO_FILE --- common.mk | 13 ++----------- variables.mk | 1 - 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/common.mk b/common.mk index c10e1c415a..9f3cf1e0e0 100644 --- a/common.mk +++ b/common.mk @@ -159,19 +159,10 @@ define mfc_extra_anno_contents } ] endef -define sfc_extra_low_transforms_anno_contents -[ - { - "class": "firrtl.stage.RunFirrtlTransformAnnotation", - "transform": "tapeout.transforms.ExtraLowTransforms" - } -] -endef export mfc_extra_anno_contents export sfc_extra_low_transforms_anno_contents -$(EXTRA_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE) +$(EXTRA_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE) echo "$$mfc_extra_anno_contents" > $(MFC_EXTRA_ANNO_FILE) - echo "$$sfc_extra_low_transforms_anno_contents" > $(SFC_EXTRA_ANNO_FILE) jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(EXTRA_ANNO_FILE) .PHONY: firrtl @@ -202,7 +193,7 @@ else echo "$(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays" > $@ endif -$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) +$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) cat $(EXTRA_ANNO_FILE) > $@ touch $@ diff --git a/variables.mk b/variables.mk index ae076c3ac0..cfb29a6135 100644 --- a/variables.mk +++ b/variables.mk @@ -180,7 +180,6 @@ FINAL_ANNO_FILE ?= $(build_dir)/$(long_name).appended.anno.json # scala firrtl compiler (sfc) outputs SFC_FIRRTL_BASENAME ?= $(build_dir)/$(long_name).sfc SFC_FIRRTL_FILE ?= $(SFC_FIRRTL_BASENAME).fir -SFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrasfc.anno.json SFC_ANNO_FILE ?= $(build_dir)/$(long_name).sfc.anno.json # firtool compiler outputs From 4c1e3d211d806486ead7956a24b8cbff83daf2b1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Apr 2024 19:56:27 -0700 Subject: [PATCH 07/10] Remove EXTRA_ANNO_FILE --- common.mk | 8 ++------ variables.mk | 1 - 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/common.mk b/common.mk index 9f3cf1e0e0..9223e29501 100644 --- a/common.mk +++ b/common.mk @@ -161,9 +161,9 @@ define mfc_extra_anno_contents endef export mfc_extra_anno_contents export sfc_extra_low_transforms_anno_contents -$(EXTRA_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE) +$(FINAL_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE) echo "$$mfc_extra_anno_contents" > $(MFC_EXTRA_ANNO_FILE) - jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(EXTRA_ANNO_FILE) + jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE) .PHONY: firrtl firrtl: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) @@ -193,10 +193,6 @@ else echo "$(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays" > $@ endif -$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) - cat $(EXTRA_ANNO_FILE) > $@ - touch $@ - $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) rm -rf $(GEN_COLLATERAL_DIR) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.transforms.GenerateModelStageMain,\ diff --git a/variables.mk b/variables.mk index cfb29a6135..e0dd123613 100644 --- a/variables.mk +++ b/variables.mk @@ -170,7 +170,6 @@ TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH)) # chisel generated outputs FIRRTL_FILE ?= $(build_dir)/$(long_name).fir ANNO_FILE ?= $(build_dir)/$(long_name).anno.json -EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extra.anno.json CHISEL_LOG_FILE ?= $(build_dir)/$(long_name).chisel.log # chisel anno modification output From a152e0af69ac4286e4671295eff18d155df11dc2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Apr 2024 19:58:07 -0700 Subject: [PATCH 08/10] Remove SFC_SMEMS_CONF --- common.mk | 2 -- variables.mk | 1 - 2 files changed, 3 deletions(-) diff --git a/common.mk b/common.mk index 9223e29501..4bec57eef8 100644 --- a/common.mk +++ b/common.mk @@ -181,7 +181,6 @@ SFC_MFC_TARGETS = \ $(MFC_BB_MODS_FILELIST) \ $(GEN_COLLATERAL_DIR) -SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket # DOC include start: FirrtlCompiler @@ -219,7 +218,6 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F --split-verilog \ -o $(GEN_COLLATERAL_DIR) \ $(SFC_FIRRTL_FILE) - -mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) 2> /dev/null $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it # DOC include end: FirrtlCompiler diff --git a/variables.mk b/variables.mk index e0dd123613..72b1bd2bae 100644 --- a/variables.mk +++ b/variables.mk @@ -193,7 +193,6 @@ MFC_TOP_SMEMS_JSON = $(GEN_COLLATERAL_DIR)/metadata/seq_mems.json MFC_MODEL_SMEMS_JSON = $(GEN_COLLATERAL_DIR)/metadata/tb_seq_mems.json # macrocompiler smems in/output -SFC_SMEMS_CONF ?= $(build_dir)/$(long_name).sfc.mems.conf TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf TOP_SMEMS_FILE ?= $(GEN_COLLATERAL_DIR)/$(long_name).top.mems.v TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir From 5992f0e0f7a63ad434d22ae1599e10a87acc303a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Apr 2024 20:09:18 -0700 Subject: [PATCH 09/10] Update docs on firrtl compile --- docs/Customization/Firrtl-Transforms.rst | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/docs/Customization/Firrtl-Transforms.rst b/docs/Customization/Firrtl-Transforms.rst index 5de6ecb3ba..f7d565a7e7 100644 --- a/docs/Customization/Firrtl-Transforms.rst +++ b/docs/Customization/Firrtl-Transforms.rst @@ -8,11 +8,9 @@ modify Chisel-elaborated RTL. As mentioned in Section :ref:`Tools/FIRRTL:firrtl`, transforms are modifications that happen on the FIRRTL IR that can modify a circuit. Transforms are a powerful tool to take in the FIRRTL IR that is emitted from Chisel and run analysis or convert the circuit into a new form. -The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler +The MLIR FIRRTL Compiler ------------------------------------------------------ -In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler (SFC) and the MLIR FIRRTL compiler (MFC). -They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster (the generated Verilog will be different). In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will -compile CHIRRTL into Verilog. +In Chipyard, the LLVM-based MLIR FIRRTL compiler (CIRCT or MFC) compiles Chisel into Verilog. For more information on MLIR FIRRTL Compiler, please visit https://mlir.llvm.org/ and https://circt.llvm.org/. From fafc71e63f07d11030c779b8acb17995c0874865 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Apr 2024 21:26:16 -0700 Subject: [PATCH 10/10] Fix SFC flow for now --- common.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common.mk b/common.mk index 4bec57eef8..9913a7781f 100644 --- a/common.mk +++ b/common.mk @@ -202,7 +202,9 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F --input-file $(FIRRTL_FILE) \ --annotation-file $(FINAL_ANNO_FILE) \ --log-level $(FIRRTL_LOGLEVEL) \ + -X none \ --allow-unrecognized-annotations) + -mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) firtool \ --format=fir \ --export-module-hierarchy \