diff --git a/generators/chipyard/src/main/scala/config/AraConfigs.scala b/generators/chipyard/src/main/scala/config/AraConfigs.scala index 803ff6212..a408aeea7 100644 --- a/generators/chipyard/src/main/scala/config/AraConfigs.scala +++ b/generators/chipyard/src/main/scala/config/AraConfigs.scala @@ -6,14 +6,14 @@ import saturn.common.{VectorParams} // Rocket-integrated configs class V4096Ara2LaneRocketConfig extends Config( new ara.WithAraRocketVectorUnit(4096, 2) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class V8192Ara4LaneRocketConfig extends Config( new ara.WithAraRocketVectorUnit(8192, 4) ++ new chipyard.config.WithSystemBusWidth(128) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 08aab4c0e..33eb5aac9 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -17,7 +17,7 @@ class ChipLikeRocketConfig extends Config( // Set up tiles //================================== new freechips.rocketchip.rocket.WithAsynchronousCDCs(depth=8, sync=3) ++ // Add async crossings between RocketTile and uncore - new freechips.rocketchip.rocket.WithNBigCores(1) ++ // 1 RocketTile + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // 1 RocketTile //================================== // Set up I/O diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala index da65d9d1c..dd1b09eb5 100644 --- a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala @@ -35,7 +35,7 @@ class SymmetricChipletRocketConfig extends Config( replicationBase = Some(1L << 32) // The upper 4GB goes off-chip ) ++ new testchipip.soc.WithOffchipBus ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config @@ -71,7 +71,7 @@ class RocketCoreChipletConfig extends Config( new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // LLC-only chiplet diff --git a/generators/chipyard/src/main/scala/config/ClockingConfigs.scala b/generators/chipyard/src/main/scala/config/ClockingConfigs.scala index 837e732ee..f35817729 100644 --- a/generators/chipyard/src/main/scala/config/ClockingConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ClockingConfigs.scala @@ -14,7 +14,7 @@ import testchipip.soc.{OBUS} // Note: This is what designs inheriting from AbstractConfig do by default class DefaultClockingRocketConfig extends Config( new chipyard.clocking.WithPassthroughClockGenerator ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // This is a more physically realistic approach, normally we can't punch out a separate @@ -23,12 +23,12 @@ class DefaultClockingRocketConfig extends Config( // clocks for each domain. See the source for WithPLLSelectorDividerClockGenerator for more info class ChipLikeClockingRocketConfig extends Config( new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // This merges all the clock domains in chiptopClockGroupsNode into one, then generates a single // clock input pin. class SingleClockBroadcastRocketConfig extends Config( new chipyard.clocking.WithSingleClockBroadcastClockGenerator ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index 1d344ee54..9252ba6b2 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -8,20 +8,20 @@ import org.chipsalliance.cde.config.{Config} class LargeBoomAndRocketConfig extends Config( new boom.v3.common.WithNLargeBooms(1) ++ // single-core boom - new freechips.rocketchip.rocket.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // single rocket-core new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) class DualLargeBoomAndDualRocketConfig extends Config( new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores - new freechips.rocketchip.rocket.WithNBigCores(2) ++ // add 2 rocket cores + new freechips.rocketchip.rocket.WithNHugeCores(2) ++ // add 2 rocket cores new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) // DOC include start: DualBoomAndSingleRocket class DualLargeBoomAndSingleRocketConfig extends Config( new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores - new freechips.rocketchip.rocket.WithNBigCores(1) ++ // add 1 rocket core + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // add 1 rocket core new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) // DOC include end: DualBoomAndSingleRocket @@ -29,6 +29,6 @@ class DualLargeBoomAndSingleRocketConfig extends Config( class LargeBoomAndRocketWithControlCoreConfig extends Config( new freechips.rocketchip.rocket.WithNSmallCores(1) ++ // Add a small "control" core new boom.v3.common.WithNLargeBooms(1) ++ // Add 1 boom core - new freechips.rocketchip.rocket.WithNBigCores(1) ++ // add 1 rocket core + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // add 1 rocket core new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala index eaae215ae..30a180439 100644 --- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala @@ -10,51 +10,51 @@ import org.chipsalliance.cde.config.{Config} class FFTRocketConfig extends Config( new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO: hack around dontTouch not working in SFC new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers. - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: FFTRocketConfig // DOC include start: GCDTLRocketConfig class GCDTLRocketConfig extends Config( new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: GCDTLRocketConfig // DOC include start: GCDAXI4BlackBoxRocketConfig class GCDAXI4BlackBoxRocketConfig extends Config( new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig // DOC include start: InitZeroRocketConfig class InitZeroRocketConfig extends Config( new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: InitZeroRocketConfig class StreamingPassthroughRocketConfig extends Config( new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include start: StreamingFIRRocketConfig class StreamingFIRRocketConfig extends Config ( new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: StreamingFIRRocketConfig class SmallNVDLARocketConfig extends Config( new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class LargeNVDLARocketConfig extends Config( new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class ManyMMIOAcceleratorRocketConfig extends Config( @@ -63,5 +63,5 @@ class ManyMMIOAcceleratorRocketConfig extends Config( new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers. new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala index 2162435c9..0ec6fe23e 100644 --- a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala @@ -8,38 +8,38 @@ import org.chipsalliance.cde.config.{Config} class SimAXIRocketConfig extends Config( new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class GB1MemoryRocketConfig extends Config( new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include start: mbusscratchpadrocket class MbusScratchpadOnlyRocketConfig extends Config( new testchipip.soc.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: mbusscratchpadrocket class SbusScratchpadRocketConfig extends Config( new testchipip.soc.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class SbusBypassRocketConfig extends Config( new freechips.rocketchip.subsystem.WithExtMemSbusBypass ++ // Add bypass path to access DRAM incoherently through an address alias - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class QuadChannelRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++ // 4 AXI4 channels - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class BroadcastCoherenceRocketConfig extends Config( new chipyard.config.WithBroadcastManager ++ // Use broadcast-based coherence hub - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index 76838d56d..22e0c5535 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -101,7 +101,7 @@ class MultiNoCConfig extends Config( channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }), routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1)) )) ++ - new freechips.rocketchip.rocket.WithNBigCores(8) ++ + new freechips.rocketchip.rocket.WithNHugeCores(8) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++ new chipyard.config.AbstractConfig @@ -180,7 +180,7 @@ class SharedNoCConfig extends Config( "system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6, "pbus" -> 4)) )) ++ - new freechips.rocketchip.rocket.WithNBigCores(8) ++ + new freechips.rocketchip.rocket.WithNHugeCores(8) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ new chipyard.config.AbstractConfig @@ -216,7 +216,7 @@ class SbusRingNoCConfig extends Config( channelParamGen = (a, b) => UserChannelParams(Seq.fill(4) { UserVirtualChannelParams(1) }), routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 2, 2)) )) ++ - new freechips.rocketchip.rocket.WithNBigCores(8) ++ + new freechips.rocketchip.rocket.WithNHugeCores(8) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.AbstractConfig ) @@ -260,7 +260,7 @@ class SbusMeshNoCConfig extends Config( ), beDivision = 4 ), inlineNoC = true) ++ - new freechips.rocketchip.rocket.WithNBigCores(12) ++ + new freechips.rocketchip.rocket.WithNHugeCores(12) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig @@ -286,6 +286,6 @@ class QuadRocketSbusRingNoCConfig extends Config( channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }), routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2)) )) ++ - new freechips.rocketchip.rocket.WithNBigCores(4) ++ + new freechips.rocketchip.rocket.WithNHugeCores(4) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index 97097c8ea..5a4712c4f 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -10,44 +10,44 @@ import freechips.rocketchip.subsystem.{MBUS} class LargeSPIFlashROMRocketConfig extends Config( new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) new chipyard.config.WithSPIFlash ++ // add the SPI flash controller - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class SmallSPIFlashRocketConfig extends Config( new chipyard.harness.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable) new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB) - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class SimBlockDeviceRocketConfig extends Config( new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice new testchipip.iceblk.WithBlockDevice ++ // add block-device module to peripherybus - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class BlockDeviceModelRocketConfig extends Config( new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel new testchipip.iceblk.WithBlockDevice ++ // add block-device module to periphery bus - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include start: GPIORocketConfig class GPIORocketConfig extends Config( new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: GPIORocketConfig class LoopbackNICRocketConfig extends Config( new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback new icenet.WithIceNIC ++ // add an IceNIC - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class MMIORocketConfig extends Config( new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class LBWIFRocketConfig extends Config( @@ -56,14 +56,14 @@ class LBWIFRocketConfig extends Config( new testchipip.soc.WithOffchipBus ++ new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include start: DmiRocket class dmiRocketConfig extends Config( new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: DmiRocket @@ -75,7 +75,7 @@ class dmiCospikeCheckpointingRocketConfig extends Config( new chipyard.config.WithNPMPs(0) ++ // remove PMPs (reduce non-core arch state) new freechips.rocketchip.rocket.WithDebugROB ++ // cospike needs wdata given by the unsynth. debug rom new freechips.rocketchip.rocket.WithCease(false) ++ // remove xrocket ISA extension - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) @@ -91,7 +91,7 @@ class ManyPeripheralsRocketConfig extends Config( new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class UARTTSIRocketConfig extends Config( @@ -100,5 +100,5 @@ class UARTTSIRocketConfig extends Config( new chipyard.config.WithMemoryBusFrequency(10) ++ new chipyard.config.WithFrontBusFrequency(10) ++ new chipyard.config.WithPeripheryBusFrequency(10) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 6e210e0bc..7b2de98c9 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -9,26 +9,26 @@ import org.chipsalliance.cde.config.{Config} // DOC include start: GemminiRocketConfig class GemminiRocketConfig extends Config( new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) // DOC include end: GemminiRocketConfig class FPGemminiRocketConfig extends Config( new gemmini.GemminiFP32DefaultConfig ++ // use FP32Gemmini systolic array GEMM accelerator - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) class LeanGemminiRocketConfig extends Config( new gemmini.LeanGemminiConfig ++ // use Lean Gemmini systolic array GEMM accelerator - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) class LeanGemminiPrintfRocketConfig extends Config( new gemmini.LeanGemminiPrintfConfig ++ // use Lean Gemmini systolic array GEMM accelerator - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) @@ -39,12 +39,12 @@ class MempressRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBanks(8) ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=16, capacityKB=2048) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class AES256ECBRocketConfig extends Config( new aes.WithAES256ECBAccel ++ // use Caliptra AES 256 ECB accelerator - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.WithSystemBusWidth(256) ++ new chipyard.config.AbstractConfig) @@ -55,7 +55,7 @@ class ReRoCCTestConfig extends Config( new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile2 is accum new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile1 is accum new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile0 is accum - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class ReRoCCManyGemminiConfig extends Config( @@ -64,10 +64,10 @@ class ReRoCCManyGemminiConfig extends Config( new gemmini.LeanGemminiConfig ++ // rerocc tile2 is gemmini new gemmini.LeanGemminiConfig ++ // rerocc tile1 is gemmini new gemmini.LeanGemminiConfig ++ // rerocc tile0 is gemmini - new freechips.rocketchip.rocket.WithNBigCores(4) ++ // 4 rocket cores + new freechips.rocketchip.rocket.WithNHugeCores(4) ++ // 4 rocket cores new chipyard.config.AbstractConfig) class ZstdCompressorRocketConfig extends Config( new compressacc.WithZstdCompressor ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index cefeb6f92..e9e4b2c4b 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -9,11 +9,11 @@ import freechips.rocketchip.subsystem.{InCluster} // -------------- class RocketConfig extends Config( - new freechips.rocketchip.rocket.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) class DualRocketConfig extends Config( - new freechips.rocketchip.rocket.WithNBigCores(2) ++ + new freechips.rocketchip.rocket.WithNHugeCores(2) ++ new chipyard.config.AbstractConfig) class TinyRocketConfig extends Config( @@ -26,17 +26,17 @@ class TinyRocketConfig extends Config( new chipyard.config.AbstractConfig) class QuadRocketConfig extends Config( - new freechips.rocketchip.rocket.WithNBigCores(4) ++ // quad-core (4 RocketTiles) + new freechips.rocketchip.rocket.WithNHugeCores(4) ++ // quad-core (4 RocketTiles) new chipyard.config.AbstractConfig) class Cloned64RocketConfig extends Config( new freechips.rocketchip.rocket.WithCloneRocketTiles(63, 0) ++ // copy tile0 63 more times - new freechips.rocketchip.rocket.WithNBigCores(1) ++ // tile0 is a BigRocket + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // tile0 is a BigRocket new chipyard.config.AbstractConfig) class RV32RocketConfig extends Config( new freechips.rocketchip.rocket.WithRV32 ++ // set RocketTiles to be 32-bit - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include start: l1scratchpadrocket @@ -46,7 +46,7 @@ class ScratchpadOnlyRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.rocket.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: l1scratchpadrocket @@ -58,18 +58,18 @@ class MMIOScratchpadOnlyRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.rocket.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class L1ScratchpadRocketConfig extends Config( new chipyard.config.WithRocketICacheScratchpad ++ // use rocket ICache scratchpad new chipyard.config.WithRocketDCacheScratchpad ++ // use rocket DCache scratchpad - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class MulticlockRocketConfig extends Config( new freechips.rocketchip.rocket.WithAsynchronousCDCs(8, 3) ++ // Add async crossings between RocketTile and uncore - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // Frequency specifications new chipyard.config.WithTileFrequency(1000.0) ++ // Matches the maximum frequency of U540 new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit", "clock_tap"), Nil), @@ -87,7 +87,7 @@ class CustomIOChipTopRocketConfig extends Config( new chipyard.example.WithBrokenOutUARTIO ++ new chipyard.example.WithCustomChipTop ++ new chipyard.example.WithCustomIOCells ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) class PrefetchingRocketConfig extends Config( @@ -96,22 +96,22 @@ class PrefetchingRocketConfig extends Config( new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, sits between L1D$ and L2, monitors L1D$ misses to prefetch into L2 new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus new freechips.rocketchip.rocket.WithL1DCacheNonblocking(2) ++ // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) class ClusteredRocketConfig extends Config( - new freechips.rocketchip.rocket.WithNBigCores(4, location=InCluster(1)) ++ - new freechips.rocketchip.rocket.WithNBigCores(4, location=InCluster(0)) ++ + new freechips.rocketchip.rocket.WithNHugeCores(4, location=InCluster(1)) ++ + new freechips.rocketchip.rocket.WithNHugeCores(4, location=InCluster(0)) ++ new freechips.rocketchip.subsystem.WithCluster(1) ++ new freechips.rocketchip.subsystem.WithCluster(0) ++ new chipyard.config.AbstractConfig) class FastRTLSimRocketConfig extends Config( new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class SV48RocketConfig extends Config( new freechips.rocketchip.rocket.WithSV48 ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/SaturnConfigs.scala b/generators/chipyard/src/main/scala/config/SaturnConfigs.scala index 4ff761c1b..9663b96a1 100644 --- a/generators/chipyard/src/main/scala/config/SaturnConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SaturnConfigs.scala @@ -6,52 +6,52 @@ import saturn.common.{VectorParams} // Rocket-integrated configs class MINV64D64RocketConfig extends Config( new saturn.rocket.WithRocketVectorUnit(64, 64, VectorParams.minParams) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class MINV128D64RocketConfig extends Config( new saturn.rocket.WithRocketVectorUnit(128, 64, VectorParams.minParams) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class MINV256D64RocketConfig extends Config( new saturn.rocket.WithRocketVectorUnit(256, 64, VectorParams.minParams) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class REFV128D128RocketConfig extends Config( new saturn.rocket.WithRocketVectorUnit(128, 128, VectorParams.refParams) ++ new chipyard.config.WithSystemBusWidth(128) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class REFV256D64RocketConfig extends Config( new saturn.rocket.WithRocketVectorUnit(256, 64, VectorParams.refParams) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class REFV256D128RocketConfig extends Config( new saturn.rocket.WithRocketVectorUnit(256, 128, VectorParams.refParams) ++ new chipyard.config.WithSystemBusWidth(128) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class REFV512D128RocketConfig extends Config( new saturn.rocket.WithRocketVectorUnit(512, 128, VectorParams.refParams) ++ new chipyard.config.WithSystemBusWidth(128) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class REFV512D256RocketConfig extends Config( new saturn.rocket.WithRocketVectorUnit(512, 256, VectorParams.refParams) ++ new chipyard.config.WithSystemBusWidth(256) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class DMAV256D256RocketConfig extends Config( new saturn.rocket.WithRocketVectorUnit(256, 256, VectorParams.dmaParams) ++ new chipyard.config.WithSystemBusWidth(256) ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) // Shuttle-integrated configs @@ -156,7 +156,7 @@ class MINV128D64RocketCosimConfig extends Config( new saturn.rocket.WithRocketVectorUnit(128, 64, VectorParams.minParams) ++ new freechips.rocketchip.rocket.WithCease(false) ++ new freechips.rocketchip.rocket.WithDebugROB ++ - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) class GENV256D128ShuttleCosimConfig extends Config( diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index dd3175cbc..e5b22d587 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -27,7 +27,7 @@ class TutorialStarterConfig extends Config( // CUSTOMIZE THE CORE // Uncomment out one (or multiple) of the lines below, and choose // how many cores you want. - // new freechips.rocketchip.rocket.WithNBigCores(1) ++ // Specify we want some number of Rocket cores + // new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // Specify we want some number of Rocket cores // new boom.v3.common.WithNSmallBooms(1) ++ // Specify we want some number of BOOM cores // CUSTOMIZE the L2 @@ -46,7 +46,7 @@ class TutorialMMIOConfig extends Config( // new chipyard.example.WithGCD(useAXI4=true) ++ // Use AXI4 version // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration - new freechips.rocketchip.rocket.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig ) @@ -90,6 +90,6 @@ class TutorialNoCConfig extends Config( new chipyard.example.WithStreamingPassthrough ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ - new freechips.rocketchip.rocket.WithNBigCores(2) ++ + new freechips.rocketchip.rocket.WithNHugeCores(2) ++ new chipyard.config.AbstractConfig ) diff --git a/generators/saturn b/generators/saturn index efced6db8..3e7999aee 160000 --- a/generators/saturn +++ b/generators/saturn @@ -1 +1 @@ -Subproject commit efced6db88573b1687a3a889160f19152878f6d2 +Subproject commit 3e7999aee13b9b6d3dbd310d9ca98c20ed5bc098