From 894721670772ed55e99abdf4c6698bbb150d9616 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Wed, 8 Mar 2023 17:57:31 +0000 Subject: [PATCH 1/7] first pass at xcelium support --- generators/testchipip | 2 +- scripts/build-toolchain-extra.sh | 6 ++ sims/xcelium/Makefile | 141 +++++++++++++++++++++++++++ toolchains/riscv-tools/riscv-isa-sim | 2 +- xcelium.mk | 77 +++++++++++++++ 5 files changed, 226 insertions(+), 2 deletions(-) create mode 100644 sims/xcelium/Makefile create mode 100644 xcelium.mk diff --git a/generators/testchipip b/generators/testchipip index 6e8a684242..2d78a04538 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6e8a68424216c9a02916af16a15850f40a534a22 +Subproject commit 2d78a045386137de3bfd10d6d970db761a92213a diff --git a/scripts/build-toolchain-extra.sh b/scripts/build-toolchain-extra.sh index 54afe98360..0914f23afa 100755 --- a/scripts/build-toolchain-extra.sh +++ b/scripts/build-toolchain-extra.sh @@ -111,4 +111,10 @@ if [ $TOOLCHAIN == "riscv-tools" ]; then make -C $RDIR/generators/gemmini/software/libgemmini install fi +echo '==> Installing DRAMSim2 Shared Library' +cd $RDIR +cd tools/DRAMSim2 +make libdramsim.so +cp libdramsim.so $RISCV/lib/ + echo "Extra Toolchain Utilities/Tests Build Complete!" diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile new file mode 100644 index 0000000000..6604b114e3 --- /dev/null +++ b/sims/xcelium/Makefile @@ -0,0 +1,141 @@ +######################################################################################### +# xcelium makefile +######################################################################################### + +define CAD_INFO_HEADER +# -------------------------------------------------------------------------------- +# This script was written and developed by Chipyard at UC Berkeley; however, the +# underlying commands and reports are copyrighted by Cadence. We thank Cadence for +# granting permission to share our research to help promote and foster the next +# generation of innovators. +# -------------------------------------------------------------------------------- +endef + +export CAD_INFO_HEADER + +######################################################################################### +# general path variables +######################################################################################### +base_dir=$(abspath ../..) +sim_dir=$(abspath .) + +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/variables.mk + +######################################################################################### +# name of simulator (used to generate *.f arguments file) +######################################################################################### +sim_name = xrun + +######################################################################################### +# vcs simulator types and rules +######################################################################################### +sim_prefix = simx +sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) +sim_debug = $(sim)-debug +sim_workdir = $(sim).xcelium.d +sim_run_tcl = $(sim)_run.tcl +sim_debug_run_tcl = $(sim_debug)_run.tcl + +include $(base_dir)/xcelium.mk + +.PHONY: default debug +default: $(sim) +debug: $(sim_debug) + +######################################################################################### +# simulation requirements +######################################################################################### +SIM_FILE_REQS += \ + $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v + +# copy files but ignore *.h files in *.f since xcelium has -Wcxx include +$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR) + cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) + $(foreach file,\ + $(SIM_FILE_REQS),\ + $(if $(filter %.h,$(file)),\ + ,\ + echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;)) + +######################################################################################### +# import other necessary rules and variables +######################################################################################### +include $(base_dir)/common.mk + +######################################################################################### +# vcs binary and arguments +######################################################################################### +VCS = xrun -64bit -elaborate +#vcs -full64 + +VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES) + +######################################################################################### +# vcs build paths +######################################################################################### +model_dir = $(build_dir)/$(long_name) +model_dir_debug = $(build_dir)/$(long_name).debug + +######################################################################################### +# vcs simulator rules +######################################################################################### + +$(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) + rm -rf $(model_dir) + $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -xmlibdirname $@ + +$(sim_run_tcl): $(sim_workdir) + echo "$$CAD_INFO_HEADER" > $(sim_run_tcl) + echo "run" >> $(sim_run_tcl) + echo "exit" >> $(sim_run_tcl) + +$(sim): $(sim_workdir) $(sim_run_tcl) + echo "#!/usr/bin/env bash" > $(sim) + echo "$$CAD_INFO_HEADER" >> $(sim) + echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 xrun +verbose +binary=super-awesome-program +permissive -R -xmlibdirname $(sim_workdir) -input $(sim_run_tcl)" >> $(sim) + chmod +x $(sim) + +$(sim_debug_run_tcl): $(sim_workdir) + echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl) + echo "database -open default_vcd_dump -vcd -into $(sim_out_name).vcd" >> $(sim_debug_run_tcl) + echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl) + echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl) + echo "run" >> $(sim_debug_run_tcl) + echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl) + echo "exit" >> $(sim_debug_run_tcl) + + +$(sim_debug): $(sim_workdir) $(sim_debug_run_tcl) + echo "#!/usr/bin/env bash" > $(sim_debug) + echo "$$CAD_INFO_HEADER" >> $(sim_debug) + echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 xrun +verbose +binary=super-awesome-program +permissive -R -xmlibdirname $(sim_workdir) -input $(sim_debug_run_tcl)" >> $(sim_debug) + chmod +x $(sim_debug) + + +######################################################################################### +# create vcs vpd/fsdb rules +######################################################################################### +.PRECIOUS: $(output_dir)/%.vpd %.vpd +$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + +.PRECIOUS: $(output_dir)/%.fsdb %.fsdb +$(output_dir)/%.fsdb: $(output_dir)/% $(sim_debug) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +fsdbfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + + +######################################################################################### +# general cleanup rules +######################################################################################### +.PHONY: clean clean-sim clean-sim-debug +clean: + rm -rf $(gen_dir) $(sim_prefix)-* ucli.key + +clean-sim: + rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key + +clean-sim-debug: + rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_debug).daidir ucli.key diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index e7d6aff19a..cd0a5dc550 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit e7d6aff19a071a059f1b9c2328ee4dac83bc677a +Subproject commit cd0a5dc55090ca8c4be4c7fb2a7937629c0eccb9 diff --git a/xcelium.mk b/xcelium.mk new file mode 100644 index 0000000000..92ff34cf47 --- /dev/null +++ b/xcelium.mk @@ -0,0 +1,77 @@ +HELP_COMPILATION_VARIABLES += \ +" USE_VPD = set to '1' to build VCS simulator to emit VPD instead of FSDB." + +HELP_SIMULATION_VARIABLES += \ +" USE_VPD = set to '1' to run VCS simulator emitting VPD instead of FSDB." + +ifndef USE_VPD +WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb +else +WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +endif + +# If ntb_random_seed unspecified, vcs uses 1 as constant seed. +# Set ntb_random_seed_automatic to actually get a random seed +ifdef RANDOM_SEED +SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED) +else +SEED_FLAG=+ntb_random_seed_automatic +endif + +CLOCK_PERIOD ?= 1.0 +RESET_DELAY ?= 777.7 + +#---------------------------------------------------------------------------------------- +# gcc configuration/optimization +#---------------------------------------------------------------------------------------- +include $(base_dir)/sims/common-sim-flags.mk + + +XC_CXX_PREFIX=-Wcxx, +XC_LD_PREFIX=-Wld, + +REMOVE_RPATH=-Wl,-rpath% + +VCS_CXXFLAGS = $(addprefix $(XC_CXX_PREFIX), $(SIM_CXXFLAGS)) +VCS_LDFLAGS = $(addprefix $(XC_LD_PREFIX), $(filter-out $(REMOVE_RPATH), $(SIM_LDFLAGS))) + +# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate) +VCS_CC_OPTS = \ + $(VCS_CXXFLAGS) \ + $(VCS_LDFLAGS) \ + -enable_rpath + +#-LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \ +# $(filter -l%,$(VCS_LDFLAGS)) + +VCS_NONCC_OPTS = \ + -fast_recompilation \ + -top $(TB) \ + -sv \ + -ALLOWREDEFINITION \ + -timescale 1ns/10ps \ + -define INTCNOPWR \ + -define INTC_NO_PWR_PINS \ + -define INTC_EMULATION \ + -f $(sim_common_files) \ + -logfile xrun_elab.log \ + -glsperf \ + -genafile access.txt \ + -notimingchecks \ + -delay_mode zero + +PREPROC_DEFINES = \ + -define VCS \ + -define CLOCK_PERIOD=$(CLOCK_PERIOD) \ + -define RESET_DELAY=$(RESET_DELAY) \ + -define PRINTF_COND=$(TB).printf_cond \ + -define STOP_COND=!$(TB).reset \ + -define MODEL=$(MODEL) \ + -define RANDOMIZE_MEM_INIT \ + -define RANDOMIZE_REG_INIT \ + -define RANDOMIZE_GARBAGE_ASSIGN \ + -define RANDOMIZE_INVALID_ASSIGN + +ifndef USE_VPD +PREPROC_DEFINES += +define+FSDB +endif From 7c2ec8fb4c0c8a173fa207ebde29956b6c7360c6 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 9 Mar 2023 01:48:25 +0000 Subject: [PATCH 2/7] more fixes --- generators/testchipip | 2 +- sims/xcelium/Makefile | 41 +++++++++++++-------------- sims/xcelium/arg-reshuffle | 21 ++++++++++++++ toolchains/riscv-tools/riscv-isa-sim | 2 +- xcelium.mk | 42 ++++++++++------------------ 5 files changed, 57 insertions(+), 51 deletions(-) create mode 100755 sims/xcelium/arg-reshuffle diff --git a/generators/testchipip b/generators/testchipip index 2d78a04538..dead693f8f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 2d78a045386137de3bfd10d6d970db761a92213a +Subproject commit dead693f8f317bfeeb4eb777c4d58c4427fbba31 diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile index 6604b114e3..ec8b84372a 100644 --- a/sims/xcelium/Makefile +++ b/sims/xcelium/Makefile @@ -30,7 +30,7 @@ include $(base_dir)/variables.mk sim_name = xrun ######################################################################################### -# vcs simulator types and rules +# xcelium simulator types and rules ######################################################################################### sim_prefix = simx sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) @@ -66,26 +66,25 @@ $(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR) include $(base_dir)/common.mk ######################################################################################### -# vcs binary and arguments +# xcelium binary and arguments ######################################################################################### -VCS = xrun -64bit -elaborate -#vcs -full64 - -VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES) +XCELIUM = xrun +XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES) ######################################################################################### -# vcs build paths +# xcelium build paths ######################################################################################### model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug + ######################################################################################### -# vcs simulator rules +# xcelium simulator rules ######################################################################################### $(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf $(model_dir) - $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -xmlibdirname $@ + $(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS) $(sim_run_tcl): $(sim_workdir) echo "$$CAD_INFO_HEADER" > $(sim_run_tcl) @@ -95,12 +94,13 @@ $(sim_run_tcl): $(sim_workdir) $(sim): $(sim_workdir) $(sim_run_tcl) echo "#!/usr/bin/env bash" > $(sim) echo "$$CAD_INFO_HEADER" >> $(sim) - echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 xrun +verbose +binary=super-awesome-program +permissive -R -xmlibdirname $(sim_workdir) -input $(sim_run_tcl)" >> $(sim) + cat arg-reshuffle >> $(sim) + echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim) chmod +x $(sim) $(sim_debug_run_tcl): $(sim_workdir) echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl) - echo "database -open default_vcd_dump -vcd -into $(sim_out_name).vcd" >> $(sim_debug_run_tcl) + echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl) echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl) echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl) echo "run" >> $(sim_debug_run_tcl) @@ -111,22 +111,19 @@ $(sim_debug_run_tcl): $(sim_workdir) $(sim_debug): $(sim_workdir) $(sim_debug_run_tcl) echo "#!/usr/bin/env bash" > $(sim_debug) echo "$$CAD_INFO_HEADER" >> $(sim_debug) - echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 xrun +verbose +binary=super-awesome-program +permissive -R -xmlibdirname $(sim_workdir) -input $(sim_debug_run_tcl)" >> $(sim_debug) + cat arg-reshuffle >> $(sim_debug) + echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug) + echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug) chmod +x $(sim_debug) ######################################################################################### -# create vcs vpd/fsdb rules +# create vcd rules ######################################################################################### -.PRECIOUS: $(output_dir)/%.vpd %.vpd -$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) +.PRECIOUS: $(output_dir)/%.vcd %.vcd +$(output_dir)/%.vcd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) -.PRECIOUS: $(output_dir)/%.fsdb %.fsdb -$(output_dir)/%.fsdb: $(output_dir)/% $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +fsdbfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) - - ######################################################################################### # general cleanup rules ######################################################################################### @@ -135,7 +132,7 @@ clean: rm -rf $(gen_dir) $(sim_prefix)-* ucli.key clean-sim: - rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key + rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log clean-sim-debug: - rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_debug).daidir ucli.key + rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_workdir) $(sim_debug_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log diff --git a/sims/xcelium/arg-reshuffle b/sims/xcelium/arg-reshuffle new file mode 100755 index 0000000000..7ccca2177b --- /dev/null +++ b/sims/xcelium/arg-reshuffle @@ -0,0 +1,21 @@ + +regular_args="" +target_args="+permissive" +for var in "$@" +do + if [[ $var = -* ]] || [[ $var = +* ]] + then + if [[ $var = +vcdfile=* ]] + then + XCELIUM_WAVEFORM_FLAG=${var/+vcdfile=/""} + else + regular_args="$regular_args $var" + fi + else + target_args="$target_args +target-argument=$var" + fi +done +target_args="$target_args +permissive-off" + +INPUT_ARGS="$regular_args $target_args" + diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index cd0a5dc550..34bebfe311 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit cd0a5dc55090ca8c4be4c7fb2a7937629c0eccb9 +Subproject commit 34bebfe31183289b5428b9a363a4596750030d3f diff --git a/xcelium.mk b/xcelium.mk index 92ff34cf47..3d9ed5ab2a 100644 --- a/xcelium.mk +++ b/xcelium.mk @@ -1,16 +1,7 @@ -HELP_COMPILATION_VARIABLES += \ -" USE_VPD = set to '1' to build VCS simulator to emit VPD instead of FSDB." -HELP_SIMULATION_VARIABLES += \ -" USE_VPD = set to '1' to run VCS simulator emitting VPD instead of FSDB." +WAVEFORM_FLAG=+vcdfile=$(sim_out_name).vcd -ifndef USE_VPD -WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb -else -WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd -endif - -# If ntb_random_seed unspecified, vcs uses 1 as constant seed. +# If ntb_random_seed unspecified, xcelium uses 1 as constant seed. # Set ntb_random_seed_automatic to actually get a random seed ifdef RANDOM_SEED SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED) @@ -32,19 +23,21 @@ XC_LD_PREFIX=-Wld, REMOVE_RPATH=-Wl,-rpath% -VCS_CXXFLAGS = $(addprefix $(XC_CXX_PREFIX), $(SIM_CXXFLAGS)) -VCS_LDFLAGS = $(addprefix $(XC_LD_PREFIX), $(filter-out $(REMOVE_RPATH), $(SIM_LDFLAGS))) +XCELIUM_CXXFLAGS = $(addprefix $(XC_CXX_PREFIX), $(SIM_CXXFLAGS)) +XCELIUM_LDFLAGS = $(addprefix $(XC_LD_PREFIX), $(filter-out $(REMOVE_RPATH), $(SIM_LDFLAGS))) -# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate) -VCS_CC_OPTS = \ - $(VCS_CXXFLAGS) \ - $(VCS_LDFLAGS) \ - -enable_rpath +XCELIUM_COMMON_ARGS = \ + -64bit \ + -xmlibdirname $(sim_workdir) \ + -l /dev/null \ + -log_xmsc_run /dev/null -#-LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \ -# $(filter -l%,$(VCS_LDFLAGS)) +XCELIUM_CC_OPTS = \ + $(XCELIUM_CXXFLAGS) \ + $(XCELIUM_LDFLAGS) \ + -enable_rpath -VCS_NONCC_OPTS = \ +XCELIUM_NONCC_OPTS = \ -fast_recompilation \ -top $(TB) \ -sv \ @@ -54,14 +47,12 @@ VCS_NONCC_OPTS = \ -define INTC_NO_PWR_PINS \ -define INTC_EMULATION \ -f $(sim_common_files) \ - -logfile xrun_elab.log \ -glsperf \ - -genafile access.txt \ -notimingchecks \ -delay_mode zero PREPROC_DEFINES = \ - -define VCS \ + -define XCELIUM \ -define CLOCK_PERIOD=$(CLOCK_PERIOD) \ -define RESET_DELAY=$(RESET_DELAY) \ -define PRINTF_COND=$(TB).printf_cond \ @@ -72,6 +63,3 @@ PREPROC_DEFINES = \ -define RANDOMIZE_GARBAGE_ASSIGN \ -define RANDOMIZE_INVALID_ASSIGN -ifndef USE_VPD -PREPROC_DEFINES += +define+FSDB -endif From c6d5e48347b3749aefa0eba84b63fab417160ad8 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Wed, 8 Mar 2023 18:26:43 -0800 Subject: [PATCH 3/7] Update arg-reshuffle --- sims/xcelium/arg-reshuffle | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/sims/xcelium/arg-reshuffle b/sims/xcelium/arg-reshuffle index 7ccca2177b..08176864ec 100755 --- a/sims/xcelium/arg-reshuffle +++ b/sims/xcelium/arg-reshuffle @@ -1,4 +1,13 @@ +# this is a wrapper that is copied into xcelium sim run scripts that +# re-maps arguments from the argument pattern used by other +# simulators (vcs, verilator) to the pattern required by xcelium. +# +# mainly: +# * +vcdfile=VAL -> XCELIUM_WAVEFORM_FLAG=VAL, to be passed in as env var +# * arguments not prefixed with a + or - are treated as the arguments to +# the target and are passed in instead with the +target-argument plusarg + regular_args="" target_args="+permissive" for var in "$@" From d70d4069c6910adf2d8551569d424c7679b019d8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 Mar 2023 14:16:07 -0700 Subject: [PATCH 4/7] [ci skip] Move xcelium tcls to generated-src --- sims/xcelium/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile index ec8b84372a..65e4d4c529 100644 --- a/sims/xcelium/Makefile +++ b/sims/xcelium/Makefile @@ -35,9 +35,9 @@ sim_name = xrun sim_prefix = simx sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim)-debug -sim_workdir = $(sim).xcelium.d -sim_run_tcl = $(sim)_run.tcl -sim_debug_run_tcl = $(sim_debug)_run.tcl +sim_workdir = $(build_dir)/xcelium.d +sim_run_tcl = $(build_dir)/xcelium_run.tcl +sim_debug_run_tcl = $(build_dir)/xcelium_debug_run.tcl include $(base_dir)/xcelium.mk From 29005da8b084dbe3c69293477e2e8e164dbafdc7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 Mar 2023 14:18:01 -0700 Subject: [PATCH 5/7] Remove extraneous stuff from xcelium makefile --- sims/xcelium/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile index 65e4d4c529..03ea00ace9 100644 --- a/sims/xcelium/Makefile +++ b/sims/xcelium/Makefile @@ -129,10 +129,10 @@ $(output_dir)/%.vcd: $(output_dir)/% $(sim_debug) ######################################################################################### .PHONY: clean clean-sim clean-sim-debug clean: - rm -rf $(gen_dir) $(sim_prefix)-* ucli.key + rm -rf $(gen_dir) $(sim_prefix)-* clean-sim: - rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log + rm -rf $(model_dir) $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log clean-sim-debug: - rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_workdir) $(sim_debug_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log + rm -rf $(model_dir_debug) $(sim_debug) $(sim_workdir) $(sim_debug_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log From 651ad51c256c866342a794a1c1eba50025ae5905 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 Mar 2023 14:18:44 -0700 Subject: [PATCH 6/7] Add .gitignore to xcelium directory --- sims/xcelium/.gitignore | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 sims/xcelium/.gitignore diff --git a/sims/xcelium/.gitignore b/sims/xcelium/.gitignore new file mode 100644 index 0000000000..254f02f7f5 --- /dev/null +++ b/sims/xcelium/.gitignore @@ -0,0 +1,3 @@ +* +!.gitignore +*Makefile \ No newline at end of file From 3fc796561781f19dac9b2717a5905ddab0485823 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 Mar 2023 14:48:32 -0700 Subject: [PATCH 7/7] [ci skip] Add LD_PRELOAD comment to xcelium makefile --- sims/xcelium/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile index 03ea00ace9..12b3108767 100644 --- a/sims/xcelium/Makefile +++ b/sims/xcelium/Makefile @@ -91,6 +91,8 @@ $(sim_run_tcl): $(sim_workdir) echo "run" >> $(sim_run_tcl) echo "exit" >> $(sim_run_tcl) +# The system libstdc++ may not link correctly with some of our dynamic libs, so +# force loading the conda one (if present) with LD_PRELOAD $(sim): $(sim_workdir) $(sim_run_tcl) echo "#!/usr/bin/env bash" > $(sim) echo "$$CAD_INFO_HEADER" >> $(sim)