diff --git a/.github/workflows/chipyard-full-flow.yml b/.github/workflows/chipyard-full-flow.yml
index 5179be0f01..0664bb604f 100644
--- a/.github/workflows/chipyard-full-flow.yml
+++ b/.github/workflows/chipyard-full-flow.yml
@@ -115,7 +115,7 @@ jobs:
 
           cd vlsi
 
-          # NOTE: most conda installs are in separate conda envs because they mess up 
+          # NOTE: most conda installs are in separate conda envs because they mess up
           #   each other's versions (for no apparent reason) and we need the latest versions
           conda config --add channels defaults
           conda config --add channels litex-hub
@@ -166,7 +166,7 @@ jobs:
     name: cleanup
     needs: [run-tutorial]
     runs-on: ferry
-    if: ${{ always() && contains(join(needs.*.result, ','), 'success') }}
+    if: ${{ always() }}
     steps:
       - name: Delete repo copy and conda env
         run: |
diff --git a/.gitignore b/.gitignore
index 9c73c6e1c6..ac8e84d09b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -26,3 +26,4 @@ project/metals.sbt
 project/project/
 .ivy2
 .sbt
+.classpath_cache/
diff --git a/build.sbt b/build.sbt
index 8160a4f92e..6f72940ab2 100644
--- a/build.sbt
+++ b/build.sbt
@@ -4,14 +4,34 @@ import Tests._
 // implicit one
 lazy val chipyardRoot = Project("chipyardRoot", file("."))
 
+// keep chisel/firrtl specific class files, rename other conflicts
+val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
+  import sbtassembly.Assembly.{Project, Library}
+  val nm = dep match {
+    case p: Project => p.name
+    case l: Library => l.moduleCoord.name
+  }
+  if (Seq("firrtl", "chisel3").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version
+    dep.target
+  } else {
+    "renamed/" + dep.target
+  }
+}
+
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
   version := "1.6",
   scalaVersion := "2.13.10",
   assembly / test := {},
-  assembly / assemblyMergeStrategy := { _ match {
-    case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
-    case _ => MergeStrategy.first}},
+  assembly / assemblyMergeStrategy := {
+    case PathList("chisel3", "stage", xs @ _*) => chiselFirrtlMergeStrategy
+    case PathList("firrtl", "stage", xs @ _*) => chiselFirrtlMergeStrategy
+    // should be safe in JDK11: https://stackoverflow.com/questions/54834125/sbt-assembly-deduplicate-module-info-class
+    case x if x.endsWith("module-info.class") => MergeStrategy.discard
+    case x =>
+      val oldStrategy = (assembly / assemblyMergeStrategy).value
+      oldStrategy(x)
+  },
   scalacOptions ++= Seq(
     "-deprecation",
     "-unchecked",
@@ -86,8 +106,6 @@ lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
   .settings(commonSettings)
   .settings(
     libraryDependencies ++= Seq(
-      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
       "org.scalatest" %% "scalatest" % "3.2.0" % "test"
     )
   )
@@ -97,8 +115,6 @@ lazy val rocketMacros  = (project in rocketChipDir / "macros")
   .settings(
     libraryDependencies ++= Seq(
       "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
-      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
     )
   )
 
@@ -225,7 +241,6 @@ lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "sr
 lazy val tapeout = (project in file("./tools/barstools/"))
   .settings(chiselSettings)
   .settings(chiselTestSettings)
-  .enablePlugins(sbtassembly.AssemblyPlugin)
   .settings(commonSettings)
 
 lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
diff --git a/common.mk b/common.mk
index 2dce97ec9b..f335a212b7 100644
--- a/common.mk
+++ b/common.mk
@@ -16,7 +16,6 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_LDFLAGS         = additional LDFLAGS for building simulators" \
 "   EXTRA_SIM_SOURCES         = additional simulation sources needed for simulator" \
 "   EXTRA_SIM_REQS            = additional make requirements to build the simulator" \
-"   ENABLE_SBT_THIN_CLIENT    = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \
 "   ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
 "   ENABLE_YOSYS_FLOW         = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
 "   EXTRA_CHISEL_OPTIONS      = additional options to pass to the Chisel compiler" \
@@ -45,11 +44,13 @@ HELP_COMMANDS += \
 "   run-binary                  = run [./$(shell basename $(sim))] and log instructions to file" \
 "   run-binary-fast             = run [./$(shell basename $(sim))] and don't log instructions" \
 "   run-binary-debug            = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \
+"   run-binaries                = run [./$(shell basename $(sim))] and log instructions to file" \
+"   run-binaries-fast           = run [./$(shell basename $(sim))] and don't log instructions" \
+"   run-binaries-debug          = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \
 "   verilog                     = generate intermediate verilog files from chisel elaboration and firrtl passes" \
 "   firrtl                      = generate intermediate firrtl files from chisel elaboration" \
 "   run-tests                   = run all assembly and benchmark tests" \
 "   launch-sbt                  = start sbt terminal" \
-"   {shutdown,start}-sbt-server = shutdown or start sbt server if using ENABLE_SBT_THIN_CLIENT" \
 "   find-config-fragments       = list all config. fragments"
 
 #########################################################################################
@@ -102,12 +103,24 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
 	cp -f $< $@
 
 #########################################################################################
-# create firrtl file rule and variables
+# compile scala jars
+#########################################################################################
+$(CHIPYARD_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
+	mkdir -p $(dir $@)
+	$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
+
+# order only dependency between sbt runs needed to avoid concurrent sbt runs
+$(TAPEOUT_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(CHIPYARD_CLASSPATH_TARGETS)
+	mkdir -p $(dir $@)
+	$(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH))
+
+#########################################################################################
+# verilog generation pipeline
 #########################################################################################
 # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
-$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS)
+$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS)
 	mkdir -p $(build_dir)
-	(set -o pipefail && $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\
+	(set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\
 		--target-dir $(build_dir) \
 		--name $(long_name) \
 		--top-module $(MODEL_PACKAGE).$(MODEL) \
@@ -192,9 +205,9 @@ endif
 	if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
 
 $(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX)
-$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
+$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
 	rm -rf $(GEN_COLLATERAL_DIR)
-	$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateModelStageMain,\
+	$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\
 		--no-dedup \
 		--output-file $(SFC_FIRRTL_BASENAME) \
 		--output-annotation-file $(SFC_ANNO_FILE) \
@@ -260,12 +273,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &:  $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
 TOP_MACROCOMPILER_MODE ?= --mode synflops
-$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TOP_SMEMS_CONF)
-	$(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
+$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF)
+	$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
 
 MODEL_MACROCOMPILER_MODE = --mode synflops
-$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE)
-	$(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
+$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE)
+	$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
 
 ########################################################################################
 # remove duplicate files and headers in list of simulation file inputs
@@ -287,37 +300,70 @@ verilog: $(sim_common_files)
 # helper rules to run simulations
 #########################################################################################
 .PHONY: run-binary run-binary-fast run-binary-debug run-fast
+	%.check-exists check-binary check-binaries
 
 check-binary:
 ifeq (,$(BINARY))
 	$(error BINARY variable is not set. Set it to the simulation binary)
 endif
-ifneq (none,$(BINARY))
-ifeq ("$(wildcard $(BINARY))","")
-	$(error BINARY=$(BINARY) not found)
-endif
+
+check-binaries:
+ifeq (,$(BINARIES))
+	$(error BINARIES variable is not set. Set it to the list of simulation binaries to run)
 endif
 
+%.check-exists:
+	if [ "$*" != "none" ] && [ ! -f "$*" ]; then printf "\n\nBinary $* not found\n\n"; exit 1; fi
+
 # allow you to override sim prereq
 ifeq (,$(BREAK_SIM_PREREQ))
 SIM_PREREQ = $(sim)
 SIM_DEBUG_PREREQ = $(sim_debug)
 endif
 
+# Function to generate the loadmem flag. First arg is the binary
+ifeq ($(LOADMEM),1)
+# If LOADMEM=1, assume BINARY is the loadmem elf
+get_loadmem_flag = +loadmem=$(1)
+else ifneq ($(LOADMEM),)
+# Otherwise, assume the variable points to an elf file
+get_loadmem_flag = +loadmem=$(LOADMEM)
+endif
+
+ifneq ($(LOADARCH),)
+get_loadarch_flag = +loadarch=$(subst mem.elf,loadarch,$(1))
+endif
+
+# get the output path base name for simulation outputs, First arg is the binary
+get_sim_out_name = $(output_dir)/$(call get_out_name,$(1))
+# sim flags that are common to run-binary/run-binary-fast/run-binary-debug
+get_common_sim_flags = $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(call get_loadmem_flag,$(1)) $(call get_loadarch_flag,$(1))
+
+.PHONY: %.run %.run.debug %.run.fast
+
 # run normal binary with hardware-logged insn dissassembly
-run-binary: $(SIM_PREREQ) check-binary | $(output_dir)
-	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
+run-binary: check-binary $(BINARY).run
+run-binaries: check-binaries $(addsuffix .run,$(BINARIES))
+
+%.run: %.check-exists $(SIM_PREREQ) | $(output_dir)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
 
 # run simulator as fast as possible (no insn disassembly)
-run-binary-fast: $(SIM_PREREQ) check-binary | $(output_dir)
-	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null | tee $(sim_out_name).log)
+run-binary-fast: check-binary $(BINARY).run.fast
+run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES))
+
+%.run.fast: %.check-exists $(SIM_PREREQ) | $(output_dir)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(PERMISSIVE_OFF) $* </dev/null | tee $(call get_sim_out_name,$*).log)
 
 # run simulator with as much debug info as possible
-run-binary-debug: $(SIM_DEBUG_PREREQ) check-binary | $(output_dir)
-ifneq (none,$(BINARY))
-	riscv64-unknown-elf-objdump -D $(BINARY) > $(sim_out_name).dump
+run-binary-debug: check-binary $(BINARY).run.debug
+run-binaries-debug: check-binaries $(addsuffix .run.debug,$(BINARIES))
+
+%.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir)
+ifneq (none,$*)
+	riscv64-unknown-elf-objdump -D $* > $(call get_sim_out_name,$*).dump
 endif
-	(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$*)) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
 
 run-fast: run-asm-tests-fast run-bmark-tests-fast
 
@@ -325,11 +371,11 @@ run-fast: run-asm-tests-fast run-bmark-tests-fast
 # helper rules to run simulator with fast loadmem
 # LEGACY - use LOADMEM=1 instead
 #########################################################################################
-run-binary-hex: run-binary
+run-binary-hex: $(BINARY).run
 run-binary-hex: override SIM_FLAGS += +loadmem=$(BINARY)
-run-binary-debug-hex: run-binary-debug
+run-binary-debug-hex: $(BINARY).run.debug
 run-binary-debug-hex: override SIM_FLAGS += +loadmem=$(BINARY)
-run-binary-fast-hex: run-binary-fast
+run-binary-fast-hex: $(BINARY).run.fast
 run-binary-fast-hex: override SIM_FLAGS += +loadmem=$(BINARY)
 
 #########################################################################################
@@ -357,7 +403,6 @@ endif
 #######################################
 # Rules for building DRAMSim2 library
 #######################################
-
 dramsim_dir = $(base_dir)/tools/DRAMSim2
 dramsim_lib = $(dramsim_dir)/libdramsim.a
 
@@ -365,27 +410,12 @@ $(dramsim_lib):
 	$(MAKE) -C $(dramsim_dir) $(notdir $@)
 
 ################################################
-# Helper to run SBT or manage the SBT server
+# Helper to run SBT
 ################################################
-
 SBT_COMMAND ?= shell
 .PHONY: launch-sbt
 launch-sbt:
-	cd $(base_dir) && $(SBT_NON_THIN) "$(SBT_COMMAND)"
-
-.PHONY: check-thin-client
-check-thin-client:
-ifeq (,$(ENABLE_SBT_THIN_CLIENT))
-	$(error ENABLE_SBT_THIN_CLIENT not set.)
-endif
-
-.PHONY: shutdown-sbt-server
-shutdown-sbt-server: check-thin-client
-	cd $(base_dir) && $(SBT) "shutdown"
-
-.PHONY: start-sbt-server
-start-sbt-server: check-thin-client
-	cd $(base_dir) && $(SBT) "exit"
+	cd $(base_dir) && $(SBT) "$(SBT_COMMAND)"
 
 #########################################################################################
 # print help text (and other help)
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index b1b70b6584..c1c809ebd5 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit b1b70b65848d56a381043a80666afe3d79ef5a67
+Subproject commit c1c809ebd5c9a76cd60d8c3169cea4bf4b2fa8fd
diff --git a/project/plugins.sbt b/project/plugins.sbt
index 2425544f63..36e1e8b64a 100644
--- a/project/plugins.sbt
+++ b/project/plugins.sbt
@@ -1,3 +1,3 @@
-addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0")
+addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "2.1.1")
 addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.10.4")
-addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.3")
+addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.6")
diff --git a/scripts/repo-clean.sh b/scripts/repo-clean.sh
index d6231621c9..c966f2652e 100755
--- a/scripts/repo-clean.sh
+++ b/scripts/repo-clean.sh
@@ -26,9 +26,9 @@ rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log
     popd
 )
 (
-    if [ -d $RDIR/generators/cva6/src/main/resources/vsrc/cva6 ]
+    if [ -d $RDIR/generators/cva6/src/main/resources/cva6/vsrc ]
     then
-        pushd $RDIR/generators/cva6/src/main/resources/vsrc/cva6
+        pushd $RDIR/generators/cva6/src/main/resources/cva6/vsrc
         if [ -d cva6 ]
         then
 	    git submodule deinit -f cva6
diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile
index fc0a9fdb96..8517fc1de5 100644
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -93,7 +93,7 @@ $(output_dir)/%.fsdb: $(output_dir)/% $(sim_debug)
 #########################################################################################
 .PHONY: clean clean-sim clean-sim-debug
 clean:
-	rm -rf $(gen_dir) $(sim_prefix)-* ucli.key
+	rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-* ucli.key
 
 clean-sim:
 	rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key
diff --git a/sims/vcs/vcs.mk b/sims/vcs/vcs.mk
index f816f102a0..0a26a48788 100644
--- a/sims/vcs/vcs.mk
+++ b/sims/vcs/vcs.mk
@@ -5,9 +5,9 @@ HELP_SIMULATION_VARIABLES += \
 "   USE_VPD                = set to '1' to run VCS simulator emitting VPD instead of FSDB."
 
 ifndef USE_VPD
-WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb
+get_waveform_flag=+fsdbfile=$(1).fsdb
 else
-WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
+get_waveform_flag=+vcdplusfile=$(1).vpd
 endif
 
 # If ntb_random_seed unspecified, vcs uses 1 as constant seed.
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index 11b803316a..8cf51e2360 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -96,7 +96,7 @@ USE_FST ?= 0
 TRACING_OPTS := $(if $(filter $(USE_FST),0),\
 	                  --trace,--trace-fst --trace-threads 1)
 # TODO: consider renaming +vcdfile in TestDriver.v to +waveformfile (or similar)
-WAVEFORM_FLAG := +vcdfile=$(sim_out_name).$(if $(filter $(USE_FST),0),vcd,fst)
+get_waveform_flag = +vcdfile=$(1).$(if $(filter $(USE_FST),0),vcd,fst)
 
 #----------------------------------------------------------------------------------------
 # verilation configuration/optimization
@@ -226,7 +226,7 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 #########################################################################################
 .PHONY: clean clean-sim clean-sim-debug
 clean:
-	rm -rf $(gen_dir) $(sim_prefix)-*
+	rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
 
 clean-sim:
 	rm -rf $(model_dir) $(sim)
diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile
index 2ca75d917f..e37c12a181 100644
--- a/sims/xcelium/Makefile
+++ b/sims/xcelium/Makefile
@@ -77,7 +77,6 @@ XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES)
 model_dir = $(build_dir)/$(long_name)
 model_dir_debug = $(build_dir)/$(long_name).debug
 
-
 #########################################################################################
 # xcelium simulator rules
 #########################################################################################
@@ -87,37 +86,35 @@ $(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
 	$(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS)
 
 $(sim_run_tcl): $(sim_workdir)
-	echo "$$CAD_INFO_HEADER" > $(sim_run_tcl)
-	echo "run" >> $(sim_run_tcl)
-	echo "exit" >> $(sim_run_tcl)
+	echo "$$CAD_INFO_HEADER" > $@
+	echo "run" >> $@
+	echo "exit" >> $@
 
 # The system libstdc++ may not link correctly with some of our dynamic libs, so
 # force loading the conda one (if present) with LD_PRELOAD
 $(sim): $(sim_workdir) $(sim_run_tcl)
-	echo "#!/usr/bin/env bash" > $(sim)
-	echo "$$CAD_INFO_HEADER" >> $(sim)
-	cat arg-reshuffle >> $(sim)
-	echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim)
-	chmod +x $(sim)
+	echo "#!/usr/bin/env bash" > $@
+	echo "$$CAD_INFO_HEADER" >> $@
+	cat arg-reshuffle >> $@
+	echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
+	chmod +x $@
 
 $(sim_debug_run_tcl): $(sim_workdir)
-	echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl)
-	echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl)
-	echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl)
-	echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl)
-	echo "run" >> $(sim_debug_run_tcl)
-	echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl)
-	echo "exit" >> $(sim_debug_run_tcl)
-
+	echo "$$CAD_INFO_HEADER" > $@
+	echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $@
+	echo "set probe_packed_limit 64k" >> $@
+	echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $@
+	echo "run" >> $@
+	echo "database -close default_vcd_dump" >> $@
+	echo "exit" >> $@
 
 $(sim_debug): $(sim_workdir) $(sim_debug_run_tcl)
-	echo "#!/usr/bin/env bash" > $(sim_debug)
-	echo "$$CAD_INFO_HEADER" >> $(sim_debug)
-	cat arg-reshuffle >> $(sim_debug)
-	echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug)
-	echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug)
-	chmod +x $(sim_debug)
-
+	echo "#!/usr/bin/env bash" > $@
+	echo "$$CAD_INFO_HEADER" >> $@
+	cat arg-reshuffle >> $@
+	echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $@
+	echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
+	chmod +x $@
 
 #########################################################################################
 # create vcd rules
@@ -131,7 +128,7 @@ $(output_dir)/%.vcd: $(output_dir)/% $(sim_debug)
 #########################################################################################
 .PHONY: clean clean-sim clean-sim-debug
 clean:
-	rm -rf $(gen_dir) $(sim_prefix)-*
+	rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
 
 clean-sim:
 	rm -rf $(model_dir) $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log
diff --git a/sims/xcelium/xcelium.mk b/sims/xcelium/xcelium.mk
index 3d9ed5ab2a..62d1e9ae18 100644
--- a/sims/xcelium/xcelium.mk
+++ b/sims/xcelium/xcelium.mk
@@ -1,5 +1,5 @@
 
-WAVEFORM_FLAG=+vcdfile=$(sim_out_name).vcd
+get_waveform_flag=+vcdfile=$(1).vcd
 
 # If ntb_random_seed unspecified, xcelium uses 1 as constant seed.
 # Set ntb_random_seed_automatic to actually get a random seed
diff --git a/tools/barstools b/tools/barstools
index 30900965f0..fe81afec14 160000
--- a/tools/barstools
+++ b/tools/barstools
@@ -1 +1 @@
-Subproject commit 30900965f0cc2d5046e2160dd9c700805a8e0542
+Subproject commit fe81afec14634316606a9dd10628c220d53bd256
diff --git a/variables.mk b/variables.mk
index dc4669af12..2beec438df 100644
--- a/variables.mk
+++ b/variables.mk
@@ -8,7 +8,7 @@ HELP_COMPILATION_VARIABLES = \
 "   JAVA_TOOL_OPTIONS = if overridden, set underlying java tool options (default sets misc. sizes and tmp dir)" \
 "   SBT_OPTS          = set additional sbt command line options (these take the form -Dsbt.<option>=<setting>) " \
 "                       See https://www.scala-sbt.org/1.x/docs/Command-Line-Reference.html\#Command+Line+Options" \
-"   SBT_BIN           = if overridden, used to invoke sbt (default is to invoke sbt by sbt-launch.jar)" \
+"   SBT               = if overridden, used to invoke sbt (default is to invoke sbt by sbt-launch.jar)" \
 "   FIRRTL_LOGLEVEL   = if overridden, set firrtl log level (default is error)"
 
 HELP_PROJECT_VARIABLES = \
@@ -25,6 +25,7 @@ HELP_PROJECT_VARIABLES = \
 
 HELP_SIMULATION_VARIABLES = \
 "   BINARY                 = riscv elf binary that the simulator will run when using the run-binary* targets" \
+"   BINARIES               = list of riscv elf binary that the simulator will run when using the run-binaries* targets" \
 "   LOADMEM                = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \
 "   LOADARCH               = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \
 "   VERBOSE_FLAGS          = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \
@@ -157,6 +158,14 @@ ifeq ($(GENERATOR_PACKAGE),hwacha)
 	long_name=$(MODEL_PACKAGE).$(CONFIG)
 endif
 
+# classpaths
+CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache
+CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar
+TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar
+# if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix)
+CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH))
+TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH))
+
 # chisel generated outputs
 FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
 ANNO_FILE   ?= $(build_dir)/$(long_name).anno.json
@@ -217,32 +226,37 @@ sim_common_files       ?= $(build_dir)/sim_files.common.f
 #########################################################################################
 JAVA_HEAP_SIZE ?= 8G
 JAVA_TMP_DIR ?= $(base_dir)/.java_tmp
-export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Dsbt.supershell=false -Djava.io.tmpdir=$(JAVA_TMP_DIR)
+export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Djava.io.tmpdir=$(JAVA_TMP_DIR)
 
 #########################################################################################
 # default sbt launch command
 #########################################################################################
 SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES)
 
-SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json
-
-ifdef ENABLE_SBT_THIN_CLIENT
-SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP)
-# enabling speeds up sbt loading
-# use with sbt script or sbtn to bypass error code issues
-SBT_CLIENT_FLAG = --client
-endif
-
 # passes $(JAVA_TOOL_OPTIONS) from env to java
-export SBT_OPTS ?= -Dsbt.ivy.home=$(base_dir)/.ivy2 -Dsbt.global.base=$(base_dir)/.sbt -Dsbt.boot.directory=$(base_dir)/.sbt/boot/ -Dsbt.color=always
-SBT_BIN ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS)
-SBT = $(SBT_BIN) $(SBT_CLIENT_FLAG)
-SBT_NON_THIN = $(subst $(SBT_CLIENT_FLAG),,$(SBT))
+export SBT_OPTS ?= -Dsbt.ivy.home=$(base_dir)/.ivy2 -Dsbt.global.base=$(base_dir)/.sbt -Dsbt.boot.directory=$(base_dir)/.sbt/boot/ -Dsbt.color=always -Dsbt.supershell=false -Dsbt.server.forcestart=true
+SBT ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS)
+
+# (1) - classpath of the fat jar
+# (2) - main class
+# (3) - main class arguments
+define run_jar_scala_main
+	cd $(base_dir) && java -cp $(1) $(2) $(3)
+endef
 
+# (1) - sbt project
+# (2) - main class
+# (3) - main class arguments
 define run_scala_main
 	cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)"
 endef
 
+# (1) - sbt project to assemble
+# (2) - classpath file(s) to create
+define run_sbt_assembly
+	cd $(base_dir) && $(SBT) ";project $(1); set assembly / assemblyOutputPath := file(\"$(2)\"); assembly"
+endef
+
 FIRRTL_LOGLEVEL ?= error
 
 #########################################################################################
@@ -256,29 +270,21 @@ output_dir=$(sim_dir)/output/$(long_name)
 PERMISSIVE_ON=+permissive
 PERMISSIVE_OFF=+permissive-off
 BINARY ?=
+BINARIES ?=
 override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles)
 VERBOSE_FLAGS ?= +verbose
-OUT_NAME ?= $(subst $() $(),_,$(notdir $(basename $(BINARY))))
+# get_out_name is a function, 1st argument is the binary
+get_out_name = $(subst $() $(),_,$(notdir $(basename $(1))))
 LOADMEM ?=
 LOADARCH ?=
 
 ifneq ($(LOADARCH),)
-override BINARY = $(LOADARCH)/mem.elf
-override OUT_NAME = $(shell basename $(LOADARCH))
+override BINARY = $(addsuffix /mem.elf,$(LOADARCH))
+override BINARIES = $(addsuffix /mem.elf,$(LOADARCH))
+override get_out_name = $(shell basename $(dir $(1)))
 override LOADMEM = 1
-override SIM_FLAGS += +loadarch=$(LOADARCH)/loadarch
 endif
 
-ifeq ($(LOADMEM),1)
-# If LOADMEM=1, assume BINARY is the loadmem elf
-override SIM_FLAGS += +loadmem=$(BINARY)
-else ifneq ($(LOADMEM),)
-# Otherwise, assume the variable points to an elf file
-override SIM_FLAGS += +loadmem=$(LOADMEM)
-endif
-
-sim_out_name = $(output_dir)/$(OUT_NAME)
-
 #########################################################################################
 # build output directory for compilation
 #########################################################################################
diff --git a/vlsi/Makefile b/vlsi/Makefile
index 8ca74d314c..b3901fe65d 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -171,4 +171,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
 #########################################################################################
 .PHONY: clean
 clean:
-	rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)
+	rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(CLASSPATH_CACHE) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)
diff --git a/vlsi/power.mk b/vlsi/power.mk
index 5e265a3589..ff1c1729ef 100644
--- a/vlsi/power.mk
+++ b/vlsi/power.mk
@@ -6,7 +6,7 @@ POWER_PAR_HIER_CONF = $(OBJ_DIR)/power-par-$(VLSI_TOP)-inputs.yml
 
 .PHONY: $(POWER_CONF) $(POWER_RTL_CONF) $(POWER_SYN_CONF) $(POWER_PAR_CONF) $(POWER_PAR_HIER_CONF)
 
-$(POWER_CONF): $(VLSI_RTL)
+$(POWER_CONF): $(VLSI_RTL) check-binary
 	mkdir -p $(dir $@)
 	echo "power.inputs:" > $@
 	echo "  top_module: $(VLSI_TOP)" >> $@
@@ -15,9 +15,9 @@ $(POWER_CONF): $(VLSI_RTL)
 ifneq ($(BINARY), )
 	echo "  waveforms: [" >> $@
 ifndef USE_VPD
-	echo "    '$(sim_out_name).fsdb'" >> $@
+	echo "    '$(call get_sim_out_name,$(BINARY)).fsdb'" >> $@
 else
-	echo "    '$(sim_out_name).vpd'" >> $@
+	echo "    '$(call get_sim_out_name,$(BINARY)).vpd'" >> $@
 endif
 	echo "  ]" >> $@
 endif
diff --git a/vlsi/sim.mk b/vlsi/sim.mk
index 291c93adf6..b721c9fb70 100644
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -4,7 +4,7 @@ SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
 
 .PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF)
 
-$(SIM_CONF): $(sim_common_files)
+$(SIM_CONF): $(sim_common_files) check-binary
 	mkdir -p $(dir $@)
 	echo "sim.inputs:" > $@
 	echo "  top_module: $(VLSI_TOP)" >> $@
@@ -47,14 +47,14 @@ ifneq ($(BINARY), )
 endif
 	echo "  tb_dut: 'TestDriver.testHarness.$(VLSI_MODEL_DUT_NAME)'" >> $@
 
-$(SIM_DEBUG_CONF): $(sim_common_files)
+$(SIM_DEBUG_CONF): $(sim_common_files) check-binary
 	mkdir -p $(dir $@)
 	mkdir -p $(output_dir)
 	echo "sim.inputs:" > $@
 	echo "  defines: ['DEBUG']" >> $@
 	echo "  defines_meta: 'append'" >> $@
 	echo "  execution_flags:" >> $@
-	for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \
+	for x in $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$(BINARY))); do \
 	  echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  execution_flags_meta: 'append'" >> $@
@@ -65,9 +65,9 @@ ifndef USE_VPD
 	echo "  options:" >> $@
 	echo '    - "-kdb"' >> $@
 	echo "  options_meta: 'append'" >> $@
-	echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@
+	echo "sim.outputs.waveforms: ['$(call get_sim_out_name,$(BINARY)).fsdb']" >> $@
 else
-	echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
+	echo "sim.outputs.waveforms: ['$(call get_sim_out_name,$(BINARY)).vpd']" >> $@
 endif
 
 $(SIM_TIMING_CONF): $(sim_common_files)