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Clean multiclock support #662
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I think we should make SimSerial behave like it does on most test-chips where it provides it's clock off chip to be caught by the testharness and used to synchronize the "serial" data. |
I agree we should make Serial more "correct". If that leaves SimDRAM as the only widget for which punching out a clock is necessary, then I think we should just special-case it. |
Don't forget multi-clock example + documentation |
When this is complete, all default examples will be multi-clock |
Released in 1.4.0 |
This issue tracks work towards clean support of multiclock designs. The vision is to use rocketchip's new diplomatic clock graph as an API to determine how to generate and connect clocks for a multiclock design.
Change all default configs to have half-freq uncore. We decided to leave default configs unchanged, to avoid degrading simulation performance too much.Impact: rtl
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