From e078fcba49eea6a5bfa61c3587130a07fbce1a05 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 4 Dec 2023 01:54:59 -0800 Subject: [PATCH 1/2] REFACTOR: rename arty35t explicitly --- fpga/Makefile | 6 +++--- fpga/src/main/scala/arty/HarnessBinders.scala | 8 ++++---- fpga/src/main/scala/arty/TestHarness.scala | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index 3d3caf1cb1..cfe760f4a0 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -72,11 +72,11 @@ ifeq ($(SUB_PROJECT),nexysvideo) FPGA_BRAND ?= xilinx endif -ifeq ($(SUB_PROJECT),arty) +ifeq ($(SUB_PROJECT),arty35t) # TODO: Fix with Arty SBT_PROJECT ?= fpga_platforms - MODEL ?= ArtyFPGATestHarness - VLOG_MODEL ?= ArtyFPGATestHarness + MODEL ?= Arty35THarness + VLOG_MODEL ?= Arty35THarness MODEL_PACKAGE ?= chipyard.fpga.arty CONFIG ?= TinyRocketArtyConfig CONFIG_PACKAGE ?= chipyard.fpga.arty diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 5cef5f8053..d2ce54892d 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder} import chipyard.iobinders._ class WithArtyDebugResetHarnessBinder extends HarnessBinder({ - case (th: ArtyFPGATestHarness, port: DebugResetPort) => { + case (th: Arty35THarness, port: DebugResetPort) => { th.dut_ndreset := port.io // Debug module reset } }) class WithArtyJTAGResetHarnessBinder extends HarnessBinder({ - case (th: ArtyFPGATestHarness, port: JTAGResetPort) => { + case (th: Arty35THarness, port: JTAGResetPort) => { port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset } }) class WithArtyJTAGHarnessBinder extends HarnessBinder({ - case (th: ArtyFPGATestHarness, port: JTAGPort) => { + case (th: Arty35THarness, port: JTAGPort) => { val jtag_wire = Wire(new JTAGIO) jtag_wire.TDO.data := port.io.TDO jtag_wire.TDO.driven := true.B @@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({ }) class WithArtyUARTHarnessBinder extends HarnessBinder({ - case (th: ArtyFPGATestHarness, port: UARTPort) => { + case (th: Arty35THarness, port: UARTPort) => { withClockAndReset(th.clock_32MHz, th.ck_rst) { IOBUF(th.uart_rxd_out, port.io.txd) port.io.rxd := IOBUF(th.uart_txd_in) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 0a81740aff..cdb1d4e490 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -10,7 +10,7 @@ import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} import chipyard.harness.{HasHarnessInstantiators} -class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators { +class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators { // Convert harness resets from Bool to Reset type. val hReset = Wire(Reset()) hReset := ~ck_rst From 00c4992842e35e77bc327d152025298a4d24c6a3 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 4 Dec 2023 02:43:49 -0800 Subject: [PATCH 2/2] FIX: update github CI --- .github/scripts/defaults.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 5d98ad2bea..d4eb7b56f0 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -34,7 +34,7 @@ grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipya grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boom" grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar" -grouping["group-fpga"]="arty arty100t nexysvideo vc707 vcu118" +grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118" # key value store to get the build strings declare -A mapping @@ -79,7 +79,7 @@ mapping["rocketchip-tlsimple"]="SUB_PROJECT=rocketchip CONFIG=TLSimpleUnitTestCo mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig" mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig" -mapping["arty"]="SUB_PROJECT=arty verilog" +mapping["arty35t"]="SUB_PROJECT=arty35t verilog" mapping["arty100t"]="SUB_PROJECT=arty100t verilog" mapping["nexysvideo"]="SUB_PROJECT=nexysvideo verilog" mapping["vc707"]="SUB_PROJECT=vc707 verilog"