From 8c7edaf128f780359b648b53fb831f396d489d9b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 19 Apr 2024 16:00:30 -0700 Subject: [PATCH] Auto-set DTSTimebase to be same as PBUS frequency --- fpga/src/main/scala/arty/Configs.scala | 2 -- .../main/scala/config/fragments/ClockingFragments.scala | 9 ++++++--- .../main/scala/config/fragments/SubsystemFragments.scala | 4 ---- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 7f10b174cf..ccb26c7def 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -5,7 +5,6 @@ import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ @@ -25,7 +24,6 @@ class WithArtyTweaks extends Config( new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ - new chipyard.config.WithDTSTimebase(32000) ++ new chipyard.config.WithSystemBusFrequency(32) ++ new chipyard.config.WithFrontBusFrequency(32) ++ new chipyard.config.WithControlBusFrequency(32) ++ diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 8cf6ae67a7..83a42146ae 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -89,9 +89,12 @@ class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site, * Mixins to set the dtsFrequency field of BusParams -- these will percolate its way * up the diplomatic graph to the clock sources. */ -class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) -}) +class WithPeripheryBusFrequency(freqMHz: Double) extends Config( + new freechips.rocketchip.subsystem.WithTimebase((freqMHz * 1e3).toLong) ++ // Match DTS timebase to PBUS (i.e. RTC) frequency. Makes RTC 'tick' at the PBUS rate. + new Config((site, here, up) => { + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) + }) +) class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index b4971cba3d..8e16b26c66 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -18,10 +18,6 @@ class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => { case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8) }) -class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => { - case DTSTimebase => freqMHz -}) - // Adds buffers on the interior of the inclusive LLC, to improve PD class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => { case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)