From 1cff5b011e1a93004599da2a136cdae2e75e0d3c Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 13 May 2021 08:01:34 -0700 Subject: [PATCH 01/81] sky130 plugin files --- src/hammer-vlsi/technology/sky130/__init__.py | 231 ++++++++++++++++++ 1 file changed, 231 insertions(+) create mode 100644 src/hammer-vlsi/technology/sky130/__init__.py diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py new file mode 100644 index 000000000..087302fb7 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -0,0 +1,231 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Skywater plugin for Hammer. +# +# See LICENSE for licence details. + +import sys +import re +import os +#import tempfile +import shutil +#from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any + +from hammer_tech import HammerTechnology +from hammer_vlsi import HammerTool, HammerPlaceAndRouteTool, TCLTool, HammerToolHookAction + +class SkywaterTech(HammerTechnology): + """ + Override the HammerTechnology used in `hammer_tech.py` + This class is loaded by function `load_from_json`, and will pass the `try` in `importlib`. + """ + def post_install_script(self) -> None: + try: + import gdspy # type: ignore + except ImportError: + self.logger.error("Couldn't import gdspy Python package, needed to merge Skywater gds.") + shutil.rmtree(self.cache_dir) + sys.exit() + # make cache directories for all necessary lib files + #dirs = 'cdl gds lef lib verilog/models'.split() + dir = 'gds'#for dir in dirs: + os.makedirs(os.path.join(self.cache_dir,dir), exist_ok=True) + # make models dirs in parse_models function + + # useful paths/values + base_dir = self.get_setting("technology.sky130.skywater_pdk") + libraries = os.listdir(base_dir+'/libraries/') + library = 'sky130_fd_sc_hd' + libs_path = base_dir+'/libraries/' + lib_path = libs_path+library+'/latest/' + cells = os.listdir(lib_path+'/cells') + + self.combine_gds(lib_path,library,cells) + #self.combine_lef(lib_path,library,cells) + #self.combine_verilog(lib_path,library,cells) + #self.parse_models(lib_path,library) + #self.combine_cdl(lib_path,library,cells) + #self.lib_setup(lib_path,library) + + def lib_setup(self,lib_path,library) -> None: + # set up file + corners = os.listdir(os.path.join(lib_path,'timing')) + # find ccsnoise corners + ccsnoise_corners = [] + for corner in corners: + if corner.endswith('_ccsnoise.lib'): + corner = corner.replace('_ccsnoise','') + ccsnoise_corners.append(corner) + for corner in corners: + if corner.endswith('_ccsnoise.lib'): + continue + # remove ccsnoise info + if corner in ccsnoise_corners: + f = open(os.path.join(self.cache_dir,'lib',corner), 'w') + lib_file = open(os.path.join(lib_path,'timing',corner),'r') + count = 0; # count brackets :( + ccsn = False + for line in lib_file: + if ( ('ccsn_first_stage' in line) or ('ccsn_last_stage' in line) ): + ccsn = True + if (not ccsn): + f.write(line) + else: + count = count + line.count('{') + count = count - line.count('}') + if count == 0: + ccsn = False + f.close() + # copy rest of lib files to tech cache + elif corner.endswith('.lib'): + shutil.copyfile(os.path.join(lib_path,'timing',corner),os.path.join(self.cache_dir,'lib',corner)) + + def combine_gds(self,lib_path,library,cells) -> None: + import gdspy + # create new gds lib + gds_lib = gdspy.GdsLibrary() + # iterate over all cells + for cell in cells: + cell_path = os.path.join(lib_path,'cells',cell) + cell_files = os.listdir(cell_path) + # iterate over all gds files for each cell + for cell_file in cell_files: + if cell_file.endswith('.gds'): + cell_gds_path = os.path.join(cell_path,cell_file) + # import gds file into gds library + cell_gds = gds_lib.read_gds(cell_gds_path) + gds_lib_path = os.path.join(self.cache_dir,'gds',library+'.gds') + gds_lib.write_gds(gds_lib_path) + + def combine_lef(self,lib_path,library,cells) -> None: + # set up file + f = open(os.path.join(self.cache_dir,"lef",library+".lef"), "w") + f.write('VERSION 5.6 ;\nNAMESCASESENSITIVE ON ;\nBUSBITCHARS "[]" ;\nDIVIDERCHAR "/" ;\n\n') + # iterate over cells + for cell in cells: + cell_path = os.path.join(lib_path,'cells',cell) + cell_files = os.listdir(cell_path) + for cell_file in cell_files: + if cell_file.endswith('.lef') and not cell_file.endswith('magic.lef'): + cell_file = open(os.path.join(cell_path,cell_file),"r") + writing=False + for line in cell_file: + if line.startswith("END LIBRARY"): + f.write('\n\n') + break + if line.startswith("MACRO"): + writing=True + if writing: + f.write(line) + f.close() + + def combine_verilog2(self,lib_path,library,cells) -> None: + # set up file + f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") + #f.write('`define UNIT_DELAY \n') # WHERE TF IS THIS DEFINED IN PDK?!?!?! + # include udp models + models = os.listdir(os.path.join(lib_path,'models')) + for model in models: + model_path = os.path.join(self.cache_dir,'verilog','models',library+'__'+model+'.v') + f.write('`include "'+model_path+'"\n') + # iterate over cells + for cell in cells: + cell_path = os.path.join(lib_path,'cells',cell) + cell_files = os.listdir(cell_path) + for cell_file in cell_files: + if cell_file.endswith('.behavioral.v') or \ + ( cell_file.endswith('.v') and cell_file.startswith(library+'__'+cell+'_') ): + cell_file = open(os.path.join(cell_path,cell_file),"r") + f.write('\n\n') # separate modules + for line in cell_file: + # edit these lines + if line.startswith('`default_nettype none\n'): + line = line.replace('none','wire') + # skip these lines + if '*' in line: continue # comments + if line.startswith('`include'): continue # unnecessary imports + if ('wire 1' in line): continue # dunno why this is in some verilog files + + f.write(line) + f.close() + + def combine_verilog(self,lib_path,library,cells) -> None: + # set up file + f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") + #f.write('`define UNIT_DELAY \n') # WHERE TF IS THIS DEFINED IN PDK?!?!?! + # include udp models + models = os.listdir(os.path.join(lib_path,'models')) + for model in models: + model_path = os.path.join(self.cache_dir,'verilog','models',library+'__'+model+'.blackbox.v') + f.write('`include "'+model_path+'"\n') + # iterate over cells + for cell in cells: + cell_path = os.path.join(lib_path,'cells',cell) + cell_files = os.listdir(cell_path) + for cell_file in cell_files: + if cell_file.endswith('.behavioral.v') or \ + ( cell_file.endswith('.v') and cell_file.startswith(library+'__'+cell+'_') ): + cell_file = open(os.path.join(cell_path,cell_file),"r") + f.write('\n\n') # separate modules + for line in cell_file: + # edit these lines + if line.startswith('`default_nettype none\n'): + line = line.replace('none','wire') + # skip these lines + if '*' in line: continue # comments + if line.startswith('`include'): continue # unnecessary imports + if ('wire 1' in line): continue # dunno why this is in some verilog files + + f.write(line) + f.close() + def parse_models(self,lib_path,library) -> None: + model_path = os.path.join(lib_path,'models') + models = os.listdir(model_path) + for model in models: + cache_model_path = os.path.join(self.cache_dir,'verilog','models') + model_filename = library+'__'+model+'.blackbox.v' + f = open(os.path.join(cache_model_path,model_filename),'w') + model_file = open(os.path.join(model_path,model,model_filename)) + for line in model_file: + if line.startswith("`default_nettype none"): + line = line.replace('none','wire') + f.write(line) + f.close() + def parse_models2(self,lib_path,library) -> None: + model_path = os.path.join(lib_path,'models') + models = os.listdir(model_path) + for model in models: + cache_model_path = os.path.join(self.cache_dir,'verilog','models') + model_filename = library+'__'+model+'.v' + f = open(os.path.join(cache_model_path,model_filename),'w') + model_file = open(os.path.join(model_path,model,model_filename)) + for line in model_file: + if line.startswith("`default_nettype none"): + line = line.replace('none','wire') + f.write(line) + f.close() + + def combine_cdl(self,lib_path,library,cells) -> None: + # set up file + f = open(os.path.join(self.cache_dir,"cdl",library+".cdl"), "w") + # iterate over cells + for cell in cells: + cell_path = os.path.join(lib_path,'cells',cell) + cell_files = os.listdir(cell_path) + for cell_file in cell_files: + if cell_file.endswith('.cdl'): + cell_file = open(os.path.join(cell_path,cell_file),"r") + writing=False + for line in cell_file: + if line.startswith(".SUBCKT"): + writing=True + if writing: + f.write(line) + if line.startswith(".ENDS"): + f.write('\n\n') + break + f.close() + +tech = SkywaterTech() + From f8f337afdc48547f41fb1e6608748a7b775f486d Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 13 May 2021 08:04:16 -0700 Subject: [PATCH 02/81] sky130 plugin files --- .../technology/sky130/defaults.yml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 src/hammer-vlsi/technology/sky130/defaults.yml diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml new file mode 100644 index 000000000..55def0f5c --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -0,0 +1,59 @@ +# Settings for the skywater technology to be overriden by the project. +technology.sky130: + skywater_pdk: "PATH_TO_SKYWATER_PDK" + open_pdks: "PATH_TO_OPEN_PDKS" + skywater_nda: "PATH_TO_NDA_FILES" + sram_lib: "" + +# Set some defaults for this technology. +vlsi: + # Technology dimension + core.node: 130 + inputs: + # Supply voltages. + supplies: + power: [{name: "VDD", pin: "VPWR"}] + ground: [{name: "VSS", pin: "VGND"}] + VDD: "1.8 V" + GND: "0 V" + + # mmmc corners config + mmmc_corners: [ + { + "name": "sky130_fd_sc_hd__ss_100C_1v60", + "type": "setup", + "voltage": "1.60 V", + "temp": "100 C" + }, + { + "name": "sky130_fd_sc_hd__ff_n40C_1v95", + "type": "hold", + "voltage": "1.95 V", + "temp": "-40 C" + } + ] + technology: + # Set standard cell LEF placement site + placement_site: "unithd" + + # Set the layer that blocks vias under bumps + # nk - not sure if this is right?? + bump_block_cut_layer: "via4" + + # Set the interval and offset for tap cells + # nk - not sure if this is right?? + tap_cell_interval: "27" + tap_cell_offset: "5" + +technology.core: + # This key should exist in the stackups list in the tech json + stackup: "sky130_fd_sc_hd" + # This should specify the TOPMOST metal layer the standard cells use for power rails + # Note that this is not usually stackup specific; it is based on the std cell libraries themselves + std_cell_rail_layer: "met1" + # This is used to provide a reference master for generating standard cells + tap_cell_rail_reference: "{sky130_fd_sc_hd__tap*}" + +par.inputs: + gds_merge: true + From d059521600e254774324749d06203e0e4c62367a Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 13 May 2021 08:51:58 -0700 Subject: [PATCH 03/81] adding tech json whoops --- .../technology/sky130/sky130.tech.json | 437 ++++++++++++++++++ 1 file changed, 437 insertions(+) create mode 100644 src/hammer-vlsi/technology/sky130/sky130.tech.json diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json new file mode 100644 index 000000000..2e345c061 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -0,0 +1,437 @@ +{ + "name": "Skywater 130nm Library", + "grid_unit": "0.001", + "time_unit": "1 ps", + "installs": [ + { + "path": "$SKYWATER_PDK", + "base var": "technology.sky130.skywater_pdk" + }, + { + "path": "$OPEN_PDKS", + "base var": "technology.sky130.open_pdks" + }, + { + "path": "$SKYWATER_NDA", + "base var": "technology.sky130.skywater_nda" + }, + { + "path": "tech-sky130-cache", + "base var": "" + } + ], + "gds map file": "$SKYWATER_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "drc decks": [ + { + "tool name": "calibre", + "deck name": "all_drc", + "path": "$SKYWATER_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules", + "newpath": "tech-sky130-cache/drc/s8_drcRules" + } + ], + "additional_drc_text": "", + + "lvs decks": [ + { + "tool name": "calibre", + "deck name": "all_lvs", + "path": "$SKYWATER_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8" + } + ], + "additional_lvs_text": "", + + "libraries": [ + { + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef", + "provides": [ + { + "lib_type": "technology" + } + ] + }, + + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.65 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.95 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.56 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.65 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.76 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.95 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.40 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.60 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.28 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.35 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.40 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.44 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.60 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.76 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "typical", + "pmos": "typical", + "temperature": "025 C" + }, + "supplies": { + "VDD": "1.80 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "typical", + "pmos": "typical", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.80 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + } + ], + "stackups": [ + { + "name": "sky130_fd_sc_hd", + "metals": [ + {"name": "li1", "index": 1, "direction": "vertical", "min_width": 0.17, "max_width": 2147483.647, "pitch": 0.34, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.17}]}, + {"name": "met1", "index": 2, "direction": "horizontal", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.17, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, + {"name": "met2", "index": 3, "direction": "vertical", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, + {"name": "met3", "index": 4, "direction": "horizontal", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.34, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, + {"name": "met4", "index": 5, "direction": "vertical", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.46, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, + {"name": "met5", "index": 6, "direction": "horizontal", "min_width": 1.6, "max_width": 2147483.647, "pitch": 3.2, "offset": 1.7, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 1.6}]} + ] + } + ], + "sites": [ + {"name": "unithd", "x": 0.46, "y": 2.72}, + {"name": "unithddbl", "x": 0.46, "y": 5.44} + ], + "physical only cells list": [ + "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", + "sky130_fd_sc_hd__tapvgnd_1", + "sky130_fd_sc_hd__tapvpwrvgnd_1", + "sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8" + ], + "special cells": [ + {"cell_type": "tapcell", "name": ["sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2"]}, + {"cell_type": "stdfiller", "name": ["sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8"]} + ] +} From 5b6199268321c3818d4e902c645de5be3dadd7f8 Mon Sep 17 00:00:00 2001 From: harrisonliew Date: Thu, 13 May 2021 11:40:21 -0700 Subject: [PATCH 04/81] preliminary untested sram compiler, also changed some skywater names to sky130 --- src/hammer-vlsi/technology/sky130/__init__.py | 66 ++-- .../technology/sky130/defaults.yml | 9 +- .../technology/sky130/sky130.tech.json | 14 +- .../technology/sky130/sram-cache-gen.py | 115 +++++++ .../technology/sky130/sram-cache.json | 301 ++++++++++++++++++ .../sky130/sram_compiler/__init__.py | 97 ++++++ src/hammer-vlsi/technology/sky130/srams.txt | 10 + src/test/mypy.sh | 2 + 8 files changed, 570 insertions(+), 44 deletions(-) create mode 100755 src/hammer-vlsi/technology/sky130/sram-cache-gen.py create mode 100644 src/hammer-vlsi/technology/sky130/sram-cache.json create mode 100644 src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py create mode 100644 src/hammer-vlsi/technology/sky130/srams.txt diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 087302fb7..c017554d9 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # -# Skywater plugin for Hammer. +# SKY130 plugin for Hammer. # # See LICENSE for licence details. @@ -15,7 +15,7 @@ from hammer_tech import HammerTechnology from hammer_vlsi import HammerTool, HammerPlaceAndRouteTool, TCLTool, HammerToolHookAction -class SkywaterTech(HammerTechnology): +class SKY130Tech(HammerTechnology): """ Override the HammerTechnology used in `hammer_tech.py` This class is loaded by function `load_from_json`, and will pass the `try` in `importlib`. @@ -24,7 +24,7 @@ def post_install_script(self) -> None: try: import gdspy # type: ignore except ImportError: - self.logger.error("Couldn't import gdspy Python package, needed to merge Skywater gds.") + self.logger.error("Couldn't import gdspy Python package, needed to merge SKY130 gds.") shutil.rmtree(self.cache_dir) sys.exit() # make cache directories for all necessary lib files @@ -32,22 +32,22 @@ def post_install_script(self) -> None: dir = 'gds'#for dir in dirs: os.makedirs(os.path.join(self.cache_dir,dir), exist_ok=True) # make models dirs in parse_models function - + # useful paths/values - base_dir = self.get_setting("technology.sky130.skywater_pdk") + base_dir = self.get_setting("technology.sky130.sky130_pdk") libraries = os.listdir(base_dir+'/libraries/') library = 'sky130_fd_sc_hd' libs_path = base_dir+'/libraries/' lib_path = libs_path+library+'/latest/' cells = os.listdir(lib_path+'/cells') - + self.combine_gds(lib_path,library,cells) #self.combine_lef(lib_path,library,cells) #self.combine_verilog(lib_path,library,cells) #self.parse_models(lib_path,library) #self.combine_cdl(lib_path,library,cells) #self.lib_setup(lib_path,library) - + def lib_setup(self,lib_path,library) -> None: # set up file corners = os.listdir(os.path.join(lib_path,'timing')) @@ -80,7 +80,7 @@ def lib_setup(self,lib_path,library) -> None: # copy rest of lib files to tech cache elif corner.endswith('.lib'): shutil.copyfile(os.path.join(lib_path,'timing',corner),os.path.join(self.cache_dir,'lib',corner)) - + def combine_gds(self,lib_path,library,cells) -> None: import gdspy # create new gds lib @@ -90,14 +90,14 @@ def combine_gds(self,lib_path,library,cells) -> None: cell_path = os.path.join(lib_path,'cells',cell) cell_files = os.listdir(cell_path) # iterate over all gds files for each cell - for cell_file in cell_files: - if cell_file.endswith('.gds'): - cell_gds_path = os.path.join(cell_path,cell_file) + for cell_file_path in cell_files: + if cell_file_path.endswith('.gds'): + cell_gds_path = os.path.join(cell_path,cell_file_path) # import gds file into gds library cell_gds = gds_lib.read_gds(cell_gds_path) gds_lib_path = os.path.join(self.cache_dir,'gds',library+'.gds') gds_lib.write_gds(gds_lib_path) - + def combine_lef(self,lib_path,library,cells) -> None: # set up file f = open(os.path.join(self.cache_dir,"lef",library+".lef"), "w") @@ -106,12 +106,12 @@ def combine_lef(self,lib_path,library,cells) -> None: for cell in cells: cell_path = os.path.join(lib_path,'cells',cell) cell_files = os.listdir(cell_path) - for cell_file in cell_files: - if cell_file.endswith('.lef') and not cell_file.endswith('magic.lef'): - cell_file = open(os.path.join(cell_path,cell_file),"r") + for cell_file_path in cell_files: + if cell_file_path.endswith('.lef') and not cell_file_path.endswith('magic.lef'): + cell_file = open(os.path.join(cell_path,cell_file_path),"r") writing=False for line in cell_file: - if line.startswith("END LIBRARY"): + if line.startswith("END LIBRARY"): f.write('\n\n') break if line.startswith("MACRO"): @@ -119,7 +119,7 @@ def combine_lef(self,lib_path,library,cells) -> None: if writing: f.write(line) f.close() - + def combine_verilog2(self,lib_path,library,cells) -> None: # set up file f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") @@ -133,10 +133,10 @@ def combine_verilog2(self,lib_path,library,cells) -> None: for cell in cells: cell_path = os.path.join(lib_path,'cells',cell) cell_files = os.listdir(cell_path) - for cell_file in cell_files: - if cell_file.endswith('.behavioral.v') or \ - ( cell_file.endswith('.v') and cell_file.startswith(library+'__'+cell+'_') ): - cell_file = open(os.path.join(cell_path,cell_file),"r") + for cell_file_path in cell_files: + if cell_file_path.endswith('.behavioral.v') or \ + ( cell_file_path.endswith('.v') and cell_file_path.startswith(library+'__'+cell+'_') ): + cell_file = open(os.path.join(cell_path,cell_file_path),"r") f.write('\n\n') # separate modules for line in cell_file: # edit these lines @@ -149,7 +149,7 @@ def combine_verilog2(self,lib_path,library,cells) -> None: f.write(line) f.close() - + def combine_verilog(self,lib_path,library,cells) -> None: # set up file f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") @@ -163,10 +163,10 @@ def combine_verilog(self,lib_path,library,cells) -> None: for cell in cells: cell_path = os.path.join(lib_path,'cells',cell) cell_files = os.listdir(cell_path) - for cell_file in cell_files: - if cell_file.endswith('.behavioral.v') or \ - ( cell_file.endswith('.v') and cell_file.startswith(library+'__'+cell+'_') ): - cell_file = open(os.path.join(cell_path,cell_file),"r") + for cell_file_path in cell_files: + if cell_file_path.endswith('.behavioral.v') or \ + ( cell_file_path.endswith('.v') and cell_file_path.startswith(library+'__'+cell+'_') ): + cell_file = open(os.path.join(cell_path,cell_file_path),"r") f.write('\n\n') # separate modules for line in cell_file: # edit these lines @@ -205,7 +205,7 @@ def parse_models2(self,lib_path,library) -> None: line = line.replace('none','wire') f.write(line) f.close() - + def combine_cdl(self,lib_path,library,cells) -> None: # set up file f = open(os.path.join(self.cache_dir,"cdl",library+".cdl"), "w") @@ -213,19 +213,19 @@ def combine_cdl(self,lib_path,library,cells) -> None: for cell in cells: cell_path = os.path.join(lib_path,'cells',cell) cell_files = os.listdir(cell_path) - for cell_file in cell_files: - if cell_file.endswith('.cdl'): - cell_file = open(os.path.join(cell_path,cell_file),"r") + for cell_file_path in cell_files: + if cell_file_path.endswith('.cdl'): + cell_file = open(os.path.join(cell_path,cell_file_path),"r") writing=False for line in cell_file: if line.startswith(".SUBCKT"): writing=True if writing: f.write(line) - if line.startswith(".ENDS"): + if line.startswith(".ENDS"): f.write('\n\n') break f.close() - -tech = SkywaterTech() + +tech = SKY130Tech() diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index 55def0f5c..724120b0e 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -1,9 +1,10 @@ -# Settings for the skywater technology to be overriden by the project. +# Settings for the sky130 technology to be overriden by the project. technology.sky130: - skywater_pdk: "PATH_TO_SKYWATER_PDK" + sky130_pdk: "PATH_TO_SKY130_PDK" open_pdks: "PATH_TO_OPEN_PDKS" - skywater_nda: "PATH_TO_NDA_FILES" - sram_lib: "" + sky130_nda: "PATH_TO_NDA_FILES" + dffram_lib: "PATH_TO_DFFRAM/Compiler/build" + openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" # Set some defaults for this technology. vlsi: diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 2e345c061..97ce77222 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -4,28 +4,28 @@ "time_unit": "1 ps", "installs": [ { - "path": "$SKYWATER_PDK", - "base var": "technology.sky130.skywater_pdk" + "path": "$SKY130_PDK", + "base var": "technology.sky130.sky130_pdk" }, { "path": "$OPEN_PDKS", "base var": "technology.sky130.open_pdks" }, { - "path": "$SKYWATER_NDA", - "base var": "technology.sky130.skywater_nda" + "path": "$SKY130_NDA", + "base var": "technology.sky130.sky130_nda" }, { "path": "tech-sky130-cache", "base var": "" } ], - "gds map file": "$SKYWATER_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "gds map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { "tool name": "calibre", "deck name": "all_drc", - "path": "$SKYWATER_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules", + "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules", "newpath": "tech-sky130-cache/drc/s8_drcRules" } ], @@ -35,7 +35,7 @@ { "tool name": "calibre", "deck name": "all_lvs", - "path": "$SKYWATER_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8" + "path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8" } ], "additional_lvs_text": "", diff --git a/src/hammer-vlsi/technology/sky130/sram-cache-gen.py b/src/hammer-vlsi/technology/sky130/sram-cache-gen.py new file mode 100755 index 000000000..bc2fe903b --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sram-cache-gen.py @@ -0,0 +1,115 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Script to generate the ASAP7 dummy SRAM cache. +# +# See LICENSE for licence details. + +import sys +import re + +from typing import List + +def main(args: List[str]) -> int: + if len(args) != 3: + print("Usage: ./sram-cache-gen.py list-of-srams-1-per-line.txt output-file.json") + print("E.g.: ./sram-cache-gen.py srams.txt sram-cache.json") + return 1 + + list_of_srams = [] # type: List[str] + with open(sys.argv[1]) as f: + for line in f: + list_of_srams.append(line) + + print(str(len(list_of_srams)) + " SRAMs to cache") + + json = [] # type: List[str] + + for sram_name in list_of_srams: + # DFFRAM-generated 1-port rams + if sram_name.startswith("RAM"): + match = re.match(r"RAM(\d+)x(\d+)", sram_name) + if match: + json.append("""{{ + "type" : "sram", + "name" : "{n}", + "depth" : {d}, + "width" : {w}, + "family" : "1rw", + "mask" : "true", + "ports" : [ {{ + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + }} ], + "extra ports" : [] +}}""".format(n=sram_name.strip(), d=match.group(1), w=match.group(2))) + else: + print("Unsupported memory: {n}".format(n=sram_name), file=sys.stderr) + return 1 + # OpenRAM-generated 2-port rams + elif sram_name.startswith("sky130_sram"): + match = re.match(r"sky130_sram_(\d+)kbyte_1rw1r_(\d+)x(\d+)_(\d+)", sram_name) + if match: + json.append(""" +{{ + "type" : "sram", + "name" : "{n}", + "depth" : {d}, + "width" : {w}, + "family" : "1rw1r", + "mask" : "true", + "ports": [ {{ + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }}, {{ + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + }} ], + "extra ports" : [] +}}""".format(n=sram_name.strip(), w=match.group(2), d=match.group(3), m=match.group(4))) + else: + print("Unsupported memory: {n}".format(n=sram_name), file=sys.stderr) + return 1 + else: + print("Unsupported memory: {n}".format(n=sram_name), file=sys.stderr) + return 1 + + json_str = "[\n" + ",\n".join(json) + "]\n" + + with open(sys.argv[2], "w") as f: + f.write(json_str) + + return 0 + +if __name__ == '__main__': + sys.exit(main(sys.argv)) diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json new file mode 100644 index 000000000..b703238ec --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -0,0 +1,301 @@ +[ +{ + "type" : "sram", + "name" : "RAM8x32", + "depth" : 8, + "width" : 32, + "family" : "1rw", + "mask" : "true", + "ports" : [ { + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + } ], + "extra ports" : [] +}, +{ + "type" : "sram", + "name" : "RAM32x32", + "depth" : 32, + "width" : 32, + "family" : "1rw", + "mask" : "true", + "ports" : [ { + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + } ], + "extra ports" : [] +}, +{ + "type" : "sram", + "name" : "RAM128x32", + "depth" : 128, + "width" : 32, + "family" : "1rw", + "mask" : "true", + "ports" : [ { + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + } ], + "extra ports" : [] +}, +{ + "type" : "sram", + "name" : "RAM512x32", + "depth" : 512, + "width" : 32, + "family" : "1rw", + "mask" : "true", + "ports" : [ { + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + } ], + "extra ports" : [] +}, +{ + "type" : "sram", + "name" : "RAM2048x32", + "depth" : 2048, + "width" : 32, + "family" : "1rw", + "mask" : "true", + "ports" : [ { + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + } ], + "extra ports" : [] +}, + +{ + "type" : "sram", + "name" : "sky130_sram_1kbyte_1rw1r_32x256_8", + "depth" : 256, + "width" : 32, + "family" : "1rw1r", + "mask" : "true", + "ports": [ { + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }, { + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + } ], + "extra ports" : [] +}, + +{ + "type" : "sram", + "name" : "sky130_sram_1kbyte_1rw1r_8x1024_8", + "depth" : 1024, + "width" : 8, + "family" : "1rw1r", + "mask" : "true", + "ports": [ { + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }, { + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + } ], + "extra ports" : [] +}, + +{ + "type" : "sram", + "name" : "sky130_sram_2kbyte_1rw1r_32x512_8", + "depth" : 512, + "width" : 32, + "family" : "1rw1r", + "mask" : "true", + "ports": [ { + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }, { + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + } ], + "extra ports" : [] +}, + +{ + "type" : "sram", + "name" : "sky130_sram_4kbyte_1rw1r_32x1024_8", + "depth" : 1024, + "width" : 32, + "family" : "1rw1r", + "mask" : "true", + "ports": [ { + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }, { + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + } ], + "extra ports" : [] +}, + +{ + "type" : "sram", + "name" : "sky130_sram_8kbyte_1rw1r_32x2048_8", + "depth" : 2048, + "width" : 32, + "family" : "1rw1r", + "mask" : "true", + "ports": [ { + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }, { + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + } ], + "extra ports" : [] +}] diff --git a/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py b/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py new file mode 100644 index 000000000..4abcc58ad --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py @@ -0,0 +1,97 @@ + +import os, tempfile, subprocess + +from hammer_vlsi import MMMCCorner, MMMCCornerType, HammerTool, HammerToolStep, HammerSRAMGeneratorTool, SRAMParameters +from hammer_vlsi.units import VoltageValue, TemperatureValue +from hammer_tech import Library, ExtraLibrary +from typing import NamedTuple, Dict, Any, List +from abc import ABCMeta, abstractmethod + +class SKY130SRAMGenerator(HammerSRAMGeneratorTool): + def tool_config_prefix(self) -> str: + return "sram_generator.sky130" + + def version_number(self, version: str) -> int: + return 0 + + # Run generator for a single sram and corner + def generate_sram(self, params: SRAMParameters, corner: MMMCCorner) -> ExtraLibrary: + tech_cache_dir = os.path.abspath(self.technology.cache_dir) + + #TODO: this is really an abuse of the corner stuff + if corner.type == MMMCCornerType.Setup: + speed_name = "slow" + speed = "SS" + elif corner.type == MMMCCornerType.Hold: + speed_name = "fast" + speed = "FF" + elif corner.type == MMMCCornerType.Extra: + speed_name = "typical" + speed = "TT" + + # Different target memories based on port count + if params.family == "1rw": + self.logger.info("Compiling 1rw memories to DFFRAM instances") + base_dir = self.get_setting("technology.sky130.dffram_lib") + fam_code = params.family + sram_name = "RAM{d}x{w}".format( + d=params.depth, + w=params.width) + #TODO: need real libs (perhaps run Liberate here?) + #For now, use the dummy lib for all corners + corner_str = "" # + lib_path = "{b}/{n}.lib".format( + b=base_dir, + n=sram_name) + if not os.path.exists(lib_path): + self.logger.error("SKY130 1rw1r SRAM cache does not support corner: {c}".format(c=corner_str)) + return ExtraLibrary(prefix=None, library=Library( + name=sram_name, + nldm_liberty_file=lib_path, + lef_file="{b}/{n}/{n}.lef".format(b=base_dir,n=sram_name), + #TODO: GDS not generated. Unclear which DEF to use? + #gds_file="{b}/{n}/{n}.gds".format(b=base_dir,n=sram_name), + spice_file="{b}/{n}/{n}.spice".format(b=base_dir,n=sram_name), + #TODO: Will not work as-is for behav. sim (this is a structural netlist referencing std. cells) + #Need to add std cell behavioral Verilog to sim.inputs.input_files + verilog_sim="{b}/{n}/{n}.nl.v".format(b=base_dir,n=sram_name), + corner={'nmos': speed_name, 'pmos': speed_name, 'temperature': str(corner.temp.value_in_units("C")) + " C"}, + supplies={'VDD': str(corner.voltage.value_in_units("V")) + " V", 'GND': "0 V"}, + provides=[{'lib_type': "sram", 'vt': params.vt}])) + elif params.family == "1rw1r": + self.logger.info("Compiling 1rw1r memories to OpenRAM instances") + base_dir = self.get_setting("technology.sky130.openram_lib") + fam_code = params.family + sram_name = "sky130_sram_{s}kbyte_1rw1r_{w}x{d}_{m}".format( + s=round(params.width*params.depth/8, -3)/1000, # size in kiB + w=params.width, + d=params.depth, + m=8) #TODO: Hammer SRAMParameters doesn't have this info + #TODO: replace this if OpenRAM characterization done for other corners + #For now, use typical lib for all corners + corner_str = "TT_1p8V_25C" + #corner_str = "{speed}_{volt}V_{temp}C".format( + # speed = speed, + # volt = str(corner.voltage.value_in_units("V")).replace(".","p"), + # temp = str(int(corner.temp.value_in_units("C"))).replace(".","p")) + lib_path = "{b}/{n}/{n}_{c}.lib".format( + b=base_dir, + n=sram_name, + c=corner_str) + if not os.path.exists(lib_path): + self.logger.error("SKY130 1rw1r SRAM cache does not support corner: {c}".format(c=corner_str)) + return ExtraLibrary(prefix=None, library=Library( + name=sram_name, + nldm_liberty_file=lib_path, + lef_file="{b}/{n}/{n}.lef".format(b=base_dir,n=sram_name), + gds_file="{b}/{n}/{n}.gds".format(b=base_dir,n=sram_name), + spice_file="{b}/{n}/{n}.lvs.sp".format(b=base_dir,n=sram_name), + verilog_sim="{b}/{n}/{n}.v".format(b=base_dir,n=sram_name), + corner={'nmos': speed_name, 'pmos': speed_name, 'temperature': str(corner.temp.value_in_units("C")) + " C"}, + supplies={'VDD': str(corner.voltage.value_in_units("V")) + " V", 'GND': "0 V"}, + provides=[{'lib_type': "sram", 'vt': params.vt}])) + else: + self.logger.error("SKY130 SRAM cache does not support family:{f}".format(f=params.family)) + return ExtraLibrary(prefix=None, library=None) + +tool=SKY130SRAMGenerator diff --git a/src/hammer-vlsi/technology/sky130/srams.txt b/src/hammer-vlsi/technology/sky130/srams.txt new file mode 100644 index 000000000..e1b44abbd --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/srams.txt @@ -0,0 +1,10 @@ +RAM8x32 +RAM32x32 +RAM128x32 +RAM512x32 +RAM2048x32 +sky130_sram_1kbyte_1rw1r_32x256_8 +sky130_sram_1kbyte_1rw1r_8x1024_8 +sky130_sram_2kbyte_1rw1r_32x512_8 +sky130_sram_4kbyte_1rw1r_32x1024_8 +sky130_sram_8kbyte_1rw1r_32x2048_8 diff --git a/src/test/mypy.sh b/src/test/mypy.sh index 45cd5000d..24f7923be 100755 --- a/src/test/mypy.sh +++ b/src/test/mypy.sh @@ -39,6 +39,8 @@ call_mypy ../hammer-vlsi/lvs/*.py call_mypy ../hammer-vlsi/pcb/generic/__init__.py call_mypy ../hammer-vlsi/technology/asap7/*.py call_mypy ../hammer-vlsi/technology/asap7/sram_compiler/__init__.py +call_mypy ../hammer-vlsi/technology/sky130/*.py +call_mypy ../hammer-vlsi/technology/sky130/sram_compiler/__init__.py # Tool plugins which may or may not exist if [ -f ../../../hammer-synopsys-plugins/sim/vcs/__init__.py ]; then From 0f43c56b1ab625097d4bbf59990096d5a18fd280 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 20 May 2021 10:32:17 -0700 Subject: [PATCH 05/81] tlef hack --- src/hammer-vlsi/technology/sky130/__init__.py | 237 +++--------------- .../technology/sky130/sky130.tech.json | 169 +++++++------ 2 files changed, 117 insertions(+), 289 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index c017554d9..a16181a08 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -9,9 +9,10 @@ import re import os #import tempfile -import shutil +#import shutil #from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any +import hammer_tech from hammer_tech import HammerTechnology from hammer_vlsi import HammerTool, HammerPlaceAndRouteTool, TCLTool, HammerToolHookAction @@ -21,211 +22,35 @@ class SKY130Tech(HammerTechnology): This class is loaded by function `load_from_json`, and will pass the `try` in `importlib`. """ def post_install_script(self) -> None: - try: - import gdspy # type: ignore - except ImportError: - self.logger.error("Couldn't import gdspy Python package, needed to merge SKY130 gds.") - shutil.rmtree(self.cache_dir) - sys.exit() - # make cache directories for all necessary lib files - #dirs = 'cdl gds lef lib verilog/models'.split() - dir = 'gds'#for dir in dirs: - os.makedirs(os.path.join(self.cache_dir,dir), exist_ok=True) - # make models dirs in parse_models function - - # useful paths/values - base_dir = self.get_setting("technology.sky130.sky130_pdk") - libraries = os.listdir(base_dir+'/libraries/') - library = 'sky130_fd_sc_hd' - libs_path = base_dir+'/libraries/' - lib_path = libs_path+library+'/latest/' - cells = os.listdir(lib_path+'/cells') - - self.combine_gds(lib_path,library,cells) - #self.combine_lef(lib_path,library,cells) - #self.combine_verilog(lib_path,library,cells) - #self.parse_models(lib_path,library) - #self.combine_cdl(lib_path,library,cells) - #self.lib_setup(lib_path,library) - - def lib_setup(self,lib_path,library) -> None: - # set up file - corners = os.listdir(os.path.join(lib_path,'timing')) - # find ccsnoise corners - ccsnoise_corners = [] - for corner in corners: - if corner.endswith('_ccsnoise.lib'): - corner = corner.replace('_ccsnoise','') - ccsnoise_corners.append(corner) - for corner in corners: - if corner.endswith('_ccsnoise.lib'): - continue - # remove ccsnoise info - if corner in ccsnoise_corners: - f = open(os.path.join(self.cache_dir,'lib',corner), 'w') - lib_file = open(os.path.join(lib_path,'timing',corner),'r') - count = 0; # count brackets :( - ccsn = False - for line in lib_file: - if ( ('ccsn_first_stage' in line) or ('ccsn_last_stage' in line) ): - ccsn = True - if (not ccsn): - f.write(line) - else: - count = count + line.count('{') - count = count - line.count('}') - if count == 0: - ccsn = False - f.close() - # copy rest of lib files to tech cache - elif corner.endswith('.lib'): - shutil.copyfile(os.path.join(lib_path,'timing',corner),os.path.join(self.cache_dir,'lib',corner)) - - def combine_gds(self,lib_path,library,cells) -> None: - import gdspy - # create new gds lib - gds_lib = gdspy.GdsLibrary() - # iterate over all cells - for cell in cells: - cell_path = os.path.join(lib_path,'cells',cell) - cell_files = os.listdir(cell_path) - # iterate over all gds files for each cell - for cell_file_path in cell_files: - if cell_file_path.endswith('.gds'): - cell_gds_path = os.path.join(cell_path,cell_file_path) - # import gds file into gds library - cell_gds = gds_lib.read_gds(cell_gds_path) - gds_lib_path = os.path.join(self.cache_dir,'gds',library+'.gds') - gds_lib.write_gds(gds_lib_path) - - def combine_lef(self,lib_path,library,cells) -> None: - # set up file - f = open(os.path.join(self.cache_dir,"lef",library+".lef"), "w") - f.write('VERSION 5.6 ;\nNAMESCASESENSITIVE ON ;\nBUSBITCHARS "[]" ;\nDIVIDERCHAR "/" ;\n\n') - # iterate over cells - for cell in cells: - cell_path = os.path.join(lib_path,'cells',cell) - cell_files = os.listdir(cell_path) - for cell_file_path in cell_files: - if cell_file_path.endswith('.lef') and not cell_file_path.endswith('magic.lef'): - cell_file = open(os.path.join(cell_path,cell_file_path),"r") - writing=False - for line in cell_file: - if line.startswith("END LIBRARY"): - f.write('\n\n') - break - if line.startswith("MACRO"): - writing=True - if writing: - f.write(line) - f.close() - - def combine_verilog2(self,lib_path,library,cells) -> None: - # set up file - f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") - #f.write('`define UNIT_DELAY \n') # WHERE TF IS THIS DEFINED IN PDK?!?!?! - # include udp models - models = os.listdir(os.path.join(lib_path,'models')) - for model in models: - model_path = os.path.join(self.cache_dir,'verilog','models',library+'__'+model+'.v') - f.write('`include "'+model_path+'"\n') - # iterate over cells - for cell in cells: - cell_path = os.path.join(lib_path,'cells',cell) - cell_files = os.listdir(cell_path) - for cell_file_path in cell_files: - if cell_file_path.endswith('.behavioral.v') or \ - ( cell_file_path.endswith('.v') and cell_file_path.startswith(library+'__'+cell+'_') ): - cell_file = open(os.path.join(cell_path,cell_file_path),"r") - f.write('\n\n') # separate modules - for line in cell_file: - # edit these lines - if line.startswith('`default_nettype none\n'): - line = line.replace('none','wire') - # skip these lines - if '*' in line: continue # comments - if line.startswith('`include'): continue # unnecessary imports - if ('wire 1' in line): continue # dunno why this is in some verilog files - - f.write(line) - f.close() - - def combine_verilog(self,lib_path,library,cells) -> None: - # set up file - f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") - #f.write('`define UNIT_DELAY \n') # WHERE TF IS THIS DEFINED IN PDK?!?!?! - # include udp models - models = os.listdir(os.path.join(lib_path,'models')) - for model in models: - model_path = os.path.join(self.cache_dir,'verilog','models',library+'__'+model+'.blackbox.v') - f.write('`include "'+model_path+'"\n') - # iterate over cells - for cell in cells: - cell_path = os.path.join(lib_path,'cells',cell) - cell_files = os.listdir(cell_path) - for cell_file_path in cell_files: - if cell_file_path.endswith('.behavioral.v') or \ - ( cell_file_path.endswith('.v') and cell_file_path.startswith(library+'__'+cell+'_') ): - cell_file = open(os.path.join(cell_path,cell_file_path),"r") - f.write('\n\n') # separate modules - for line in cell_file: - # edit these lines - if line.startswith('`default_nettype none\n'): - line = line.replace('none','wire') - # skip these lines - if '*' in line: continue # comments - if line.startswith('`include'): continue # unnecessary imports - if ('wire 1' in line): continue # dunno why this is in some verilog files - - f.write(line) - f.close() - def parse_models(self,lib_path,library) -> None: - model_path = os.path.join(lib_path,'models') - models = os.listdir(model_path) - for model in models: - cache_model_path = os.path.join(self.cache_dir,'verilog','models') - model_filename = library+'__'+model+'.blackbox.v' - f = open(os.path.join(cache_model_path,model_filename),'w') - model_file = open(os.path.join(model_path,model,model_filename)) - for line in model_file: - if line.startswith("`default_nettype none"): - line = line.replace('none','wire') - f.write(line) - f.close() - def parse_models2(self,lib_path,library) -> None: - model_path = os.path.join(lib_path,'models') - models = os.listdir(model_path) - for model in models: - cache_model_path = os.path.join(self.cache_dir,'verilog','models') - model_filename = library+'__'+model+'.v' - f = open(os.path.join(cache_model_path,model_filename),'w') - model_file = open(os.path.join(model_path,model,model_filename)) - for line in model_file: - if line.startswith("`default_nettype none"): - line = line.replace('none','wire') - f.write(line) - f.close() - - def combine_cdl(self,lib_path,library,cells) -> None: - # set up file - f = open(os.path.join(self.cache_dir,"cdl",library+".cdl"), "w") - # iterate over cells - for cell in cells: - cell_path = os.path.join(lib_path,'cells',cell) - cell_files = os.listdir(cell_path) - for cell_file_path in cell_files: - if cell_file_path.endswith('.cdl'): - cell_file = open(os.path.join(cell_path,cell_file_path),"r") - writing=False - for line in cell_file: - if line.startswith(".SUBCKT"): - writing=True - if writing: - f.write(line) - if line.startswith(".ENDS"): - f.write('\n\n') - break - f.close() + # maybe run open_pdks for the user and install in tech cache...? + # this takes a while and ~7Gb + + # hack tlef + sky130A = self.get_setting("technology.sky130.sky130A") + lef_files = self.read_libs([ + hammer_tech.filters.lef_filter + ], hammer_tech.HammerTechnologyUtils.to_plain_item) + tlef_new_path = lef_files[0] + words = tlef_new_path.split('/') + tlef_filename = words[-1] + library_name = tlef_filename.split('.')[0] + tlef_old_path = os.path.join(sky130A,'libs.ref',library_name,'techlef',tlef_filename) + + f_old = open(tlef_old_path,'r') + f_new = open(tlef_new_path,'w') + for line in f_old: + f_new.write(line) + if line.strip() == 'END pwell': + f_new.write(''' +LAYER licon + TYPE CUT ; +END licon +''') + + f_old.close() + f_new.close() + print('Loaded Sky130 Tech') + tech = SKY130Tech() diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 97ce77222..29d0fd6c9 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -15,6 +15,10 @@ "path": "$SKY130_NDA", "base var": "technology.sky130.sky130_nda" }, + { + "path": "$SKY130A", + "base var": "technology.sky130.sky130A" + }, { "path": "tech-sky130-cache", "base var": "" @@ -25,8 +29,7 @@ { "tool name": "calibre", "deck name": "all_drc", - "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules", - "newpath": "tech-sky130-cache/drc/s8_drcRules" + "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" } ], "additional_drc_text": "", @@ -42,7 +45,7 @@ "libraries": [ { - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef", + "lef file": "tech-sky130-cache/techlef/sky130_fd_sc_hd.tlef", "provides": [ { "lib_type": "technology" @@ -51,11 +54,11 @@ }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -73,11 +76,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -95,11 +98,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -117,11 +120,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -139,11 +142,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -161,11 +164,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -183,11 +186,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -205,11 +208,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -227,11 +230,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -249,11 +252,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -271,11 +274,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -293,11 +296,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -315,11 +318,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -337,11 +340,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -359,11 +362,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "typical", "pmos": "typical", @@ -381,11 +384,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "typical", "pmos": "typical", From 050c5a06547b12507913c4aadc9f08d8ec5feedc Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Thu, 20 May 2021 12:56:13 -0700 Subject: [PATCH 06/81] Single eFabless SRAM dual-port SRAM posing as single-port --- .../technology/sky130/sram-cache-gen.py | 4 +- .../technology/sky130/sram-cache.json | 349 +++--------------- .../sky130/sram_compiler/__init__.py | 69 ++-- src/hammer-vlsi/technology/sky130/srams.txt | 5 - 4 files changed, 87 insertions(+), 340 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/sram-cache-gen.py b/src/hammer-vlsi/technology/sky130/sram-cache-gen.py index bc2fe903b..9caf01c89 100755 --- a/src/hammer-vlsi/technology/sky130/sram-cache-gen.py +++ b/src/hammer-vlsi/technology/sky130/sram-cache-gen.py @@ -33,7 +33,7 @@ def main(args: List[str]) -> int: json.append("""{{ "type" : "sram", "name" : "{n}", - "depth" : {d}, + "depth" : "{d}", "width" : {w}, "family" : "1rw", "mask" : "true", @@ -65,7 +65,7 @@ def main(args: List[str]) -> int: {{ "type" : "sram", "name" : "{n}", - "depth" : {d}, + "depth" : "{d}", "width" : {w}, "family" : "1rw1r", "mask" : "true", diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json index b703238ec..421880750 100644 --- a/src/hammer-vlsi/technology/sky130/sram-cache.json +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -1,301 +1,50 @@ [ -{ - "type" : "sram", - "name" : "RAM8x32", - "depth" : 8, - "width" : 32, - "family" : "1rw", - "mask" : "true", - "ports" : [ { - "address port name" : "A", - "address port polarity" : "active high", - "clock port name" : "CLK", - "clock port polarity" : "positive edge", - "output port name" : "Do", - "output port polarity" : "active high", - "input port name" : "Di", - "input port polarity" : "active high", - "chip enable port name" : "EN", - "chip enable port polarity" : "active high", - "mask port name" : "WE", - "mask port polarity" : "active high", - "mask granularity" : 8 - } ], - "extra ports" : [] -}, -{ - "type" : "sram", - "name" : "RAM32x32", - "depth" : 32, - "width" : 32, - "family" : "1rw", - "mask" : "true", - "ports" : [ { - "address port name" : "A", - "address port polarity" : "active high", - "clock port name" : "CLK", - "clock port polarity" : "positive edge", - "output port name" : "Do", - "output port polarity" : "active high", - "input port name" : "Di", - "input port polarity" : "active high", - "chip enable port name" : "EN", - "chip enable port polarity" : "active high", - "mask port name" : "WE", - "mask port polarity" : "active high", - "mask granularity" : 8 - } ], - "extra ports" : [] -}, -{ - "type" : "sram", - "name" : "RAM128x32", - "depth" : 128, - "width" : 32, - "family" : "1rw", - "mask" : "true", - "ports" : [ { - "address port name" : "A", - "address port polarity" : "active high", - "clock port name" : "CLK", - "clock port polarity" : "positive edge", - "output port name" : "Do", - "output port polarity" : "active high", - "input port name" : "Di", - "input port polarity" : "active high", - "chip enable port name" : "EN", - "chip enable port polarity" : "active high", - "mask port name" : "WE", - "mask port polarity" : "active high", - "mask granularity" : 8 - } ], - "extra ports" : [] -}, -{ - "type" : "sram", - "name" : "RAM512x32", - "depth" : 512, - "width" : 32, - "family" : "1rw", - "mask" : "true", - "ports" : [ { - "address port name" : "A", - "address port polarity" : "active high", - "clock port name" : "CLK", - "clock port polarity" : "positive edge", - "output port name" : "Do", - "output port polarity" : "active high", - "input port name" : "Di", - "input port polarity" : "active high", - "chip enable port name" : "EN", - "chip enable port polarity" : "active high", - "mask port name" : "WE", - "mask port polarity" : "active high", - "mask granularity" : 8 - } ], - "extra ports" : [] -}, -{ - "type" : "sram", - "name" : "RAM2048x32", - "depth" : 2048, - "width" : 32, - "family" : "1rw", - "mask" : "true", - "ports" : [ { - "address port name" : "A", - "address port polarity" : "active high", - "clock port name" : "CLK", - "clock port polarity" : "positive edge", - "output port name" : "Do", - "output port polarity" : "active high", - "input port name" : "Di", - "input port polarity" : "active high", - "chip enable port name" : "EN", - "chip enable port polarity" : "active high", - "mask port name" : "WE", - "mask port polarity" : "active high", - "mask granularity" : 8 - } ], - "extra ports" : [] -}, - -{ - "type" : "sram", - "name" : "sky130_sram_1kbyte_1rw1r_32x256_8", - "depth" : 256, - "width" : 32, - "family" : "1rw1r", - "mask" : "true", - "ports": [ { - "address port name" : "addr0", - "address port polarity" : "active high", - "clock port name" : "clk0", - "clock port polarity" : "positive edge", - "write enable port name" : "web0", - "write enable port polarity" : "active low", - "output port name" : "dout0", - "output port polarity" : "active high", - "input port name" : "din0", - "input port polarity" : "active high", - "chip enable port name" : "csb0", - "chip enable port polarity" : "active low", - "mask port name" : "wmask0", - "mask port polarity" : "active high", - "mask granularity" : 8 - }, { - "address port name" : "addr1", - "address port polarity" : "active high", - "clock port name" : "clk1", - "clock port polarity" : "positive edge", - "output port name" : "dout1", - "output port polarity" : "active high", - "chip enable port name" : "csb1", - "chip enable port polarity" : "active low" - } ], - "extra ports" : [] -}, - -{ - "type" : "sram", - "name" : "sky130_sram_1kbyte_1rw1r_8x1024_8", - "depth" : 1024, - "width" : 8, - "family" : "1rw1r", - "mask" : "true", - "ports": [ { - "address port name" : "addr0", - "address port polarity" : "active high", - "clock port name" : "clk0", - "clock port polarity" : "positive edge", - "write enable port name" : "web0", - "write enable port polarity" : "active low", - "output port name" : "dout0", - "output port polarity" : "active high", - "input port name" : "din0", - "input port polarity" : "active high", - "chip enable port name" : "csb0", - "chip enable port polarity" : "active low", - "mask port name" : "wmask0", - "mask port polarity" : "active high", - "mask granularity" : 8 - }, { - "address port name" : "addr1", - "address port polarity" : "active high", - "clock port name" : "clk1", - "clock port polarity" : "positive edge", - "output port name" : "dout1", - "output port polarity" : "active high", - "chip enable port name" : "csb1", - "chip enable port polarity" : "active low" - } ], - "extra ports" : [] -}, - -{ - "type" : "sram", - "name" : "sky130_sram_2kbyte_1rw1r_32x512_8", - "depth" : 512, - "width" : 32, - "family" : "1rw1r", - "mask" : "true", - "ports": [ { - "address port name" : "addr0", - "address port polarity" : "active high", - "clock port name" : "clk0", - "clock port polarity" : "positive edge", - "write enable port name" : "web0", - "write enable port polarity" : "active low", - "output port name" : "dout0", - "output port polarity" : "active high", - "input port name" : "din0", - "input port polarity" : "active high", - "chip enable port name" : "csb0", - "chip enable port polarity" : "active low", - "mask port name" : "wmask0", - "mask port polarity" : "active high", - "mask granularity" : 8 - }, { - "address port name" : "addr1", - "address port polarity" : "active high", - "clock port name" : "clk1", - "clock port polarity" : "positive edge", - "output port name" : "dout1", - "output port polarity" : "active high", - "chip enable port name" : "csb1", - "chip enable port polarity" : "active low" - } ], - "extra ports" : [] -}, - -{ - "type" : "sram", - "name" : "sky130_sram_4kbyte_1rw1r_32x1024_8", - "depth" : 1024, - "width" : 32, - "family" : "1rw1r", - "mask" : "true", - "ports": [ { - "address port name" : "addr0", - "address port polarity" : "active high", - "clock port name" : "clk0", - "clock port polarity" : "positive edge", - "write enable port name" : "web0", - "write enable port polarity" : "active low", - "output port name" : "dout0", - "output port polarity" : "active high", - "input port name" : "din0", - "input port polarity" : "active high", - "chip enable port name" : "csb0", - "chip enable port polarity" : "active low", - "mask port name" : "wmask0", - "mask port polarity" : "active high", - "mask granularity" : 8 - }, { - "address port name" : "addr1", - "address port polarity" : "active high", - "clock port name" : "clk1", - "clock port polarity" : "positive edge", - "output port name" : "dout1", - "output port polarity" : "active high", - "chip enable port name" : "csb1", - "chip enable port polarity" : "active low" - } ], - "extra ports" : [] -}, - -{ - "type" : "sram", - "name" : "sky130_sram_8kbyte_1rw1r_32x2048_8", - "depth" : 2048, - "width" : 32, - "family" : "1rw1r", - "mask" : "true", - "ports": [ { - "address port name" : "addr0", - "address port polarity" : "active high", - "clock port name" : "clk0", - "clock port polarity" : "positive edge", - "write enable port name" : "web0", - "write enable port polarity" : "active low", - "output port name" : "dout0", - "output port polarity" : "active high", - "input port name" : "din0", - "input port polarity" : "active high", - "chip enable port name" : "csb0", - "chip enable port polarity" : "active low", - "mask port name" : "wmask0", - "mask port polarity" : "active high", - "mask granularity" : 8 - }, { - "address port name" : "addr1", - "address port polarity" : "active high", - "clock port name" : "clk1", - "clock port polarity" : "positive edge", - "output port name" : "dout1", - "output port polarity" : "active high", - "chip enable port name" : "csb1", - "chip enable port polarity" : "active low" - } ], - "extra ports" : [] -}] + { + "type": "sram", + "name": "sky130_sram_8kbyte_1rw1r_32x2048_8", + "depth": "2048", + "width": 32, + "family": "1rw", + "mask": "true", + "vt": "svt", + "ports": [ + { + "address port name": "addr0", + "address port polarity": "active high", + "clock port name": "clk0", + "clock port polarity": "positive edge", + "write enable port name": "web0", + "write enable port polarity": "active low", + "output port name": "dout0", + "output port polarity": "active high", + "input port name": "din0", + "input port polarity": "active high", + "chip enable port name": "csb0", + "chip enable port polarity": "active low", + "mask port name": "wmask0", + "mask port polarity": "active high", + "mask granularity": 8 + } + ], + "extra ports": [ + { + "name": "clk1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "csb1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "addr1", + "width": 11, + "type": "constant", + "value": 0 + } + ] + } +] \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py b/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py index 4abcc58ad..2283023fb 100644 --- a/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py +++ b/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py @@ -30,43 +30,46 @@ def generate_sram(self, params: SRAMParameters, corner: MMMCCorner) -> ExtraLibr speed = "TT" # Different target memories based on port count + # if params.family == "1rw": + # self.logger.info("Compiling 1rw memories to DFFRAM instances") + # base_dir = self.get_setting("technology.sky130.dffram_lib") + # fam_code = params.family + # sram_name = "RAM{d}x{w}".format( + # d=params.depth, + # w=params.width) + # #TODO: need real libs (perhaps run Liberate here?) + # #For now, use the dummy lib for all corners + # corner_str = "" # + # lib_path = "{b}/{n}.lib".format( + # b=base_dir, + # n=sram_name) + # if not os.path.exists(lib_path): + # self.logger.error("SKY130 1rw1r SRAM cache does not support corner: {c}".format(c=corner_str)) + # return ExtraLibrary(prefix=None, library=Library( + # name=sram_name, + # nldm_liberty_file=lib_path, + # lef_file="{b}/{n}/{n}.lef".format(b=base_dir,n=sram_name), + # #TODO: GDS not generated. Unclear which DEF to use? + # #gds_file="{b}/{n}/{n}.gds".format(b=base_dir,n=sram_name), + # spice_file="{b}/{n}/{n}.spice".format(b=base_dir,n=sram_name), + # #TODO: Will not work as-is for behav. sim (this is a structural netlist referencing std. cells) + # #Need to add std cell behavioral Verilog to sim.inputs.input_files + # verilog_sim="{b}/{n}/{n}.nl.v".format(b=base_dir,n=sram_name), + # corner={'nmos': speed_name, 'pmos': speed_name, 'temperature': str(corner.temp.value_in_units("C")) + " C"}, + # supplies={'VDD': str(corner.voltage.value_in_units("V")) + " V", 'GND': "0 V"}, + # provides=[{'lib_type': "sram", 'vt': params.vt}])) + # elif params.family == "1rw1r": if params.family == "1rw": - self.logger.info("Compiling 1rw memories to DFFRAM instances") - base_dir = self.get_setting("technology.sky130.dffram_lib") - fam_code = params.family - sram_name = "RAM{d}x{w}".format( - d=params.depth, - w=params.width) - #TODO: need real libs (perhaps run Liberate here?) - #For now, use the dummy lib for all corners - corner_str = "" # - lib_path = "{b}/{n}.lib".format( - b=base_dir, - n=sram_name) - if not os.path.exists(lib_path): - self.logger.error("SKY130 1rw1r SRAM cache does not support corner: {c}".format(c=corner_str)) - return ExtraLibrary(prefix=None, library=Library( - name=sram_name, - nldm_liberty_file=lib_path, - lef_file="{b}/{n}/{n}.lef".format(b=base_dir,n=sram_name), - #TODO: GDS not generated. Unclear which DEF to use? - #gds_file="{b}/{n}/{n}.gds".format(b=base_dir,n=sram_name), - spice_file="{b}/{n}/{n}.spice".format(b=base_dir,n=sram_name), - #TODO: Will not work as-is for behav. sim (this is a structural netlist referencing std. cells) - #Need to add std cell behavioral Verilog to sim.inputs.input_files - verilog_sim="{b}/{n}/{n}.nl.v".format(b=base_dir,n=sram_name), - corner={'nmos': speed_name, 'pmos': speed_name, 'temperature': str(corner.temp.value_in_units("C")) + " C"}, - supplies={'VDD': str(corner.voltage.value_in_units("V")) + " V", 'GND': "0 V"}, - provides=[{'lib_type': "sram", 'vt': params.vt}])) - elif params.family == "1rw1r": self.logger.info("Compiling 1rw1r memories to OpenRAM instances") base_dir = self.get_setting("technology.sky130.openram_lib") fam_code = params.family - sram_name = "sky130_sram_{s}kbyte_1rw1r_{w}x{d}_{m}".format( - s=round(params.width*params.depth/8, -3)/1000, # size in kiB - w=params.width, - d=params.depth, - m=8) #TODO: Hammer SRAMParameters doesn't have this info + s=round(round(params.width*params.depth/8, -3)/1000) # size in kiB + w=params.width + d=params.depth + m=8 + sram_name = f"sky130_sram_{s}kbyte_1rw1r_{w}x{d}_{m}" + print(f"SRAM_NAME: {sram_name}") + #TODO: Hammer SRAMParameters doesn't have this info #TODO: replace this if OpenRAM characterization done for other corners #For now, use typical lib for all corners corner_str = "TT_1p8V_25C" diff --git a/src/hammer-vlsi/technology/sky130/srams.txt b/src/hammer-vlsi/technology/sky130/srams.txt index e1b44abbd..1c9be4b71 100644 --- a/src/hammer-vlsi/technology/sky130/srams.txt +++ b/src/hammer-vlsi/technology/sky130/srams.txt @@ -1,8 +1,3 @@ -RAM8x32 -RAM32x32 -RAM128x32 -RAM512x32 -RAM2048x32 sky130_sram_1kbyte_1rw1r_32x256_8 sky130_sram_1kbyte_1rw1r_8x1024_8 sky130_sram_2kbyte_1rw1r_32x512_8 From c7574cc6e591ab455104b0411263a53f5f1dd02c Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Fri, 21 May 2021 08:50:54 -0700 Subject: [PATCH 07/81] WIP PnR Debug --- src/hammer-vlsi/technology/sky130/__init__.py | 38 ++-- .../technology/sky130/sky130.tech.json | 215 +++++++++++++++--- 2 files changed, 198 insertions(+), 55 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index a16181a08..986028f2a 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -8,8 +8,7 @@ import sys import re import os -#import tempfile -#import shutil +from pathlib import Path #from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any import hammer_tech @@ -25,32 +24,35 @@ def post_install_script(self) -> None: # maybe run open_pdks for the user and install in tech cache...? # this takes a while and ~7Gb - # hack tlef - sky130A = self.get_setting("technology.sky130.sky130A") - lef_files = self.read_libs([ - hammer_tech.filters.lef_filter - ], hammer_tech.HammerTechnologyUtils.to_plain_item) - tlef_new_path = lef_files[0] - words = tlef_new_path.split('/') - tlef_filename = words[-1] - library_name = tlef_filename.split('.')[0] - tlef_old_path = os.path.join(sky130A,'libs.ref',library_name,'techlef',tlef_filename) + # hack tlef, adding this very important `licon` section + setting_dir = self.get_setting("technology.sky130.open_pdks") + setting_dir = Path(setting_dir) + library_name = 'sky130_fd_sc_hd' + tlef_old_path = setting_dir / 'sky130'/ 'sky130A' / 'libs.ref' / library_name / 'techlef' / f'{library_name}.tlef' + if not tlef_old_path.exists(): + raise FileNotFoundError(f"Tech-LEF not found: {tlef_old_path}") + + cache_tech_dir_path = Path(self.cache_dir) / 'techlef' + os.makedirs(cache_tech_dir_path, exist_ok=True) + tlef_new_path = cache_tech_dir_path / f'{library_name}.tlef' f_old = open(tlef_old_path,'r') f_new = open(tlef_new_path,'w') for line in f_old: f_new.write(line) if line.strip() == 'END pwell': - f_new.write(''' -LAYER licon - TYPE CUT ; -END licon -''') - + f_new.write(_the_tlef_edit) + f_old.close() f_new.close() print('Loaded Sky130 Tech') +_the_tlef_edit = ''' +LAYER licon + TYPE CUT ; +END licon +''' + tech = SKY130Tech() diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 29d0fd6c9..84abb4b35 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -33,7 +33,6 @@ } ], "additional_drc_text": "", - "lvs decks": [ { "tool name": "calibre", @@ -42,7 +41,6 @@ } ], "additional_lvs_text": "", - "libraries": [ { "lef file": "tech-sky130-cache/techlef/sky130_fd_sc_hd.tlef", @@ -52,7 +50,6 @@ } ] }, - { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", @@ -71,7 +68,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -93,7 +90,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -115,7 +112,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -137,7 +134,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -159,7 +156,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -181,7 +178,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -203,7 +200,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -225,7 +222,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -247,7 +244,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -269,7 +266,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -291,7 +288,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -313,7 +310,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -335,7 +332,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -357,7 +354,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -379,7 +376,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -401,7 +398,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] } @@ -410,31 +407,175 @@ { "name": "sky130_fd_sc_hd", "metals": [ - {"name": "li1", "index": 1, "direction": "vertical", "min_width": 0.17, "max_width": 2147483.647, "pitch": 0.34, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.17}]}, - {"name": "met1", "index": 2, "direction": "horizontal", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.17, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, - {"name": "met2", "index": 3, "direction": "vertical", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, - {"name": "met3", "index": 4, "direction": "horizontal", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.34, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, - {"name": "met4", "index": 5, "direction": "vertical", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.46, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, - {"name": "met5", "index": 6, "direction": "horizontal", "min_width": 1.6, "max_width": 2147483.647, "pitch": 3.2, "offset": 1.7, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 1.6}]} + { + "name": "li1", + "index": 1, + "direction": "vertical", + "min_width": 0.17, + "max_width": 2147483.647, + "pitch": 0.34, + "offset": 0.23, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.17 + } + ] + }, + { + "name": "met1", + "index": 2, + "direction": "horizontal", + "min_width": 0.14, + "max_width": 2147483.647, + "pitch": 0.28, + "offset": 0.17, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.14 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.28 + } + ] + }, + { + "name": "met2", + "index": 3, + "direction": "vertical", + "min_width": 0.14, + "max_width": 2147483.647, + "pitch": 0.28, + "offset": 0.23, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.14 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.28 + } + ] + }, + { + "name": "met3", + "index": 4, + "direction": "horizontal", + "min_width": 0.3, + "max_width": 2147483.647, + "pitch": 0.6, + "offset": 0.34, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.3 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.4 + } + ] + }, + { + "name": "met4", + "index": 5, + "direction": "vertical", + "min_width": 0.3, + "max_width": 2147483.647, + "pitch": 0.6, + "offset": 0.46, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.3 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.4 + } + ] + }, + { + "name": "met5", + "index": 6, + "direction": "horizontal", + "min_width": 1.6, + "max_width": 2147483.647, + "pitch": 3.2, + "offset": 1.7, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 1.6 + } + ] + } ] } ], "sites": [ - {"name": "unithd", "x": 0.46, "y": 2.72}, - {"name": "unithddbl", "x": 0.46, "y": 5.44} + { + "name": "unithd", + "x": 0.46, + "y": 2.72 + }, + { + "name": "unithddbl", + "x": 0.46, + "y": 5.44 + } ], "physical only cells list": [ - "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", - "sky130_fd_sc_hd__tapvgnd_1", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4", + "sky130_fd_sc_hd__tap_1", + "sky130_fd_sc_hd__tap_2", + "sky130_fd_sc_hd__tapvgnd_1", "sky130_fd_sc_hd__tapvpwrvgnd_1", - "sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8" + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", + "sky130_fd_sc_hd__decap_3", + "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", + "sky130_fd_sc_hd__decap_8" ], "special cells": [ - {"cell_type": "tapcell", "name": ["sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2"]}, - {"cell_type": "stdfiller", "name": ["sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", - "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", - "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8"]} + { + "cell_type": "tapcell", + "name": [ + "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2", + "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4", + "sky130_fd_sc_hd__tap_1", + "sky130_fd_sc_hd__tap_2" + ] + }, + { + "cell_type": "stdfiller", + "name": [ + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", + "sky130_fd_sc_hd__decap_3", + "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", + "sky130_fd_sc_hd__decap_8" + ] + } ] -} +} \ No newline at end of file From 490a72d4da7d02b8a814d559b97a7626873d7922 Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Wed, 26 May 2021 12:23:11 -0700 Subject: [PATCH 08/81] Update sky130.tech.json --- .../technology/sky130/sky130.tech.json | 221 ++++++++++++++---- 1 file changed, 173 insertions(+), 48 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 29d0fd6c9..96182230e 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -7,10 +7,6 @@ "path": "$SKY130_PDK", "base var": "technology.sky130.sky130_pdk" }, - { - "path": "$OPEN_PDKS", - "base var": "technology.sky130.open_pdks" - }, { "path": "$SKY130_NDA", "base var": "technology.sky130.sky130_nda" @@ -24,7 +20,7 @@ "base var": "" } ], - "gds map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "gds map file": "tech-sky130-cache/technology_library.layermap", "drc decks": [ { "tool name": "calibre", @@ -33,7 +29,6 @@ } ], "additional_drc_text": "", - "lvs decks": [ { "tool name": "calibre", @@ -42,17 +37,53 @@ } ], "additional_lvs_text": "", - + "physical only cells list": [ + "sky130_fd_sc_hd__tap_1", + "sky130_fd_sc_hd__tap_2", + "sky130_fd_sc_hd__tapvgnd_1", + "sky130_fd_sc_hd__tapvpwrvgnd_1", + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", + "sky130_fd_sc_hd__decap_3", + "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", + "sky130_fd_sc_hd__decap_8" + ], + "special cells": [ + { + "cell_type": "tapcell", + "name": [ + "sky130_fd_sc_hd__tap_1", + "sky130_fd_sc_hd__tap_2" + ] + }, + { + "cell_type": "stdfiller", + "name": [ + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", + "sky130_fd_sc_hd__decap_3", + "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", + "sky130_fd_sc_hd__decap_8" + ] + } + ], "libraries": [ { - "lef file": "tech-sky130-cache/techlef/sky130_fd_sc_hd.tlef", + "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", "provides": [ { "lib_type": "technology" } ] }, - { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", @@ -71,7 +102,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -93,7 +124,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -115,7 +146,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -137,7 +168,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -159,7 +190,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -181,7 +212,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -203,7 +234,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -225,7 +256,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -247,7 +278,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -269,7 +300,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -291,7 +322,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -313,7 +344,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -335,7 +366,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -357,7 +388,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -379,7 +410,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -401,7 +432,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] } @@ -410,31 +441,125 @@ { "name": "sky130_fd_sc_hd", "metals": [ - {"name": "li1", "index": 1, "direction": "vertical", "min_width": 0.17, "max_width": 2147483.647, "pitch": 0.34, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.17}]}, - {"name": "met1", "index": 2, "direction": "horizontal", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.17, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, - {"name": "met2", "index": 3, "direction": "vertical", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, - {"name": "met3", "index": 4, "direction": "horizontal", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.34, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, - {"name": "met4", "index": 5, "direction": "vertical", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.46, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, - {"name": "met5", "index": 6, "direction": "horizontal", "min_width": 1.6, "max_width": 2147483.647, "pitch": 3.2, "offset": 1.7, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 1.6}]} + { + "name": "li1", + "index": 1, + "direction": "vertical", + "min_width": 0.17, + "max_width": 2147483.647, + "pitch": 0.34, + "offset": 0.23, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.17 + } + ] + }, + { + "name": "met1", + "index": 2, + "direction": "horizontal", + "min_width": 0.14, + "max_width": 2147483.647, + "pitch": 0.28, + "offset": 0.17, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.14 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.28 + } + ] + }, + { + "name": "met2", + "index": 3, + "direction": "vertical", + "min_width": 0.14, + "max_width": 2147483.647, + "pitch": 0.28, + "offset": 0.23, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.14 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.28 + } + ] + }, + { + "name": "met3", + "index": 4, + "direction": "horizontal", + "min_width": 0.3, + "max_width": 2147483.647, + "pitch": 0.6, + "offset": 0.34, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.3 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.4 + } + ] + }, + { + "name": "met4", + "index": 5, + "direction": "vertical", + "min_width": 0.3, + "max_width": 2147483.647, + "pitch": 0.6, + "offset": 0.46, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.3 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.4 + } + ] + }, + { + "name": "met5", + "index": 6, + "direction": "horizontal", + "min_width": 1.6, + "max_width": 2147483.647, + "pitch": 3.2, + "offset": 1.7, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 1.6 + } + ] + } ] } ], "sites": [ - {"name": "unithd", "x": 0.46, "y": 2.72}, - {"name": "unithddbl", "x": 0.46, "y": 5.44} - ], - "physical only cells list": [ - "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", - "sky130_fd_sc_hd__tapvgnd_1", - "sky130_fd_sc_hd__tapvpwrvgnd_1", - "sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8" - ], - "special cells": [ - {"cell_type": "tapcell", "name": ["sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2"]}, - {"cell_type": "stdfiller", "name": ["sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", - "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", - "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8"]} + { + "name": "unithd", + "x": 0.46, + "y": 2.72 + }, + { + "name": "unithddbl", + "x": 0.46, + "y": 5.44 + } ] -} +} \ No newline at end of file From 0bb03ada82bc545c08cba6467f6769014d7b29e6 Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Thu, 27 May 2021 12:43:25 -0700 Subject: [PATCH 09/81] Merge Sky130 TLEF Manipulations --- src/hammer-vlsi/technology/sky130/__init__.py | 38 ++++++++++--------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index a16181a08..986028f2a 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -8,8 +8,7 @@ import sys import re import os -#import tempfile -#import shutil +from pathlib import Path #from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any import hammer_tech @@ -25,32 +24,35 @@ def post_install_script(self) -> None: # maybe run open_pdks for the user and install in tech cache...? # this takes a while and ~7Gb - # hack tlef - sky130A = self.get_setting("technology.sky130.sky130A") - lef_files = self.read_libs([ - hammer_tech.filters.lef_filter - ], hammer_tech.HammerTechnologyUtils.to_plain_item) - tlef_new_path = lef_files[0] - words = tlef_new_path.split('/') - tlef_filename = words[-1] - library_name = tlef_filename.split('.')[0] - tlef_old_path = os.path.join(sky130A,'libs.ref',library_name,'techlef',tlef_filename) + # hack tlef, adding this very important `licon` section + setting_dir = self.get_setting("technology.sky130.open_pdks") + setting_dir = Path(setting_dir) + library_name = 'sky130_fd_sc_hd' + tlef_old_path = setting_dir / 'sky130'/ 'sky130A' / 'libs.ref' / library_name / 'techlef' / f'{library_name}.tlef' + if not tlef_old_path.exists(): + raise FileNotFoundError(f"Tech-LEF not found: {tlef_old_path}") + + cache_tech_dir_path = Path(self.cache_dir) / 'techlef' + os.makedirs(cache_tech_dir_path, exist_ok=True) + tlef_new_path = cache_tech_dir_path / f'{library_name}.tlef' f_old = open(tlef_old_path,'r') f_new = open(tlef_new_path,'w') for line in f_old: f_new.write(line) if line.strip() == 'END pwell': - f_new.write(''' -LAYER licon - TYPE CUT ; -END licon -''') - + f_new.write(_the_tlef_edit) + f_old.close() f_new.close() print('Loaded Sky130 Tech') +_the_tlef_edit = ''' +LAYER licon + TYPE CUT ; +END licon +''' + tech = SKY130Tech() From 29ad7cdb90e158ee8dba47ed70d6e54135eb92c7 Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Thu, 27 May 2021 13:53:57 -0700 Subject: [PATCH 10/81] Add dont_use scan-flops --- src/hammer-vlsi/technology/sky130/defaults.yml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index 724120b0e..d72ef162c 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -9,7 +9,11 @@ technology.sky130: # Set some defaults for this technology. vlsi: # Technology dimension - core.node: 130 + core: + node: 130 + sram_generator_tool: "sram_compiler" + sram_generator_tool_path: ["${HAMMER_HOME}/src/hammer-vlsi/technology/sky130"] + sram_generator_tool_path_meta: "append" inputs: # Supply voltages. supplies: @@ -17,6 +21,8 @@ vlsi: ground: [{name: "VSS", pin: "VGND"}] VDD: "1.8 V" GND: "0 V" + + dont_use_list: ["*sdf*"] # Scan flops go haywire! Avoid them. # mmmc corners config mmmc_corners: [ From 8e27d78dd22617f50b5940f1a40c8f8113c4b32c Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Thu, 27 May 2021 17:06:02 -0700 Subject: [PATCH 11/81] Copy Sky130 Layer-Map --- src/hammer-vlsi/technology/sky130/__init__.py | 24 +++++++++++++++---- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 986028f2a..318f13062 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -7,7 +7,7 @@ import sys import re -import os +import os, shutil from pathlib import Path #from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any @@ -23,8 +23,12 @@ class SKY130Tech(HammerTechnology): def post_install_script(self) -> None: # maybe run open_pdks for the user and install in tech cache...? # this takes a while and ~7Gb + self.setup_techlef() + self.setup_layermap() + print('Loaded Sky130 Tech') - # hack tlef, adding this very important `licon` section + def setup_techlef(self) -> None: + """ Copy and hack the tech-lef, adding this very important `licon` section """ setting_dir = self.get_setting("technology.sky130.open_pdks") setting_dir = Path(setting_dir) library_name = 'sky130_fd_sc_hd' @@ -32,7 +36,7 @@ def post_install_script(self) -> None: if not tlef_old_path.exists(): raise FileNotFoundError(f"Tech-LEF not found: {tlef_old_path}") - cache_tech_dir_path = Path(self.cache_dir) / 'techlef' + cache_tech_dir_path = Path(self.cache_dir) os.makedirs(cache_tech_dir_path, exist_ok=True) tlef_new_path = cache_tech_dir_path / f'{library_name}.tlef' @@ -42,10 +46,20 @@ def post_install_script(self) -> None: f_new.write(line) if line.strip() == 'END pwell': f_new.write(_the_tlef_edit) - f_old.close() f_new.close() - print('Loaded Sky130 Tech') + + def setup_layermap(self) -> None: + """ Copy the layer-map into `self.cache_dir` """ + nda_dir = self.get_setting("technology.sky130.sky130_nda") + nda_dir = Path(nda_dir) + layermap = nda_dir / "s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap" + if not layermap.exists(): + raise FileNotFoundError(f"Layer-map not found: {layermap}") + cache_path = Path(self.cache_dir) + os.makedirs(cache_path, exist_ok=True) + shutil.copy(layermap, cache_path) + _the_tlef_edit = ''' From 1b20acdbeae72ecea16d4045b2a16220a6a77777 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 1 Jun 2021 10:26:07 -0700 Subject: [PATCH 12/81] removed open_pdks variable, added gds map path --- src/hammer-vlsi/technology/sky130/__init__.py | 4 +-- .../technology/sky130/defaults.yml | 3 +- .../technology/sky130/sky130.tech.json | 35 +++++++++++++++++-- 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 318f13062..7ee5ac236 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -29,10 +29,10 @@ def post_install_script(self) -> None: def setup_techlef(self) -> None: """ Copy and hack the tech-lef, adding this very important `licon` section """ - setting_dir = self.get_setting("technology.sky130.open_pdks") + setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) library_name = 'sky130_fd_sc_hd' - tlef_old_path = setting_dir / 'sky130'/ 'sky130A' / 'libs.ref' / library_name / 'techlef' / f'{library_name}.tlef' + tlef_old_path = setting_dir / 'libs.ref' / library_name / 'techlef' / f'{library_name}.tlef' if not tlef_old_path.exists(): raise FileNotFoundError(f"Tech-LEF not found: {tlef_old_path}") diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index d72ef162c..b1bc0a216 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -1,10 +1,11 @@ # Settings for the sky130 technology to be overriden by the project. technology.sky130: sky130_pdk: "PATH_TO_SKY130_PDK" - open_pdks: "PATH_TO_OPEN_PDKS" sky130_nda: "PATH_TO_NDA_FILES" + sky130A: "PATH_TO_SKY130A_DIR" dffram_lib: "PATH_TO_DFFRAM/Compiler/build" openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" + gds_map_file: "PATH_TO_GDS_MAP_FILE (you must write this)" # Set some defaults for this technology. vlsi: diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 96182230e..e74c44fb7 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -15,12 +15,17 @@ "path": "$SKY130A", "base var": "technology.sky130.sky130A" }, + { + "path": "$GDS_MAP_FILE", + "base var": "technology.sky130.gds_map_file" + }, { "path": "tech-sky130-cache", "base var": "" } ], - "gds map file": "tech-sky130-cache/technology_library.layermap", + "gds map file": "$GDS_MAP_FILE", + "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { "tool name": "calibre", @@ -52,12 +57,12 @@ "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8" ], + "dont use list": [], "special cells": [ { "cell_type": "tapcell", "name": [ - "sky130_fd_sc_hd__tap_1", - "sky130_fd_sc_hd__tap_2" + "sky130_fd_sc_hd__tapvpwrvgnd_1" ] }, { @@ -73,11 +78,24 @@ "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8" ] + }, + { + "cell_type": "tielocell", + "name": [ + "sky130_fd_sc_hd__conb_1" + ] + }, + { + "cell_type": "tiehicell", + "name": [ + "sky130_fd_sc_hd__conb_1" + ] } ], "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", + "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", "provides": [ { "lib_type": "technology" @@ -435,6 +453,17 @@ "vt": "RVT" } ] + }, + { + "lef file": "$SKY130A/libs.ref/sky130_fd_pr/lef/sky130_fd_pr.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_pr/cdl/sky130_fd_pr.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_pr/gds/sky130_fd_pr.gds", + "provides": [ + { + "lib_type": "primitives", + "vt": "RVT" + } + ] } ], "stackups": [ From 99307160fdf3bd25f39cb9c755d9e48ae513dfea Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 1 Jun 2021 10:26:27 -0700 Subject: [PATCH 13/81] removed open_pdks variable, added gds map path --- src/hammer-vlsi/technology/sky130/defaults.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index b1bc0a216..ec7b5ffe5 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -5,7 +5,7 @@ technology.sky130: sky130A: "PATH_TO_SKY130A_DIR" dffram_lib: "PATH_TO_DFFRAM/Compiler/build" openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" - gds_map_file: "PATH_TO_GDS_MAP_FILE (you must write this)" + gds_map_file: "PATH_TO_GDS_MAP_FILE (you must write this file)" # Set some defaults for this technology. vlsi: From c2b0213d7c50a98e9484ceb7ba71092701ffb8db Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 3 Jun 2021 12:35:18 -0700 Subject: [PATCH 14/81] fixed floating nets and CDL netlist device names --- src/hammer-vlsi/technology/sky130/__init__.py | 126 +++++++++++++++++- .../technology/sky130/defaults.yml | 7 + .../technology/sky130/sky130.tech.json | 32 ++--- 3 files changed, 144 insertions(+), 21 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 7ee5ac236..6e8a9faf2 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -9,7 +9,7 @@ import re import os, shutil from pathlib import Path -#from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any +from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any import hammer_tech from hammer_tech import HammerTechnology @@ -23,22 +23,59 @@ class SKY130Tech(HammerTechnology): def post_install_script(self) -> None: # maybe run open_pdks for the user and install in tech cache...? # this takes a while and ~7Gb + self.library_name = 'sky130_fd_sc_hd' + self.setup_cdl() self.setup_techlef() self.setup_layermap() + self.setup_lvs_deck() print('Loaded Sky130 Tech') + # Helper functions - copied from TSMC28 plugin + def expand_tech_cache_path(self, path) -> str: + """ Replace occurrences of the cache directory's basename with + the full path to the cache dir.""" + cache_dir_basename = os.path.basename(self.cache_dir) + return path.replace(cache_dir_basename, self.cache_dir) + + def ensure_dirs_exist(self, path) -> None: + dir_name = os.path.dirname(path) + if not os.path.exists(dir_name): + self.logger.info('Creating directory: {}'.format(dir_name)) + os.makedirs(dir_name) + + # Tech setup steps + def setup_cdl(self) -> None: + """ Copy and hack the cdl, replacing pfet_01v8_hvt/nfet_01v8 with phighvt/nshort """ + setting_dir = self.get_setting("technology.sky130.sky130A") + setting_dir = Path(setting_dir) + cdl_old_path = setting_dir / 'libs.ref' / self.library_name / 'cdl' / f'{self.library_name}.cdl' + if not cdl_old_path.exists(): + raise FileNotFoundError(f"CDL not found: {cdl_old_path}") + + cache_tech_dir_path = Path(self.cache_dir) + os.makedirs(cache_tech_dir_path, exist_ok=True) + cdl_new_path = cache_tech_dir_path / f'{self.library_name}.cdl' + + f_old = open(cdl_old_path,'r') + f_new = open(cdl_new_path,'w') + for line in f_old: + new_line = line.replace('pfet_01v8_hvt','phighvt') + new_line = new_line.replace('nfet_01v8', 'nshort') + f_new.write(new_line) + f_old.close() + f_new.close() + def setup_techlef(self) -> None: """ Copy and hack the tech-lef, adding this very important `licon` section """ setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) - library_name = 'sky130_fd_sc_hd' - tlef_old_path = setting_dir / 'libs.ref' / library_name / 'techlef' / f'{library_name}.tlef' + tlef_old_path = setting_dir / 'libs.ref' / self.library_name / 'techlef' / f'{self.library_name}.tlef' if not tlef_old_path.exists(): raise FileNotFoundError(f"Tech-LEF not found: {tlef_old_path}") cache_tech_dir_path = Path(self.cache_dir) os.makedirs(cache_tech_dir_path, exist_ok=True) - tlef_new_path = cache_tech_dir_path / f'{library_name}.tlef' + tlef_new_path = cache_tech_dir_path / f'{self.library_name}.tlef' f_old = open(tlef_old_path,'r') f_new = open(tlef_new_path,'w') @@ -60,7 +97,40 @@ def setup_layermap(self) -> None: os.makedirs(cache_path, exist_ok=True) shutil.copy(layermap, cache_path) - + def setup_lvs_deck(self) -> None: + """Remove conflicting specification statements found in PDK LVS decks.""" + pattern = '.*({}).*\n'.format('|'.join(LVS_DECK_SCRUB_LINES)) + matcher = re.compile(pattern) + + source_paths = self.get_setting('technology.sky130.lvs_deck_sources') + lvs_decks = list(self.config.lvs_decks) + for i in range(len(lvs_decks)): + deck = lvs_decks[i] + try: + source_path = source_paths[i] + except IndexError: + self.logging.error( + 'No corresponding source for LVS deck {}'.format(deck)) + dest_path = self.expand_tech_cache_path(str(deck.path)) + self.ensure_dirs_exist(dest_path) + with open(source_path, 'r') as sf: + with open(dest_path, 'w') as df: + self.logger.info("Modifying LVS deck: {} -> {}".format + (source_path, dest_path)) + df.write(matcher.sub("", sf.read())) + + def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: + hooks = {"innovus": [ + HammerTool.make_post_insertion_hook("init_design", sky130_innovus_settings), + HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), + #HammerTool.make_replacement_hook("power_straps", intech22_innovus.intech22_reference_power_straps), + # HammerTool.make_post_insertion_hook("power_straps", intech22_innovus.intech22_m2_staples), + # HammerTool.make_pre_insertion_hook("clock_tree", intech22_innovus.intech22_cts_options), + # HammerTool.make_replacement_hook("add_fillers", intech22_innovus.intech22_add_fillers), + ]} + return hooks.get(tool_name, []) + + _the_tlef_edit = ''' LAYER licon @@ -68,5 +138,51 @@ def setup_layermap(self) -> None: END licon ''' +LVS_DECK_SCRUB_LINES = [ + "VIRTUAL CONNECT REPORT", + "SOURCE PRIMARY", + "SOURCE SYSTEM SPICE", + "SOURCE PATH", + "ERC", + "LVS REPORT" +] + +# various Innovus database settings +def sky130_innovus_settings(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "Innovus settings can only run on par" + """Settings for every tool invocation""" + ht.append( + ''' +########################################################## +# Routing attributes [get_db -category route] +########################################################## +#------------------------------------------------------------------------------- +set_db route_design_antenna_diode_insertion 1 +set_db route_design_antenna_cell_name "sky130_fd_sc_hd__diode_2" +set_db route_design_bottom_routing_layer 1 + ''' + ) + return True + +# Pair VDD/VPWR and VSS/VGND nets +# these commands are already added in Innovus.write_netlist, +# but must also occur before power straps are placed +def sky130_power_nets(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "Innovus settings can only run on par" + """Settings for every tool invocation""" + ht.append( + ''' +connect_global_net VDD -type net -net_base_name VPWR +connect_global_net VSS -type net -net_base_name VGND + ''' + ) + return True + + + tech = SKY130Tech() diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index ec7b5ffe5..b9ab93582 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -5,7 +5,10 @@ technology.sky130: sky130A: "PATH_TO_SKY130A_DIR" dffram_lib: "PATH_TO_DFFRAM/Compiler/build" openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" + gds_map_file: "PATH_TO_GDS_MAP_FILE (you must write this file)" + lvs_deck_sources: + - "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" # Set some defaults for this technology. vlsi: @@ -65,3 +68,7 @@ technology.core: par.inputs: gds_merge: true + +# Calibre environment variables +mentor.extra_env_vars: + - PDK_HOME: "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1" \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index e74c44fb7..ab574775d 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -106,7 +106,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -128,7 +128,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -150,7 +150,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -172,7 +172,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -194,7 +194,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -216,7 +216,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -238,7 +238,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -260,7 +260,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -282,7 +282,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -304,7 +304,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -326,7 +326,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -348,7 +348,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -370,7 +370,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -392,7 +392,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -414,7 +414,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "typical", @@ -436,7 +436,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "typical", From 18e7a26351d8c9dff52cb49e53ffec2a4bc8a7b8 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 3 Jun 2021 14:05:35 -0700 Subject: [PATCH 15/81] set met1 as bottom routing layer --- src/hammer-vlsi/technology/sky130/__init__.py | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 6e8a9faf2..406ce0f84 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -121,8 +121,9 @@ def setup_lvs_deck(self) -> None: def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ - HammerTool.make_post_insertion_hook("init_design", sky130_innovus_settings), - HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), + HammerTool.make_post_insertion_hook("init_design", sky130_innovus_settings), + HammerTool.make_pre_insertion_hook("place_tap_cells", sky130_place_endcaps), + HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), #HammerTool.make_replacement_hook("power_straps", intech22_innovus.intech22_reference_power_straps), # HammerTool.make_post_insertion_hook("power_straps", intech22_innovus.intech22_m2_staples), # HammerTool.make_pre_insertion_hook("clock_tree", intech22_innovus.intech22_cts_options), @@ -161,7 +162,7 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: #------------------------------------------------------------------------------- set_db route_design_antenna_diode_insertion 1 set_db route_design_antenna_cell_name "sky130_fd_sc_hd__diode_2" -set_db route_design_bottom_routing_layer 1 +set_db route_design_bottom_routing_layer 2 ''' ) return True @@ -182,7 +183,20 @@ def sky130_power_nets(ht: HammerTool) -> bool: ) return True - +# reference: /tools/commercial/skywater/swtech130/skywater-src-nda/scs8hd/V0.0.2/scripts +def sky130_place_endcaps(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "endcap insertion can only run on par" + ht.append( + ''' +set_db add_endcaps_boundary_tap true +set_db add_endcaps_left_edge sky130_fd_sc_hd__tap_1 +set_db add_endcaps_right_edge sky130_fd_sc_hd__tap_1 +add_endcaps + ''' + ) + return True tech = SKY130Tech() From b8704b8853607c2bd6cd8e3bf5eb28fedce2a727 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 3 Jun 2021 17:43:50 -0700 Subject: [PATCH 16/81] adding supply pin mapping to defaults file --- .../technology/sky130/defaults.yml | 38 ++++++++++--------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index b9ab93582..a67d80922 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -10,6 +10,10 @@ technology.sky130: lvs_deck_sources: - "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" +# Calibre environment variables +mentor.extra_env_vars: + - PDK_HOME: "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1" + # Set some defaults for this technology. vlsi: # Technology dimension @@ -21,26 +25,30 @@ vlsi: inputs: # Supply voltages. supplies: - power: [{name: "VDD", pin: "VPWR"}] - ground: [{name: "VSS", pin: "VGND"}] - VDD: "1.8 V" - GND: "0 V" + power: [ {name: "VDD", pin: "VDD"}, + {name: "VPWR", pin: "VPWR", tie: "VDD"}, + {name: "VPB", pin: "VPB", tie: "VDD"}] + ground: [ {name: "VSS", pin: "VSS"}, + {name: "VGND", pin: "VGND", tie: "VSS"}, + {name: "VNB", pin: "VNB", tie: "VSS"}] + VDD: "1.8 V" + GND: "0 V" dont_use_list: ["*sdf*"] # Scan flops go haywire! Avoid them. # mmmc corners config mmmc_corners: [ { - "name": "sky130_fd_sc_hd__ss_100C_1v60", - "type": "setup", - "voltage": "1.60 V", - "temp": "100 C" + name: "sky130_fd_sc_hd__ss_100C_1v60", + type: "setup", + voltage: "1.60 V", + temp: "100 C" }, { - "name": "sky130_fd_sc_hd__ff_n40C_1v95", - "type": "hold", - "voltage": "1.95 V", - "temp": "-40 C" + name: "sky130_fd_sc_hd__ff_n40C_1v95", + type: "hold", + voltage: "1.95 V", + temp: "-40 C" } ] technology: @@ -67,8 +75,4 @@ technology.core: par.inputs: gds_merge: true - - -# Calibre environment variables -mentor.extra_env_vars: - - PDK_HOME: "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1" \ No newline at end of file + \ No newline at end of file From c2d78e4139dcc238540fdb8476af5f568c2a1a49 Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Sun, 6 Jun 2021 16:29:34 -0700 Subject: [PATCH 17/81] Sky130 using 4k rather than less-mature 8k SRAM --- src/hammer-vlsi/technology/sky130/sram-cache.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json index 421880750..22f714698 100644 --- a/src/hammer-vlsi/technology/sky130/sram-cache.json +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -1,8 +1,8 @@ [ { "type": "sram", - "name": "sky130_sram_8kbyte_1rw1r_32x2048_8", - "depth": "2048", + "name": "sky130_sram_4kbyte_1rw1r_32x1024_8", + "depth": "1024", "width": 32, "family": "1rw", "mask": "true", From 5f5c664d6e8b28353a0f3fcb63c6c344549886bb Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 7 Jun 2021 11:08:14 -0700 Subject: [PATCH 18/81] gcd passes LVS --- src/hammer-vlsi/technology/sky130/__init__.py | 56 ++++++++++++++----- .../technology/sky130/defaults.yml | 21 ++++--- .../technology/sky130/sky130.tech.json | 19 ++----- 3 files changed, 60 insertions(+), 36 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 406ce0f84..13f1a9de6 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -59,9 +59,9 @@ def setup_cdl(self) -> None: f_old = open(cdl_old_path,'r') f_new = open(cdl_new_path,'w') for line in f_old: - new_line = line.replace('pfet_01v8_hvt','phighvt') - new_line = new_line.replace('nfet_01v8', 'nshort') - f_new.write(new_line) + line = line.replace('pfet_01v8_hvt','phighvt') + line = line.replace('nfet_01v8', 'nshort') + f_new.write(line) f_old.close() f_new.close() @@ -122,8 +122,10 @@ def setup_lvs_deck(self) -> None: def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ HammerTool.make_post_insertion_hook("init_design", sky130_innovus_settings), - HammerTool.make_pre_insertion_hook("place_tap_cells", sky130_place_endcaps), + HammerTool.make_pre_insertion_hook("place_tap_cells", sky130_add_endcaps), HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), + HammerTool.make_post_insertion_hook("place_opt_design", sky130_add_tieoffs), + HammerTool.make_pre_insertion_hook("write_design", sky130_connect_nets), #HammerTool.make_replacement_hook("power_straps", intech22_innovus.intech22_reference_power_straps), # HammerTool.make_post_insertion_hook("power_straps", intech22_innovus.intech22_m2_staples), # HammerTool.make_pre_insertion_hook("clock_tree", intech22_innovus.intech22_cts_options), @@ -167,14 +169,30 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: ) return True + + +# reference: /tools/commercial/skywater/swtech130/skywater-src-nda/scs8hd/V0.0.2/scripts +def sky130_add_endcaps(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "endcap insertion can only run on par" + ht.append( + ''' +set_db add_endcaps_boundary_tap true +set_db add_endcaps_left_edge sky130_fd_sc_hd__tap_1 +set_db add_endcaps_right_edge sky130_fd_sc_hd__tap_1 +add_endcaps + ''' + ) + return True + # Pair VDD/VPWR and VSS/VGND nets # these commands are already added in Innovus.write_netlist, # but must also occur before power straps are placed def sky130_power_nets(ht: HammerTool) -> bool: assert isinstance( ht, HammerPlaceAndRouteTool - ), "Innovus settings can only run on par" - """Settings for every tool invocation""" + ), "connect global nets can only run on par" ht.append( ''' connect_global_net VDD -type net -net_base_name VPWR @@ -183,17 +201,29 @@ def sky130_power_nets(ht: HammerTool) -> bool: ) return True -# reference: /tools/commercial/skywater/swtech130/skywater-src-nda/scs8hd/V0.0.2/scripts -def sky130_place_endcaps(ht: HammerTool) -> bool: +# TODO: add these two functions into Hammer Innovus plugin +def sky130_add_tieoffs(ht: HammerTool) -> bool: assert isinstance( ht, HammerPlaceAndRouteTool - ), "endcap insertion can only run on par" + ), "tie high/low cell insertion can only run on par" ht.append( ''' -set_db add_endcaps_boundary_tap true -set_db add_endcaps_left_edge sky130_fd_sc_hd__tap_1 -set_db add_endcaps_right_edge sky130_fd_sc_hd__tap_1 -add_endcaps +set_db add_tieoffs_cells sky130_fd_sc_hd__conb_1 +add_tieoffs + ''' + ) + return True + +def sky130_connect_nets(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "connect global nets can only run on par" + ht.append( + ''' +connect_global_net VDD -type pg_pin -pin_base_name VPWR -all +connect_global_net VDD -type pg_pin -pin_base_name VPB -all +connect_global_net VSS -type pg_pin -pin_base_name VGND -all +connect_global_net VSS -type pg_pin -pin_base_name VNB -all ''' ) return True diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index a67d80922..d37146c8d 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -6,7 +6,9 @@ technology.sky130: dffram_lib: "PATH_TO_DFFRAM/Compiler/build" openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" - gds_map_file: "PATH_TO_GDS_MAP_FILE (you must write this file)" + # GDS map file path, not provided by efabless + gds_map_file: "${CHIPYARD_HOME}/vlsi/sky130-files/sky130_lefpin.map" + lvs_deck_sources: - "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" @@ -24,13 +26,14 @@ vlsi: sram_generator_tool_path_meta: "append" inputs: # Supply voltages. + # TODO: add ability to tie pin to net in Hammer Innovus plugin supplies: - power: [ {name: "VDD", pin: "VDD"}, - {name: "VPWR", pin: "VPWR", tie: "VDD"}, - {name: "VPB", pin: "VPB", tie: "VDD"}] - ground: [ {name: "VSS", pin: "VSS"}, - {name: "VGND", pin: "VGND", tie: "VSS"}, - {name: "VNB", pin: "VNB", tie: "VSS"}] + power: [ {name: "VDD", pin: "VDD"}] + # {name: "VPWR", pin: "VPWR", tie: "VDD"}, + # {name: "VPB", pin: "VPB", tie: "VDD"}] + ground: [ {name: "VSS", pin: "VSS"}] + # {name: "VGND", pin: "VGND", tie: "VSS"}, + # {name: "VNB", pin: "VNB", tie: "VSS"}] VDD: "1.8 V" GND: "0 V" @@ -60,8 +63,8 @@ vlsi: bump_block_cut_layer: "via4" # Set the interval and offset for tap cells - # nk - not sure if this is right?? - tap_cell_interval: "27" + # interval value from the eFPGA---RTL-to-GDS-with-SKY130 + tap_cell_interval: "40" tap_cell_offset: "5" technology.core: diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index ab574775d..bb952f7fb 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -38,10 +38,11 @@ { "tool name": "calibre", "deck name": "all_lvs", - "path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8" + "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", + "path": "tech-sky130-cache/lvsControlFile_s8" } ], - "additional_lvs_text": "", + "additional_lvs_text": "\nLVS FILTER D OPEN SOURCE\nLVS FILTER D OPEN LAYOUT", "physical only cells list": [ "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", @@ -51,11 +52,7 @@ "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", - "sky130_fd_sc_hd__decap_3", - "sky130_fd_sc_hd__decap_4", - "sky130_fd_sc_hd__decap_6", - "sky130_fd_sc_hd__decap_8" + "sky130_fd_sc_hd__diode_2" ], "dont use list": [], "special cells": [ @@ -80,13 +77,7 @@ ] }, { - "cell_type": "tielocell", - "name": [ - "sky130_fd_sc_hd__conb_1" - ] - }, - { - "cell_type": "tiehicell", + "cell_type": "tiehilocell", "name": [ "sky130_fd_sc_hd__conb_1" ] From 7982d44381ad661adb9e1cec929f430bb1954f56 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 7 Jun 2021 13:02:11 -0700 Subject: [PATCH 19/81] fixed path to gds map file --- src/hammer-vlsi/technology/sky130/defaults.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index d37146c8d..ac0148d08 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -7,7 +7,7 @@ technology.sky130: openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" # GDS map file path, not provided by efabless - gds_map_file: "${CHIPYARD_HOME}/vlsi/sky130-files/sky130_lefpin.map" + gds_map_file: "sky130-files/sky130_lefpin.map" lvs_deck_sources: - "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" From b205d3d65ba0665c4f793d0f2de9cf48acc685cd Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 14 Jun 2021 12:08:06 -0700 Subject: [PATCH 20/81] innovus and calibre commands --- src/hammer-vlsi/technology/sky130/__init__.py | 23 +++++++++++++++++++ .../technology/sky130/sky130.tech.json | 10 +++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 13f1a9de6..1ede3a0c2 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -24,6 +24,7 @@ def post_install_script(self) -> None: # maybe run open_pdks for the user and install in tech cache...? # this takes a while and ~7Gb self.library_name = 'sky130_fd_sc_hd' + self.setup_sram_cdl() self.setup_cdl() self.setup_techlef() self.setup_layermap() @@ -42,6 +43,19 @@ def ensure_dirs_exist(self, path) -> None: if not os.path.exists(dir_name): self.logger.info('Creating directory: {}'.format(dir_name)) os.makedirs(dir_name) + + def setup_sram_cdl(self) -> None: + old_path = Path(self.get_setting("technology.sky130.openram_lib")) / 'sky130_sram_4kbyte_1rw1r_32x1024_8' / 'sky130_sram_4kbyte_1rw1r_32x1024_8.lvs.sp' + new_path = self.expand_tech_cache_path('tech-sky130-cache/sky130_sram_4kbyte_1rw1r_32x1024_8/sky130_sram_4kbyte_1rw1r_32x1024_8.lvs.sp') + print(new_path) + self.ensure_dirs_exist(new_path) + with open(old_path,'r') as f_old: + with open(new_path,'w') as f_new: + for line in f_old: + line = line.replace('sky130_fd_pr__pfet_01v8','pshort') + line = line.replace('sky130_fd_pr__nfet_01v8','nshort') + f_new.write(line) + # Tech setup steps def setup_cdl(self) -> None: @@ -118,6 +132,7 @@ def setup_lvs_deck(self) -> None: self.logger.info("Modifying LVS deck: {} -> {}".format (source_path, dest_path)) df.write(matcher.sub("", sf.read())) + df.write(LVS_DECK_INSERT_LINES) def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ @@ -150,6 +165,14 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: "LVS REPORT" ] +# TODO: black boxing sram is temporary!! +LVS_DECK_INSERT_LINES = ''' +LVS FILTER D OPEN SOURCE +LVS FILTER D OPEN LAYOUT + +LVS BOX sky130_sram_4kbyte_1rw1r_32x1024_8 +''' + # various Innovus database settings def sky130_innovus_settings(ht: HammerTool) -> bool: assert isinstance( diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index bb952f7fb..0c19cf51a 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -42,7 +42,7 @@ "path": "tech-sky130-cache/lvsControlFile_s8" } ], - "additional_lvs_text": "\nLVS FILTER D OPEN SOURCE\nLVS FILTER D OPEN LAYOUT", + "additional_lvs_text": "", "physical only cells list": [ "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", @@ -93,6 +93,14 @@ } ] }, + { + "spice file": "/tools/B/nayiri/sky130/chipyard-osci-sky130/vlsi/sky130-files/devices.cdl", + "provides": [ + { + "lib_type": "technology" + } + ] + }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", From 903209f69636f6d9ff494d193159d3c68624d296 Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Wed, 16 Jun 2021 11:46:51 -0700 Subject: [PATCH 21/81] Move Sky130 to use 1-2kB OpenRAM SRAM macros. Exclude them from DRC runs --- src/hammer-vlsi/technology/sky130/__init__.py | 35 ++++--- .../technology/sky130/sram-cache.json | 98 ++++++++++++++++++- 2 files changed, 120 insertions(+), 13 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 1ede3a0c2..898d814dd 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -44,17 +44,27 @@ def ensure_dirs_exist(self, path) -> None: self.logger.info('Creating directory: {}'.format(dir_name)) os.makedirs(dir_name) + @staticmethod + def openram_sram_names() -> None: + """ Return a list of cell-names of the OpenRAM SRAMs (that we'll use). """ + return [ + # "sky130_sram_4kbyte_1rw1r_32x1024_8", # Eventually to be reinstated, some day + "sky130_sram_1kbyte_1rw1r_32x256_8", + "sky130_sram_1kbyte_1rw1r_8x1024_8", + "sky130_sram_2kbyte_1rw1r_32x512_8" + ] + def setup_sram_cdl(self) -> None: - old_path = Path(self.get_setting("technology.sky130.openram_lib")) / 'sky130_sram_4kbyte_1rw1r_32x1024_8' / 'sky130_sram_4kbyte_1rw1r_32x1024_8.lvs.sp' - new_path = self.expand_tech_cache_path('tech-sky130-cache/sky130_sram_4kbyte_1rw1r_32x1024_8/sky130_sram_4kbyte_1rw1r_32x1024_8.lvs.sp') - print(new_path) - self.ensure_dirs_exist(new_path) - with open(old_path,'r') as f_old: - with open(new_path,'w') as f_new: - for line in f_old: - line = line.replace('sky130_fd_pr__pfet_01v8','pshort') - line = line.replace('sky130_fd_pr__nfet_01v8','nshort') - f_new.write(line) + for sram_name in self.openram_sram_names(): + old_path = Path(self.get_setting("technology.sky130.openram_lib")) / sram_name / f"{sram_name}.lvs.sp" + new_path = self.expand_tech_cache_path(f'tech-sky130-cache/{sram_name}/{sram_name}.lvs.sp') + self.ensure_dirs_exist(new_path) + with open(old_path,'r') as f_old: + with open(new_path,'w') as f_new: + for line in f_old: + line = line.replace('sky130_fd_pr__pfet_01v8','pshort') + line = line.replace('sky130_fd_pr__nfet_01v8','nshort') + f_new.write(line) # Tech setup steps @@ -165,13 +175,14 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: "LVS REPORT" ] -# TODO: black boxing sram is temporary!! LVS_DECK_INSERT_LINES = ''' LVS FILTER D OPEN SOURCE LVS FILTER D OPEN LAYOUT -LVS BOX sky130_sram_4kbyte_1rw1r_32x1024_8 ''' +# TODO: black boxing sram is temporary!! +for name in SKY130Tech.openram_sram_names(): + LVS_DECK_INSERT_LINES += f"LVS BOX {name} \n" # various Innovus database settings def sky130_innovus_settings(ht: HammerTool) -> bool: diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json index 22f714698..5c05e5d2b 100644 --- a/src/hammer-vlsi/technology/sky130/sram-cache.json +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -1,8 +1,104 @@ [ { "type": "sram", - "name": "sky130_sram_4kbyte_1rw1r_32x1024_8", + "name": "sky130_sram_1kbyte_1rw1r_8x1024_8", "depth": "1024", + "width": 8, + "family": "1rw", + "mask": "true", + "vt": "svt", + "ports": [ + { + "address port name": "addr0", + "address port polarity": "active high", + "clock port name": "clk0", + "clock port polarity": "positive edge", + "write enable port name": "web0", + "write enable port polarity": "active low", + "output port name": "dout0", + "output port polarity": "active high", + "input port name": "din0", + "input port polarity": "active high", + "chip enable port name": "csb0", + "chip enable port polarity": "active low", + "mask port name": "wmask0", + "mask port polarity": "active high", + "mask granularity": 8 + } + ], + "extra ports": [ + { + "name": "clk1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "csb1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "addr1", + "width": 11, + "type": "constant", + "value": 0 + } + ] + }, + { + "type": "sram", + "name": "sky130_sram_1kbyte_1rw1r_32x256_8", + "depth": "256", + "width": 32, + "family": "1rw", + "mask": "true", + "vt": "svt", + "ports": [ + { + "address port name": "addr0", + "address port polarity": "active high", + "clock port name": "clk0", + "clock port polarity": "positive edge", + "write enable port name": "web0", + "write enable port polarity": "active low", + "output port name": "dout0", + "output port polarity": "active high", + "input port name": "din0", + "input port polarity": "active high", + "chip enable port name": "csb0", + "chip enable port polarity": "active low", + "mask port name": "wmask0", + "mask port polarity": "active high", + "mask granularity": 8 + } + ], + "extra ports": [ + { + "name": "clk1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "csb1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "addr1", + "width": 11, + "type": "constant", + "value": 0 + } + ] + }, + { + "type": "sram", + "name": "sky130_sram_2kbyte_1rw1r_32x512_8", + "depth": "512", "width": 32, "family": "1rw", "mask": "true", From c471edf19a3f702c3a80e32ed25f92b840250bca Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Thu, 17 Jun 2021 22:01:02 -0700 Subject: [PATCH 22/81] Bug-fix unused port widths on Sky130 SRAMs --- src/hammer-vlsi/technology/sky130/sram-cache.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json index 5c05e5d2b..fa459914a 100644 --- a/src/hammer-vlsi/technology/sky130/sram-cache.json +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -41,7 +41,7 @@ }, { "name": "addr1", - "width": 11, + "width": 10, "type": "constant", "value": 0 } @@ -89,7 +89,7 @@ }, { "name": "addr1", - "width": 11, + "width": 8, "type": "constant", "value": 0 } @@ -137,7 +137,7 @@ }, { "name": "addr1", - "width": 11, + "width": 9, "type": "constant", "value": 0 } From ea4ecbd0201bc814cd2091a47519faefb8133762 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 26 Jul 2021 16:25:36 -0700 Subject: [PATCH 23/81] sky130 plugin updates from tapeout --- src/hammer-vlsi/technology/sky130/__init__.py | 130 +++++++++++++++--- .../technology/sky130/defaults.yml | 21 +-- .../technology/sky130/sky130.tech.json | 55 ++++---- 3 files changed, 148 insertions(+), 58 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 898d814dd..f5778840c 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -26,8 +26,8 @@ def post_install_script(self) -> None: self.library_name = 'sky130_fd_sc_hd' self.setup_sram_cdl() self.setup_cdl() + self.setup_verilog() self.setup_techlef() - self.setup_layermap() self.setup_lvs_deck() print('Loaded Sky130 Tech') @@ -70,6 +70,7 @@ def setup_sram_cdl(self) -> None: # Tech setup steps def setup_cdl(self) -> None: """ Copy and hack the cdl, replacing pfet_01v8_hvt/nfet_01v8 with phighvt/nshort """ + # TODO: figure out how to rename the devices to pass Calibre LVS setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) cdl_old_path = setting_dir / 'libs.ref' / self.library_name / 'cdl' / f'{self.library_name}.cdl' @@ -88,6 +89,26 @@ def setup_cdl(self) -> None: f_new.write(line) f_old.close() f_new.close() + + def setup_verilog(self) -> None: + """ Copy and hack the verilog """ + setting_dir = self.get_setting("technology.sky130.sky130A") + setting_dir = Path(setting_dir) + verilog_old_path = setting_dir / 'libs.ref' / self.library_name / 'verilog' / f'{self.library_name}.v' + if not verilog_old_path.exists(): + raise FileNotFoundError(f"Verilog not found: {verilog_old_path}") + + cache_tech_dir_path = Path(self.cache_dir) + os.makedirs(cache_tech_dir_path, exist_ok=True) + verilog_new_path = cache_tech_dir_path / f'{self.library_name}.v' + + f_old = open(verilog_old_path,'r') + f_new = open(verilog_new_path,'w') + for line in f_old: + line = line.replace('wire 1','// wire 1') + f_new.write(line) + f_old.close() + f_new.close() def setup_techlef(self) -> None: """ Copy and hack the tech-lef, adding this very important `licon` section """ @@ -110,16 +131,16 @@ def setup_techlef(self) -> None: f_old.close() f_new.close() - def setup_layermap(self) -> None: - """ Copy the layer-map into `self.cache_dir` """ - nda_dir = self.get_setting("technology.sky130.sky130_nda") - nda_dir = Path(nda_dir) - layermap = nda_dir / "s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap" - if not layermap.exists(): - raise FileNotFoundError(f"Layer-map not found: {layermap}") - cache_path = Path(self.cache_dir) - os.makedirs(cache_path, exist_ok=True) - shutil.copy(layermap, cache_path) + # def setup_layermap(self) -> None: + # """ Copy the layer-map into `self.cache_dir` """ + # nda_dir = self.get_setting("technology.sky130.sky130_nda") + # nda_dir = Path(nda_dir) + # layermap = nda_dir / "s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap" + # if not layermap.exists(): + # raise FileNotFoundError(f"Layer-map not found: {layermap}") + # cache_path = Path(self.cache_dir) + # os.makedirs(cache_path, exist_ok=True) + # shutil.copy(layermap, cache_path) def setup_lvs_deck(self) -> None: """Remove conflicting specification statements found in PDK LVS decks.""" @@ -142,7 +163,7 @@ def setup_lvs_deck(self) -> None: self.logger.info("Modifying LVS deck: {} -> {}".format (source_path, dest_path)) df.write(matcher.sub("", sf.read())) - df.write(LVS_DECK_INSERT_LINES) + # df.write(LVS_DECK_INSERT_LINES) def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ @@ -151,10 +172,6 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), HammerTool.make_post_insertion_hook("place_opt_design", sky130_add_tieoffs), HammerTool.make_pre_insertion_hook("write_design", sky130_connect_nets), - #HammerTool.make_replacement_hook("power_straps", intech22_innovus.intech22_reference_power_straps), - # HammerTool.make_post_insertion_hook("power_straps", intech22_innovus.intech22_m2_staples), - # HammerTool.make_pre_insertion_hook("clock_tree", intech22_innovus.intech22_cts_options), - # HammerTool.make_replacement_hook("add_fillers", intech22_innovus.intech22_add_fillers), ]} return hooks.get(tool_name, []) @@ -178,11 +195,25 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: LVS_DECK_INSERT_LINES = ''' LVS FILTER D OPEN SOURCE LVS FILTER D OPEN LAYOUT - ''' + # TODO: black boxing sram is temporary!! for name in SKY130Tech.openram_sram_names(): LVS_DECK_INSERT_LINES += f"LVS BOX {name} \n" + LVS_DECK_INSERT_LINES += f"LVS FILTER {name} OPEN \n" + +# EXCLUDE CELL sky130_sram_1kbyte_1rw1r_32x256_8 +# EXCLUDE CELL sky130_sram_1kbyte_1rw1r_8x1024_8 +# EXCLUDE CELL sky130_sram_2kbyte_1rw1r_32x512_8 + +# LVS BOX sky130_sram_1kbyte_1rw1r_32x256_8 +# LVS BOX sky130_sram_1kbyte_1rw1r_8x1024_8 +# LVS BOX sky130_sram_2kbyte_1rw1r_32x512_8 + +# LVS FILTER sky130_sram_1kbyte_1rw1r_32x256_8 OPEN +# LVS FILTER sky130_sram_1kbyte_1rw1r_8x1024_8 OPEN +# LVS FILTER sky130_sram_2kbyte_1rw1r_32x512_8 OPEN + # various Innovus database settings def sky130_innovus_settings(ht: HammerTool) -> bool: @@ -192,6 +223,47 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: """Settings for every tool invocation""" ht.append( ''' + +########################################################## +# Placement attributes [get_db -category place] +########################################################## +#------------------------------------------------------------------------------- +set_db place_global_place_io_pins true + +set_db opt_honor_fences true +set_db place_detail_dpt_flow true +set_db place_detail_color_aware_legal true +set_db place_global_solver_effort high +set_db place_detail_check_cut_spacing true +set_db place_global_cong_effort high + +########################################################## +# Optimization attributes [get_db -category opt] +########################################################## +#------------------------------------------------------------------------------- + +set_db opt_fix_fanout_load true +set_db opt_clock_gate_aware false +set_db opt_area_recovery true +set_db opt_post_route_area_reclaim setup_aware +set_db opt_fix_hold_verbose true +# set_db opt_fix_hold_lib_cells "BUFFD0BWP30P140HVT BUFFD1BWP30P140HVT BUFFD2BWP30P140HVT BUFFD3BWP30P140HVT BUFFD4BWP30P140HVT BUFFD6BWP30P140HVT BUFFD8BWP30P140HVT BUFFD12BWP30P140HVT BUFFD16BWP30P140HVT BUFFD20BWP30P140HVT BUFFD24BWP30P140HVT DEL025D1BWP30P140HVT" + + +########################################################## +# Clock attributes [get_db -category cts] +########################################################## +#------------------------------------------------------------------------------- +#set_db cts_target_skew .15 +#set_db cts_target_max_transition_time .3 +#set_db cts_update_io_latency false + +# set_db cts_use_inverters true +# set_db cts_buffer_cells "clkbuf clkdlybuf4s15 clkdlybuf4s18 clkdlybuf4s25 clkdlybuf4s50" +# set_db cts_inverter_cells "clkinv clkinvlp" +# set_db cts_clock_gating_cells "CKLHQD1BWP30P140HVT CKLHQD2BWP30P140HVT CKLHQD3BWP30P140HVT CKLHQD4BWP30P140HVT CKLHQD6BWP30P140HVT CKLHQD8BWP30P140HVT CKLHQD12BWP30P140HVT CKLHQD16BWP30P140HVT CKLHQD20BWP30P140HVT CKLHQD24BWP30P140HVT CKLNQD1BWP30P140HVT CKLNQD2BWP30P140HVT CKLNQD3BWP30P140HVT CKLNQD4BWP30P140HVT CKLNQD6BWP30P140HVT CKLNQD8BWP30P140HVT CKLNQD12BWP30P140HVT CKLNQD16BWP30P140HVT CKLNQD20BWP30P140HVT CKLNQD24BWP30P140HVT" + + ########################################################## # Routing attributes [get_db -category route] ########################################################## @@ -199,6 +271,19 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: set_db route_design_antenna_diode_insertion 1 set_db route_design_antenna_cell_name "sky130_fd_sc_hd__diode_2" set_db route_design_bottom_routing_layer 2 + +set_db route_design_high_freq_search_repair true +set_db route_design_detail_post_route_spread_wire true +set_db route_design_with_si_driven true +set_db route_design_with_timing_driven true +set_db route_design_concurrent_minimize_via_count_effort high +set_db opt_consider_routing_congestion true +set_db route_design_detail_use_multi_cut_via_effort medium + +set_db cts_target_skew 0.03 +set_db cts_max_fanout 10 +set_db opt_setup_target_slack 0.10 +set_db opt_hold_target_slack 0.10 ''' ) return True @@ -235,6 +320,17 @@ def sky130_power_nets(ht: HammerTool) -> bool: ) return True +def sky130_remove_route_blockages(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "removing blockages can only run on par" + ht.append( + ''' +delete_route_blockages -layers {met1 met4} + ''' + ) + return True + # TODO: add these two functions into Hammer Innovus plugin def sky130_add_tieoffs(ht: HammerTool) -> bool: assert isinstance( diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index ac0148d08..4de5e751c 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -28,16 +28,18 @@ vlsi: # Supply voltages. # TODO: add ability to tie pin to net in Hammer Innovus plugin supplies: - power: [ {name: "VDD", pin: "VDD"}] - # {name: "VPWR", pin: "VPWR", tie: "VDD"}, - # {name: "VPB", pin: "VPB", tie: "VDD"}] - ground: [ {name: "VSS", pin: "VSS"}] - # {name: "VGND", pin: "VGND", tie: "VSS"}, - # {name: "VNB", pin: "VNB", tie: "VSS"}] + power: [ {name: "VDD", pin: "VDD"}] + {name: "VPWR", pin: "VPWR", tie: "VDD"}, + {name: "VPB", pin: "VPB" , tie: "VDD"}] + ground: [ {name: "VSS", pin: "VSS"}] + {name: "VGND", pin: "VGND", tie: "VSS"}, + {name: "VNB", pin: "VNB" , tie: "VSS"}] VDD: "1.8 V" GND: "0 V" - dont_use_list: ["*sdf*"] # Scan flops go haywire! Avoid them. + # moved these to json + # dont_use_mode: append + # dont_use_list: ["*sdf*","sky130_fd_sc_hd__probe_p_8"] # Scan flops go haywire! Avoid them. # mmmc corners config mmmc_corners: [ @@ -63,8 +65,7 @@ vlsi: bump_block_cut_layer: "via4" # Set the interval and offset for tap cells - # interval value from the eFPGA---RTL-to-GDS-with-SKY130 - tap_cell_interval: "40" + tap_cell_interval: "15" tap_cell_offset: "5" technology.core: @@ -74,7 +75,7 @@ technology.core: # Note that this is not usually stackup specific; it is based on the std cell libraries themselves std_cell_rail_layer: "met1" # This is used to provide a reference master for generating standard cells - tap_cell_rail_reference: "{sky130_fd_sc_hd__tap*}" + tap_cell_rail_reference: "sky130_fd_sc_hd__tap*" par.inputs: gds_merge: true diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 0c19cf51a..6f802e769 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -26,6 +26,7 @@ ], "gds map file": "$GDS_MAP_FILE", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "other layermap file": "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/VirtuosoOA/libs/s8phirs_10r/s8phirs_10r.layermap", "drc decks": [ { "tool name": "calibre", @@ -33,6 +34,7 @@ "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" } ], + "new additional_drc_text": "EXCLUDE CELL sky130_sram_1kbyte_1rw1r_32x256_8 \n EXCLUDE CELL sky130_sram_1kbyte_1rw1r_8x1024_8 \n EXCLUDE CELL sky130_sram_2kbyte_1rw1r_32x512_8", "additional_drc_text": "", "lvs decks": [ { @@ -42,7 +44,8 @@ "path": "tech-sky130-cache/lvsControlFile_s8" } ], - "additional_lvs_text": "", + "old additional_lvs_text": "LVS FILTER D OPEN SOURCE \n LVS FILTER D OPEN LAYOUT \n LVS BOX sky130_sram_1kbyte_1rw1r_32x256_8 \n LVS BOX sky130_sram_2kbyte_1rw1r_32x512_8", + "additional_lvs_text": "LVS FILTER D OPEN SOURCE \nLVS FILTER D OPEN LAYOUT \nLVS BOX sky130_sram_1kbyte_1rw1r_32x256_8 \nLVS BOX sky130_sram_2kbyte_1rw1r_32x512_8 \nLVS FILTER sky130_sram_1kbyte_1rw1r_32x256_8 OPEN \nLVS FILTER sky130_sram_2kbyte_1rw1r_32x512_8 OPEN", "physical only cells list": [ "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", @@ -54,7 +57,7 @@ "sky130_fd_sc_hd__fill_8", "sky130_fd_sc_hd__diode_2" ], - "dont use list": [], + "dont use list": ["*sdf*","sky130_fd_sc_hd__probe_p_8"], "special cells": [ { "cell_type": "tapcell", @@ -94,16 +97,17 @@ ] }, { - "spice file": "/tools/B/nayiri/sky130/chipyard-osci-sky130/vlsi/sky130-files/devices.cdl", + "spice file": "tech-sky130-cache/sky130-files/devices.cdl", + "verilog sim fake": "tech-sky130-cache/primitives.v", "provides": [ { - "lib_type": "technology" + "lib_type": "extra stuffs" } ] }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -125,7 +129,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -147,7 +151,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -169,7 +173,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -191,7 +195,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -213,7 +217,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -235,7 +239,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -257,7 +261,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -279,7 +283,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -301,7 +305,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -323,7 +327,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -345,7 +349,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -367,7 +371,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -389,7 +393,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -411,7 +415,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -433,7 +437,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -452,17 +456,6 @@ "vt": "RVT" } ] - }, - { - "lef file": "$SKY130A/libs.ref/sky130_fd_pr/lef/sky130_fd_pr.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_pr/cdl/sky130_fd_pr.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_pr/gds/sky130_fd_pr.gds", - "provides": [ - { - "lib_type": "primitives", - "vt": "RVT" - } - ] } ], "stackups": [ From 00696f51aced688a44a1dd9db8979d19d97b1196 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 26 Jul 2021 16:31:05 -0700 Subject: [PATCH 24/81] files to generate sky130.tech.json --- .../technology/sky130/tech-json/README | 4 + .../sky130/tech-json/beginning.json | 76 +++ .../sky130/tech-json/generate_json.py | 98 +++ .../technology/sky130/tech-json/sites.json | 6 + .../sky130/tech-json/sky130.tech.json | 585 ++++++++++++++++++ .../technology/sky130/tech-json/stackup.json | 11 + 6 files changed, 780 insertions(+) create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/README create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/beginning.json create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/generate_json.py create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/sites.json create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/stackup.json diff --git a/src/hammer-vlsi/technology/sky130/tech-json/README b/src/hammer-vlsi/technology/sky130/tech-json/README new file mode 100644 index 000000000..e42cce3f5 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/README @@ -0,0 +1,4 @@ +Make sure $HAMMER_HOME points to the Hammer install you're using with Sky130. +Then run: + >> python generate_json.py +This writes the tech json file to ./sky130.tech.json and $HAMMER_HOME/src/hammer-vlsi/technology/sky130/sky130.tech.json diff --git a/src/hammer-vlsi/technology/sky130/tech-json/beginning.json b/src/hammer-vlsi/technology/sky130/tech-json/beginning.json new file mode 100644 index 000000000..8bf75d7a5 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/beginning.json @@ -0,0 +1,76 @@ +{ + "name": "Skywater 130nm Library", + "grid_unit": "0.001", + "time_unit": "1 ps", + "installs": [ + { + "path": "$SKY130_PDK", + "base var": "technology.sky130.sky130_pdk" + }, + { + "path": "$SKY130_NDA", + "base var": "technology.sky130.sky130_nda" + }, + { + "path": "$SKY130A", + "base var": "technology.sky130.sky130A" + }, + { + "path": "$GDS_MAP_FILE", + "base var": "technology.sky130.gds_map_file" + }, + { + "path": "tech-sky130-cache", + "base var": "" + } + ], + "gds map file": "$GDS_MAP_FILE", + "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "drc decks": [ + { + "tool name": "calibre", + "deck name": "all_drc", + "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" + } + ], + "additional_drc_text": "", + + "lvs decks": [ + { + "tool name": "calibre", + "deck name": "all_lvs", + "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", + "path": "tech-sky130-cache/lvsControlFile_s8" + } + ], + "additional_lvs_text": "", + + "physical only cells list": [ + "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", + "sky130_fd_sc_hd__tapvgnd_1", + "sky130_fd_sc_hd__tapvpwrvgnd_1", + "sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__diode_2" + ], + "dont use list": [], + "special cells": [ + {"cell_type": "tapcell", "name": ["sky130_fd_sc_hd__tapvpwrvgnd_1"]}, + {"cell_type": "stdfiller", "name": ["sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8"]}, + {"cell_type": "tiehilocell", "name": ["sky130_fd_sc_hd__conb_1"]} + ], + + "libraries": [ + { + "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", + "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", + "provides": [ + { + "lib_type": "technology" + } + ] + } + ] +} \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py b/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py new file mode 100644 index 000000000..135766e9f --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py @@ -0,0 +1,98 @@ +import json +import os +from pathlib import Path +data = {} + +HAMMER_HOME = os.getenv('HAMMER_HOME') +SKY130A = os.getenv('SKY130A') +JSON_PATH = os.path.join(HAMMER_HOME,'src/hammer-vlsi/technology/sky130/sky130.tech.json') + + +library='sky130_fd_sc_hd' + +with open('beginning.json', 'r') as f: + data = json.load(f) + +SKYWATER_LIBS = os.path.join('$SKY130A','libs.ref',library) +LIBRARY_PATH = os.path.join(SKY130A,'libs.ref',library,'lib') +lib_corners=os.listdir(LIBRARY_PATH) +for cornerfilename in lib_corners: + if (not (library in cornerfilename) ) : continue + if ('ccsnoise' in cornerfilename): continue + + tmp = cornerfilename.replace('.lib','__') + cornername = tmp.split('__')[1] + cornerparts = cornername.split('_') + + speed = cornerparts[0] + if (speed == 'ff'): speed = 'fast' + if (speed == 'tt'): speed = 'typical' + if (speed == 'ss'): speed = 'slow' + + temp = cornerparts[1] + temp = temp.replace('n','-') + temp = temp.split('C')[0]+' C' + + vdd = cornerparts[2] + vdd = vdd.split('v') + vdd = vdd[0]+'.'+vdd[1]+' V' + + lib_entry = { + "nldm liberty file": os.path.join(SKYWATER_LIBS,'lib', cornerfilename), + "verilog sim": os.path.join(SKYWATER_LIBS,'verilog', library+'.v'), + # maybe this instead: + # "verilog sim": os.path.join('tech-sky130-cache', library+'.v'), + "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), + "spice file": os.path.join('tech-sky130-cache', library+'.cdl'), + "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), + "corner": { + "nmos": speed, + "pmos": speed, + "temperature": temp + }, + "supplies": { + "VDD": vdd, + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + } + + data["libraries"].append(lib_entry) + +stackups = {} +with open('stackup.json', 'r') as f: + stackups = json.load(f) +stackups["name"] = library +data["stackups"] = [stackups] + +library='sky130_fd_pr' +SKYWATER_LIBS=os.path.join('$SKY130A',"libs.ref",library) +lib_entry = { + "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), + "spice file": os.path.join(SKYWATER_LIBS,'cdl', library+'.cdl'), + "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), + "provides": [ + { + "lib_type": "primitives", + "vt": "RVT" + } + ] +} + +data["libraries"].append(lib_entry) + +sites = {} +with open('sites.json', 'r') as f: + sites = json.load(f) +data["sites"] = sites["sites"] + +with open('sky130.tech.json', 'w') as f: + json.dump(data, f, indent=2) + +# with open(os.path.join(JSON_PATH), 'w') as f: +# json.dump(data, f, indent=2) \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/tech-json/sites.json b/src/hammer-vlsi/technology/sky130/tech-json/sites.json new file mode 100644 index 000000000..e243250cb --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/sites.json @@ -0,0 +1,6 @@ +{ + "sites": [ + {"name": "unithd", "x": 0.46, "y": 2.72}, + {"name": "unithddbl", "x": 0.46, "y": 5.44} + ] +} \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json b/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json new file mode 100644 index 000000000..f244ff46e --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json @@ -0,0 +1,585 @@ +{ + "name": "Skywater 130nm Library", + "grid_unit": "0.001", + "time_unit": "1 ps", + "installs": [ + { + "path": "$SKY130_PDK", + "base var": "technology.sky130.sky130_pdk" + }, + { + "path": "$SKY130_NDA", + "base var": "technology.sky130.sky130_nda" + }, + { + "path": "$SKY130A", + "base var": "technology.sky130.sky130A" + }, + { + "path": "$GDS_MAP_FILE", + "base var": "technology.sky130.gds_map_file" + }, + { + "path": "tech-sky130-cache", + "base var": "" + } + ], + "gds map file": "$GDS_MAP_FILE", + "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "drc decks": [ + { + "tool name": "calibre", + "deck name": "all_drc", + "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" + } + ], + "additional_drc_text": "", + "lvs decks": [ + { + "tool name": "calibre", + "deck name": "all_lvs", + "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", + "path": "tech-sky130-cache/lvsControlFile_s8" + } + ], + "additional_lvs_text": "", + "physical only cells list": [ + "sky130_fd_sc_hd__tap_1", + "sky130_fd_sc_hd__tap_2", + "sky130_fd_sc_hd__tapvgnd_1", + "sky130_fd_sc_hd__tapvpwrvgnd_1", + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__diode_2" + ], + "dont use list": [], + "special cells": [ + { + "cell_type": "tapcell", + "name": [ + "sky130_fd_sc_hd__tapvpwrvgnd_1" + ] + }, + { + "cell_type": "stdfiller", + "name": [ + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", + "sky130_fd_sc_hd__decap_3", + "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", + "sky130_fd_sc_hd__decap_8" + ] + }, + { + "cell_type": "tiehilocell", + "name": [ + "sky130_fd_sc_hd__conb_1" + ] + } + ], + "libraries": [ + { + "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", + "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", + "provides": [ + { + "lib_type": "technology" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.65 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.95 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.56 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.65 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.76 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.95 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.40 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.60 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.28 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.35 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.40 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.44 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.60 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.76 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "typical", + "pmos": "typical", + "temperature": "025 C" + }, + "supplies": { + "VDD": "1.80 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "typical", + "pmos": "typical", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.80 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "lef file": "$SKY130A/libs.ref/sky130_fd_pr/lef/sky130_fd_pr.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_pr/cdl/sky130_fd_pr.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_pr/gds/sky130_fd_pr.gds", + "provides": [ + { + "lib_type": "primitives", + "vt": "RVT" + } + ] + } + ], + "stackups": [ + { + "name": "sky130_fd_sc_hd", + "metals": [ + { + "name": "li1", + "index": 1, + "direction": "vertical", + "min_width": 0.17, + "max_width": 2147483.647, + "pitch": 0.34, + "offset": 0.23, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.17 + } + ] + }, + { + "name": "met1", + "index": 2, + "direction": "horizontal", + "min_width": 0.14, + "max_width": 2147483.647, + "pitch": 0.28, + "offset": 0.17, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.14 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.28 + } + ] + }, + { + "name": "met2", + "index": 3, + "direction": "vertical", + "min_width": 0.14, + "max_width": 2147483.647, + "pitch": 0.28, + "offset": 0.23, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.14 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.28 + } + ] + }, + { + "name": "met3", + "index": 4, + "direction": "horizontal", + "min_width": 0.3, + "max_width": 2147483.647, + "pitch": 0.6, + "offset": 0.34, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.3 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.4 + } + ] + }, + { + "name": "met4", + "index": 5, + "direction": "vertical", + "min_width": 0.3, + "max_width": 2147483.647, + "pitch": 0.6, + "offset": 0.46, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.3 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.4 + } + ] + }, + { + "name": "met5", + "index": 6, + "direction": "horizontal", + "min_width": 1.6, + "max_width": 2147483.647, + "pitch": 3.2, + "offset": 1.7, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 1.6 + } + ] + } + ] + } + ], + "sites": [ + { + "name": "unithd", + "x": 0.46, + "y": 2.72 + }, + { + "name": "unithddbl", + "x": 0.46, + "y": 5.44 + } + ] +} \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/tech-json/stackup.json b/src/hammer-vlsi/technology/sky130/tech-json/stackup.json new file mode 100644 index 000000000..13914d9d8 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/stackup.json @@ -0,0 +1,11 @@ + { + "name" : "TODO", + "metals": [ + {"name": "li1", "index": 1, "direction": "vertical", "min_width": 0.17, "max_width": 2147483.647, "pitch": 0.34, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.17}]}, + {"name": "met1", "index": 2, "direction": "horizontal", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.17, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, + {"name": "met2", "index": 3, "direction": "vertical", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, + {"name": "met3", "index": 4, "direction": "horizontal", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.34, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, + {"name": "met4", "index": 5, "direction": "vertical", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.46, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, + {"name": "met5", "index": 6, "direction": "horizontal", "min_width": 1.6, "max_width": 2147483.647, "pitch": 3.2, "offset": 1.7, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 1.6}]} + ] + } From 376af40ae60e9f31b909777cf8f2ba1693c4bcee Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 29 Jul 2021 14:54:40 -0700 Subject: [PATCH 25/81] last sky130 plugin tweaks --- src/hammer-vlsi/technology/sky130/__init__.py | 16 ++-------------- src/hammer-vlsi/technology/sky130/defaults.yml | 4 ++-- 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index f5778840c..0876047c6 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -66,7 +66,6 @@ def setup_sram_cdl(self) -> None: line = line.replace('sky130_fd_pr__nfet_01v8','nshort') f_new.write(line) - # Tech setup steps def setup_cdl(self) -> None: """ Copy and hack the cdl, replacing pfet_01v8_hvt/nfet_01v8 with phighvt/nshort """ @@ -131,17 +130,6 @@ def setup_techlef(self) -> None: f_old.close() f_new.close() - # def setup_layermap(self) -> None: - # """ Copy the layer-map into `self.cache_dir` """ - # nda_dir = self.get_setting("technology.sky130.sky130_nda") - # nda_dir = Path(nda_dir) - # layermap = nda_dir / "s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap" - # if not layermap.exists(): - # raise FileNotFoundError(f"Layer-map not found: {layermap}") - # cache_path = Path(self.cache_dir) - # os.makedirs(cache_path, exist_ok=True) - # shutil.copy(layermap, cache_path) - def setup_lvs_deck(self) -> None: """Remove conflicting specification statements found in PDK LVS decks.""" pattern = '.*({}).*\n'.format('|'.join(LVS_DECK_SCRUB_LINES)) @@ -163,7 +151,7 @@ def setup_lvs_deck(self) -> None: self.logger.info("Modifying LVS deck: {} -> {}".format (source_path, dest_path)) df.write(matcher.sub("", sf.read())) - # df.write(LVS_DECK_INSERT_LINES) + df.write(LVS_DECK_INSERT_LINES) def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ @@ -290,7 +278,7 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: -# reference: /tools/commercial/skywater/swtech130/skywater-src-nda/scs8hd/V0.0.2/scripts +# from NDA scripts def sky130_add_endcaps(ht: HammerTool) -> bool: assert isinstance( ht, HammerPlaceAndRouteTool diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index 4de5e751c..c30dc942c 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -28,10 +28,10 @@ vlsi: # Supply voltages. # TODO: add ability to tie pin to net in Hammer Innovus plugin supplies: - power: [ {name: "VDD", pin: "VDD"}] + power: [ {name: "VDD", pin: "VDD"}, {name: "VPWR", pin: "VPWR", tie: "VDD"}, {name: "VPB", pin: "VPB" , tie: "VDD"}] - ground: [ {name: "VSS", pin: "VSS"}] + ground: [ {name: "VSS", pin: "VSS"}, {name: "VGND", pin: "VGND", tie: "VSS"}, {name: "VNB", pin: "VNB" , tie: "VSS"}] VDD: "1.8 V" From 430cee9606d2403eed5770f0f9030e7d042f3a1c Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 30 Jul 2021 15:31:51 -0700 Subject: [PATCH 26/81] changed underscore to dash in name --- .../technology/sky130/tech-json/README | 2 +- .../sky130/tech-json/generate-json.py | 98 +++++++++++++++++++ 2 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/generate-json.py diff --git a/src/hammer-vlsi/technology/sky130/tech-json/README b/src/hammer-vlsi/technology/sky130/tech-json/README index e42cce3f5..b7c6df966 100644 --- a/src/hammer-vlsi/technology/sky130/tech-json/README +++ b/src/hammer-vlsi/technology/sky130/tech-json/README @@ -1,4 +1,4 @@ Make sure $HAMMER_HOME points to the Hammer install you're using with Sky130. Then run: - >> python generate_json.py + >> python generate-json.py This writes the tech json file to ./sky130.tech.json and $HAMMER_HOME/src/hammer-vlsi/technology/sky130/sky130.tech.json diff --git a/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py b/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py new file mode 100644 index 000000000..135766e9f --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py @@ -0,0 +1,98 @@ +import json +import os +from pathlib import Path +data = {} + +HAMMER_HOME = os.getenv('HAMMER_HOME') +SKY130A = os.getenv('SKY130A') +JSON_PATH = os.path.join(HAMMER_HOME,'src/hammer-vlsi/technology/sky130/sky130.tech.json') + + +library='sky130_fd_sc_hd' + +with open('beginning.json', 'r') as f: + data = json.load(f) + +SKYWATER_LIBS = os.path.join('$SKY130A','libs.ref',library) +LIBRARY_PATH = os.path.join(SKY130A,'libs.ref',library,'lib') +lib_corners=os.listdir(LIBRARY_PATH) +for cornerfilename in lib_corners: + if (not (library in cornerfilename) ) : continue + if ('ccsnoise' in cornerfilename): continue + + tmp = cornerfilename.replace('.lib','__') + cornername = tmp.split('__')[1] + cornerparts = cornername.split('_') + + speed = cornerparts[0] + if (speed == 'ff'): speed = 'fast' + if (speed == 'tt'): speed = 'typical' + if (speed == 'ss'): speed = 'slow' + + temp = cornerparts[1] + temp = temp.replace('n','-') + temp = temp.split('C')[0]+' C' + + vdd = cornerparts[2] + vdd = vdd.split('v') + vdd = vdd[0]+'.'+vdd[1]+' V' + + lib_entry = { + "nldm liberty file": os.path.join(SKYWATER_LIBS,'lib', cornerfilename), + "verilog sim": os.path.join(SKYWATER_LIBS,'verilog', library+'.v'), + # maybe this instead: + # "verilog sim": os.path.join('tech-sky130-cache', library+'.v'), + "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), + "spice file": os.path.join('tech-sky130-cache', library+'.cdl'), + "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), + "corner": { + "nmos": speed, + "pmos": speed, + "temperature": temp + }, + "supplies": { + "VDD": vdd, + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + } + + data["libraries"].append(lib_entry) + +stackups = {} +with open('stackup.json', 'r') as f: + stackups = json.load(f) +stackups["name"] = library +data["stackups"] = [stackups] + +library='sky130_fd_pr' +SKYWATER_LIBS=os.path.join('$SKY130A',"libs.ref",library) +lib_entry = { + "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), + "spice file": os.path.join(SKYWATER_LIBS,'cdl', library+'.cdl'), + "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), + "provides": [ + { + "lib_type": "primitives", + "vt": "RVT" + } + ] +} + +data["libraries"].append(lib_entry) + +sites = {} +with open('sites.json', 'r') as f: + sites = json.load(f) +data["sites"] = sites["sites"] + +with open('sky130.tech.json', 'w') as f: + json.dump(data, f, indent=2) + +# with open(os.path.join(JSON_PATH), 'w') as f: +# json.dump(data, f, indent=2) \ No newline at end of file From 7f9b9729918fcfb1943232d4a30d2a85e546ceff Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 30 Jul 2021 15:32:49 -0700 Subject: [PATCH 27/81] changed underscore to dash in name --- .../sky130/tech-json/generate_json.py | 98 ------------------- 1 file changed, 98 deletions(-) delete mode 100644 src/hammer-vlsi/technology/sky130/tech-json/generate_json.py diff --git a/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py b/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py deleted file mode 100644 index 135766e9f..000000000 --- a/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py +++ /dev/null @@ -1,98 +0,0 @@ -import json -import os -from pathlib import Path -data = {} - -HAMMER_HOME = os.getenv('HAMMER_HOME') -SKY130A = os.getenv('SKY130A') -JSON_PATH = os.path.join(HAMMER_HOME,'src/hammer-vlsi/technology/sky130/sky130.tech.json') - - -library='sky130_fd_sc_hd' - -with open('beginning.json', 'r') as f: - data = json.load(f) - -SKYWATER_LIBS = os.path.join('$SKY130A','libs.ref',library) -LIBRARY_PATH = os.path.join(SKY130A,'libs.ref',library,'lib') -lib_corners=os.listdir(LIBRARY_PATH) -for cornerfilename in lib_corners: - if (not (library in cornerfilename) ) : continue - if ('ccsnoise' in cornerfilename): continue - - tmp = cornerfilename.replace('.lib','__') - cornername = tmp.split('__')[1] - cornerparts = cornername.split('_') - - speed = cornerparts[0] - if (speed == 'ff'): speed = 'fast' - if (speed == 'tt'): speed = 'typical' - if (speed == 'ss'): speed = 'slow' - - temp = cornerparts[1] - temp = temp.replace('n','-') - temp = temp.split('C')[0]+' C' - - vdd = cornerparts[2] - vdd = vdd.split('v') - vdd = vdd[0]+'.'+vdd[1]+' V' - - lib_entry = { - "nldm liberty file": os.path.join(SKYWATER_LIBS,'lib', cornerfilename), - "verilog sim": os.path.join(SKYWATER_LIBS,'verilog', library+'.v'), - # maybe this instead: - # "verilog sim": os.path.join('tech-sky130-cache', library+'.v'), - "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), - "spice file": os.path.join('tech-sky130-cache', library+'.cdl'), - "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), - "corner": { - "nmos": speed, - "pmos": speed, - "temperature": temp - }, - "supplies": { - "VDD": vdd, - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - } - - data["libraries"].append(lib_entry) - -stackups = {} -with open('stackup.json', 'r') as f: - stackups = json.load(f) -stackups["name"] = library -data["stackups"] = [stackups] - -library='sky130_fd_pr' -SKYWATER_LIBS=os.path.join('$SKY130A',"libs.ref",library) -lib_entry = { - "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), - "spice file": os.path.join(SKYWATER_LIBS,'cdl', library+'.cdl'), - "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), - "provides": [ - { - "lib_type": "primitives", - "vt": "RVT" - } - ] -} - -data["libraries"].append(lib_entry) - -sites = {} -with open('sites.json', 'r') as f: - sites = json.load(f) -data["sites"] = sites["sites"] - -with open('sky130.tech.json', 'w') as f: - json.dump(data, f, indent=2) - -# with open(os.path.join(JSON_PATH), 'w') as f: -# json.dump(data, f, indent=2) \ No newline at end of file From 127fc41728221b20df9955e3c42858c1e6376cdf Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 13 May 2021 08:01:34 -0700 Subject: [PATCH 28/81] sky130 plugin files --- src/hammer-vlsi/technology/sky130/__init__.py | 231 ++++++++++++++++++ 1 file changed, 231 insertions(+) create mode 100644 src/hammer-vlsi/technology/sky130/__init__.py diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py new file mode 100644 index 000000000..087302fb7 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -0,0 +1,231 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Skywater plugin for Hammer. +# +# See LICENSE for licence details. + +import sys +import re +import os +#import tempfile +import shutil +#from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any + +from hammer_tech import HammerTechnology +from hammer_vlsi import HammerTool, HammerPlaceAndRouteTool, TCLTool, HammerToolHookAction + +class SkywaterTech(HammerTechnology): + """ + Override the HammerTechnology used in `hammer_tech.py` + This class is loaded by function `load_from_json`, and will pass the `try` in `importlib`. + """ + def post_install_script(self) -> None: + try: + import gdspy # type: ignore + except ImportError: + self.logger.error("Couldn't import gdspy Python package, needed to merge Skywater gds.") + shutil.rmtree(self.cache_dir) + sys.exit() + # make cache directories for all necessary lib files + #dirs = 'cdl gds lef lib verilog/models'.split() + dir = 'gds'#for dir in dirs: + os.makedirs(os.path.join(self.cache_dir,dir), exist_ok=True) + # make models dirs in parse_models function + + # useful paths/values + base_dir = self.get_setting("technology.sky130.skywater_pdk") + libraries = os.listdir(base_dir+'/libraries/') + library = 'sky130_fd_sc_hd' + libs_path = base_dir+'/libraries/' + lib_path = libs_path+library+'/latest/' + cells = os.listdir(lib_path+'/cells') + + self.combine_gds(lib_path,library,cells) + #self.combine_lef(lib_path,library,cells) + #self.combine_verilog(lib_path,library,cells) + #self.parse_models(lib_path,library) + #self.combine_cdl(lib_path,library,cells) + #self.lib_setup(lib_path,library) + + def lib_setup(self,lib_path,library) -> None: + # set up file + corners = os.listdir(os.path.join(lib_path,'timing')) + # find ccsnoise corners + ccsnoise_corners = [] + for corner in corners: + if corner.endswith('_ccsnoise.lib'): + corner = corner.replace('_ccsnoise','') + ccsnoise_corners.append(corner) + for corner in corners: + if corner.endswith('_ccsnoise.lib'): + continue + # remove ccsnoise info + if corner in ccsnoise_corners: + f = open(os.path.join(self.cache_dir,'lib',corner), 'w') + lib_file = open(os.path.join(lib_path,'timing',corner),'r') + count = 0; # count brackets :( + ccsn = False + for line in lib_file: + if ( ('ccsn_first_stage' in line) or ('ccsn_last_stage' in line) ): + ccsn = True + if (not ccsn): + f.write(line) + else: + count = count + line.count('{') + count = count - line.count('}') + if count == 0: + ccsn = False + f.close() + # copy rest of lib files to tech cache + elif corner.endswith('.lib'): + shutil.copyfile(os.path.join(lib_path,'timing',corner),os.path.join(self.cache_dir,'lib',corner)) + + def combine_gds(self,lib_path,library,cells) -> None: + import gdspy + # create new gds lib + gds_lib = gdspy.GdsLibrary() + # iterate over all cells + for cell in cells: + cell_path = os.path.join(lib_path,'cells',cell) + cell_files = os.listdir(cell_path) + # iterate over all gds files for each cell + for cell_file in cell_files: + if cell_file.endswith('.gds'): + cell_gds_path = os.path.join(cell_path,cell_file) + # import gds file into gds library + cell_gds = gds_lib.read_gds(cell_gds_path) + gds_lib_path = os.path.join(self.cache_dir,'gds',library+'.gds') + gds_lib.write_gds(gds_lib_path) + + def combine_lef(self,lib_path,library,cells) -> None: + # set up file + f = open(os.path.join(self.cache_dir,"lef",library+".lef"), "w") + f.write('VERSION 5.6 ;\nNAMESCASESENSITIVE ON ;\nBUSBITCHARS "[]" ;\nDIVIDERCHAR "/" ;\n\n') + # iterate over cells + for cell in cells: + cell_path = os.path.join(lib_path,'cells',cell) + cell_files = os.listdir(cell_path) + for cell_file in cell_files: + if cell_file.endswith('.lef') and not cell_file.endswith('magic.lef'): + cell_file = open(os.path.join(cell_path,cell_file),"r") + writing=False + for line in cell_file: + if line.startswith("END LIBRARY"): + f.write('\n\n') + break + if line.startswith("MACRO"): + writing=True + if writing: + f.write(line) + f.close() + + def combine_verilog2(self,lib_path,library,cells) -> None: + # set up file + f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") + #f.write('`define UNIT_DELAY \n') # WHERE TF IS THIS DEFINED IN PDK?!?!?! + # include udp models + models = os.listdir(os.path.join(lib_path,'models')) + for model in models: + model_path = os.path.join(self.cache_dir,'verilog','models',library+'__'+model+'.v') + f.write('`include "'+model_path+'"\n') + # iterate over cells + for cell in cells: + cell_path = os.path.join(lib_path,'cells',cell) + cell_files = os.listdir(cell_path) + for cell_file in cell_files: + if cell_file.endswith('.behavioral.v') or \ + ( cell_file.endswith('.v') and cell_file.startswith(library+'__'+cell+'_') ): + cell_file = open(os.path.join(cell_path,cell_file),"r") + f.write('\n\n') # separate modules + for line in cell_file: + # edit these lines + if line.startswith('`default_nettype none\n'): + line = line.replace('none','wire') + # skip these lines + if '*' in line: continue # comments + if line.startswith('`include'): continue # unnecessary imports + if ('wire 1' in line): continue # dunno why this is in some verilog files + + f.write(line) + f.close() + + def combine_verilog(self,lib_path,library,cells) -> None: + # set up file + f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") + #f.write('`define UNIT_DELAY \n') # WHERE TF IS THIS DEFINED IN PDK?!?!?! + # include udp models + models = os.listdir(os.path.join(lib_path,'models')) + for model in models: + model_path = os.path.join(self.cache_dir,'verilog','models',library+'__'+model+'.blackbox.v') + f.write('`include "'+model_path+'"\n') + # iterate over cells + for cell in cells: + cell_path = os.path.join(lib_path,'cells',cell) + cell_files = os.listdir(cell_path) + for cell_file in cell_files: + if cell_file.endswith('.behavioral.v') or \ + ( cell_file.endswith('.v') and cell_file.startswith(library+'__'+cell+'_') ): + cell_file = open(os.path.join(cell_path,cell_file),"r") + f.write('\n\n') # separate modules + for line in cell_file: + # edit these lines + if line.startswith('`default_nettype none\n'): + line = line.replace('none','wire') + # skip these lines + if '*' in line: continue # comments + if line.startswith('`include'): continue # unnecessary imports + if ('wire 1' in line): continue # dunno why this is in some verilog files + + f.write(line) + f.close() + def parse_models(self,lib_path,library) -> None: + model_path = os.path.join(lib_path,'models') + models = os.listdir(model_path) + for model in models: + cache_model_path = os.path.join(self.cache_dir,'verilog','models') + model_filename = library+'__'+model+'.blackbox.v' + f = open(os.path.join(cache_model_path,model_filename),'w') + model_file = open(os.path.join(model_path,model,model_filename)) + for line in model_file: + if line.startswith("`default_nettype none"): + line = line.replace('none','wire') + f.write(line) + f.close() + def parse_models2(self,lib_path,library) -> None: + model_path = os.path.join(lib_path,'models') + models = os.listdir(model_path) + for model in models: + cache_model_path = os.path.join(self.cache_dir,'verilog','models') + model_filename = library+'__'+model+'.v' + f = open(os.path.join(cache_model_path,model_filename),'w') + model_file = open(os.path.join(model_path,model,model_filename)) + for line in model_file: + if line.startswith("`default_nettype none"): + line = line.replace('none','wire') + f.write(line) + f.close() + + def combine_cdl(self,lib_path,library,cells) -> None: + # set up file + f = open(os.path.join(self.cache_dir,"cdl",library+".cdl"), "w") + # iterate over cells + for cell in cells: + cell_path = os.path.join(lib_path,'cells',cell) + cell_files = os.listdir(cell_path) + for cell_file in cell_files: + if cell_file.endswith('.cdl'): + cell_file = open(os.path.join(cell_path,cell_file),"r") + writing=False + for line in cell_file: + if line.startswith(".SUBCKT"): + writing=True + if writing: + f.write(line) + if line.startswith(".ENDS"): + f.write('\n\n') + break + f.close() + +tech = SkywaterTech() + From 3576ca92c3b790cf50d57a6c05d69829493f4521 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 13 May 2021 08:04:16 -0700 Subject: [PATCH 29/81] sky130 plugin files --- .../technology/sky130/defaults.yml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 src/hammer-vlsi/technology/sky130/defaults.yml diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml new file mode 100644 index 000000000..55def0f5c --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -0,0 +1,59 @@ +# Settings for the skywater technology to be overriden by the project. +technology.sky130: + skywater_pdk: "PATH_TO_SKYWATER_PDK" + open_pdks: "PATH_TO_OPEN_PDKS" + skywater_nda: "PATH_TO_NDA_FILES" + sram_lib: "" + +# Set some defaults for this technology. +vlsi: + # Technology dimension + core.node: 130 + inputs: + # Supply voltages. + supplies: + power: [{name: "VDD", pin: "VPWR"}] + ground: [{name: "VSS", pin: "VGND"}] + VDD: "1.8 V" + GND: "0 V" + + # mmmc corners config + mmmc_corners: [ + { + "name": "sky130_fd_sc_hd__ss_100C_1v60", + "type": "setup", + "voltage": "1.60 V", + "temp": "100 C" + }, + { + "name": "sky130_fd_sc_hd__ff_n40C_1v95", + "type": "hold", + "voltage": "1.95 V", + "temp": "-40 C" + } + ] + technology: + # Set standard cell LEF placement site + placement_site: "unithd" + + # Set the layer that blocks vias under bumps + # nk - not sure if this is right?? + bump_block_cut_layer: "via4" + + # Set the interval and offset for tap cells + # nk - not sure if this is right?? + tap_cell_interval: "27" + tap_cell_offset: "5" + +technology.core: + # This key should exist in the stackups list in the tech json + stackup: "sky130_fd_sc_hd" + # This should specify the TOPMOST metal layer the standard cells use for power rails + # Note that this is not usually stackup specific; it is based on the std cell libraries themselves + std_cell_rail_layer: "met1" + # This is used to provide a reference master for generating standard cells + tap_cell_rail_reference: "{sky130_fd_sc_hd__tap*}" + +par.inputs: + gds_merge: true + From 1e80ce22bee2e5a5b8f32d75ec40e09fc38e9db1 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 13 May 2021 08:51:58 -0700 Subject: [PATCH 30/81] adding tech json whoops --- .../technology/sky130/sky130.tech.json | 437 ++++++++++++++++++ 1 file changed, 437 insertions(+) create mode 100644 src/hammer-vlsi/technology/sky130/sky130.tech.json diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json new file mode 100644 index 000000000..2e345c061 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -0,0 +1,437 @@ +{ + "name": "Skywater 130nm Library", + "grid_unit": "0.001", + "time_unit": "1 ps", + "installs": [ + { + "path": "$SKYWATER_PDK", + "base var": "technology.sky130.skywater_pdk" + }, + { + "path": "$OPEN_PDKS", + "base var": "technology.sky130.open_pdks" + }, + { + "path": "$SKYWATER_NDA", + "base var": "technology.sky130.skywater_nda" + }, + { + "path": "tech-sky130-cache", + "base var": "" + } + ], + "gds map file": "$SKYWATER_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "drc decks": [ + { + "tool name": "calibre", + "deck name": "all_drc", + "path": "$SKYWATER_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules", + "newpath": "tech-sky130-cache/drc/s8_drcRules" + } + ], + "additional_drc_text": "", + + "lvs decks": [ + { + "tool name": "calibre", + "deck name": "all_lvs", + "path": "$SKYWATER_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8" + } + ], + "additional_lvs_text": "", + + "libraries": [ + { + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef", + "provides": [ + { + "lib_type": "technology" + } + ] + }, + + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.65 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.95 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.56 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.65 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": 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"$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.40 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": 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"stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", + "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "typical", + "pmos": "typical", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.80 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + } + ], + "stackups": [ + { + "name": "sky130_fd_sc_hd", + "metals": [ + {"name": "li1", "index": 1, "direction": "vertical", "min_width": 0.17, "max_width": 2147483.647, "pitch": 0.34, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.17}]}, + {"name": "met1", "index": 2, "direction": "horizontal", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.17, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, + {"name": "met2", "index": 3, "direction": "vertical", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, + {"name": "met3", "index": 4, "direction": "horizontal", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.34, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, + {"name": "met4", "index": 5, "direction": "vertical", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.46, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, + {"name": "met5", "index": 6, "direction": "horizontal", "min_width": 1.6, "max_width": 2147483.647, "pitch": 3.2, "offset": 1.7, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 1.6}]} + ] + } + ], + "sites": [ + {"name": "unithd", "x": 0.46, "y": 2.72}, + {"name": "unithddbl", "x": 0.46, "y": 5.44} + ], + "physical only cells list": [ + "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", + "sky130_fd_sc_hd__tapvgnd_1", + "sky130_fd_sc_hd__tapvpwrvgnd_1", + "sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8" + ], + "special cells": [ + {"cell_type": "tapcell", "name": ["sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2"]}, + {"cell_type": "stdfiller", "name": ["sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8"]} + ] +} From 66a764408a60082a82fa47d5b3d6dd7f78476807 Mon Sep 17 00:00:00 2001 From: harrisonliew Date: Thu, 13 May 2021 11:40:21 -0700 Subject: [PATCH 31/81] preliminary untested sram compiler, also changed some skywater names to sky130 --- src/hammer-vlsi/technology/sky130/__init__.py | 66 ++-- .../technology/sky130/defaults.yml | 9 +- .../technology/sky130/sky130.tech.json | 14 +- .../technology/sky130/sram-cache-gen.py | 115 +++++++ .../technology/sky130/sram-cache.json | 301 ++++++++++++++++++ .../sky130/sram_compiler/__init__.py | 97 ++++++ src/hammer-vlsi/technology/sky130/srams.txt | 10 + src/test/mypy.sh | 2 + 8 files changed, 570 insertions(+), 44 deletions(-) create mode 100755 src/hammer-vlsi/technology/sky130/sram-cache-gen.py create mode 100644 src/hammer-vlsi/technology/sky130/sram-cache.json create mode 100644 src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py create mode 100644 src/hammer-vlsi/technology/sky130/srams.txt diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 087302fb7..c017554d9 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # -# Skywater plugin for Hammer. +# SKY130 plugin for Hammer. # # See LICENSE for licence details. @@ -15,7 +15,7 @@ from hammer_tech import HammerTechnology from hammer_vlsi import HammerTool, HammerPlaceAndRouteTool, TCLTool, HammerToolHookAction -class SkywaterTech(HammerTechnology): +class SKY130Tech(HammerTechnology): """ Override the HammerTechnology used in `hammer_tech.py` This class is loaded by function `load_from_json`, and will pass the `try` in `importlib`. @@ -24,7 +24,7 @@ def post_install_script(self) -> None: try: import gdspy # type: ignore except ImportError: - self.logger.error("Couldn't import gdspy Python package, needed to merge Skywater gds.") + self.logger.error("Couldn't import gdspy Python package, needed to merge SKY130 gds.") shutil.rmtree(self.cache_dir) sys.exit() # make cache directories for all necessary lib files @@ -32,22 +32,22 @@ def post_install_script(self) -> None: dir = 'gds'#for dir in dirs: os.makedirs(os.path.join(self.cache_dir,dir), exist_ok=True) # make models dirs in parse_models function - + # useful paths/values - base_dir = self.get_setting("technology.sky130.skywater_pdk") + base_dir = self.get_setting("technology.sky130.sky130_pdk") libraries = os.listdir(base_dir+'/libraries/') library = 'sky130_fd_sc_hd' libs_path = base_dir+'/libraries/' lib_path = libs_path+library+'/latest/' cells = os.listdir(lib_path+'/cells') - + self.combine_gds(lib_path,library,cells) #self.combine_lef(lib_path,library,cells) #self.combine_verilog(lib_path,library,cells) #self.parse_models(lib_path,library) #self.combine_cdl(lib_path,library,cells) #self.lib_setup(lib_path,library) - + def lib_setup(self,lib_path,library) -> None: # set up file corners = os.listdir(os.path.join(lib_path,'timing')) @@ -80,7 +80,7 @@ def lib_setup(self,lib_path,library) -> None: # copy rest of lib files to tech cache elif corner.endswith('.lib'): shutil.copyfile(os.path.join(lib_path,'timing',corner),os.path.join(self.cache_dir,'lib',corner)) - + def combine_gds(self,lib_path,library,cells) -> None: import gdspy # create new gds lib @@ -90,14 +90,14 @@ def combine_gds(self,lib_path,library,cells) -> None: cell_path = os.path.join(lib_path,'cells',cell) cell_files = os.listdir(cell_path) # iterate over all gds files for each cell - for cell_file in cell_files: - if cell_file.endswith('.gds'): - cell_gds_path = os.path.join(cell_path,cell_file) + for cell_file_path in cell_files: + if cell_file_path.endswith('.gds'): + cell_gds_path = os.path.join(cell_path,cell_file_path) # import gds file into gds library cell_gds = gds_lib.read_gds(cell_gds_path) gds_lib_path = os.path.join(self.cache_dir,'gds',library+'.gds') gds_lib.write_gds(gds_lib_path) - + def combine_lef(self,lib_path,library,cells) -> None: # set up file f = open(os.path.join(self.cache_dir,"lef",library+".lef"), "w") @@ -106,12 +106,12 @@ def combine_lef(self,lib_path,library,cells) -> None: for cell in cells: cell_path = os.path.join(lib_path,'cells',cell) cell_files = os.listdir(cell_path) - for cell_file in cell_files: - if cell_file.endswith('.lef') and not cell_file.endswith('magic.lef'): - cell_file = open(os.path.join(cell_path,cell_file),"r") + for cell_file_path in cell_files: + if cell_file_path.endswith('.lef') and not cell_file_path.endswith('magic.lef'): + cell_file = open(os.path.join(cell_path,cell_file_path),"r") writing=False for line in cell_file: - if line.startswith("END LIBRARY"): + if line.startswith("END LIBRARY"): f.write('\n\n') break if line.startswith("MACRO"): @@ -119,7 +119,7 @@ def combine_lef(self,lib_path,library,cells) -> None: if writing: f.write(line) f.close() - + def combine_verilog2(self,lib_path,library,cells) -> None: # set up file f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") @@ -133,10 +133,10 @@ def combine_verilog2(self,lib_path,library,cells) -> None: for cell in cells: cell_path = os.path.join(lib_path,'cells',cell) cell_files = os.listdir(cell_path) - for cell_file in cell_files: - if cell_file.endswith('.behavioral.v') or \ - ( cell_file.endswith('.v') and cell_file.startswith(library+'__'+cell+'_') ): - cell_file = open(os.path.join(cell_path,cell_file),"r") + for cell_file_path in cell_files: + if cell_file_path.endswith('.behavioral.v') or \ + ( cell_file_path.endswith('.v') and cell_file_path.startswith(library+'__'+cell+'_') ): + cell_file = open(os.path.join(cell_path,cell_file_path),"r") f.write('\n\n') # separate modules for line in cell_file: # edit these lines @@ -149,7 +149,7 @@ def combine_verilog2(self,lib_path,library,cells) -> None: f.write(line) f.close() - + def combine_verilog(self,lib_path,library,cells) -> None: # set up file f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") @@ -163,10 +163,10 @@ def combine_verilog(self,lib_path,library,cells) -> None: for cell in cells: cell_path = os.path.join(lib_path,'cells',cell) cell_files = os.listdir(cell_path) - for cell_file in cell_files: - if cell_file.endswith('.behavioral.v') or \ - ( cell_file.endswith('.v') and cell_file.startswith(library+'__'+cell+'_') ): - cell_file = open(os.path.join(cell_path,cell_file),"r") + for cell_file_path in cell_files: + if cell_file_path.endswith('.behavioral.v') or \ + ( cell_file_path.endswith('.v') and cell_file_path.startswith(library+'__'+cell+'_') ): + cell_file = open(os.path.join(cell_path,cell_file_path),"r") f.write('\n\n') # separate modules for line in cell_file: # edit these lines @@ -205,7 +205,7 @@ def parse_models2(self,lib_path,library) -> None: line = line.replace('none','wire') f.write(line) f.close() - + def combine_cdl(self,lib_path,library,cells) -> None: # set up file f = open(os.path.join(self.cache_dir,"cdl",library+".cdl"), "w") @@ -213,19 +213,19 @@ def combine_cdl(self,lib_path,library,cells) -> None: for cell in cells: cell_path = os.path.join(lib_path,'cells',cell) cell_files = os.listdir(cell_path) - for cell_file in cell_files: - if cell_file.endswith('.cdl'): - cell_file = open(os.path.join(cell_path,cell_file),"r") + for cell_file_path in cell_files: + if cell_file_path.endswith('.cdl'): + cell_file = open(os.path.join(cell_path,cell_file_path),"r") writing=False for line in cell_file: if line.startswith(".SUBCKT"): writing=True if writing: f.write(line) - if line.startswith(".ENDS"): + if line.startswith(".ENDS"): f.write('\n\n') break f.close() - -tech = SkywaterTech() + +tech = SKY130Tech() diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index 55def0f5c..724120b0e 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -1,9 +1,10 @@ -# Settings for the skywater technology to be overriden by the project. +# Settings for the sky130 technology to be overriden by the project. technology.sky130: - skywater_pdk: "PATH_TO_SKYWATER_PDK" + sky130_pdk: "PATH_TO_SKY130_PDK" open_pdks: "PATH_TO_OPEN_PDKS" - skywater_nda: "PATH_TO_NDA_FILES" - sram_lib: "" + sky130_nda: "PATH_TO_NDA_FILES" + dffram_lib: "PATH_TO_DFFRAM/Compiler/build" + openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" # Set some defaults for this technology. vlsi: diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 2e345c061..97ce77222 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -4,28 +4,28 @@ "time_unit": "1 ps", "installs": [ { - "path": "$SKYWATER_PDK", - "base var": "technology.sky130.skywater_pdk" + "path": "$SKY130_PDK", + "base var": "technology.sky130.sky130_pdk" }, { "path": "$OPEN_PDKS", "base var": "technology.sky130.open_pdks" }, { - "path": "$SKYWATER_NDA", - "base var": "technology.sky130.skywater_nda" + "path": "$SKY130_NDA", + "base var": "technology.sky130.sky130_nda" }, { "path": "tech-sky130-cache", "base var": "" } ], - "gds map file": "$SKYWATER_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "gds map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { "tool name": "calibre", "deck name": "all_drc", - "path": "$SKYWATER_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules", + "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules", "newpath": "tech-sky130-cache/drc/s8_drcRules" } ], @@ -35,7 +35,7 @@ { "tool name": "calibre", "deck name": "all_lvs", - "path": "$SKYWATER_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8" + "path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8" } ], "additional_lvs_text": "", diff --git a/src/hammer-vlsi/technology/sky130/sram-cache-gen.py b/src/hammer-vlsi/technology/sky130/sram-cache-gen.py new file mode 100755 index 000000000..bc2fe903b --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sram-cache-gen.py @@ -0,0 +1,115 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Script to generate the ASAP7 dummy SRAM cache. +# +# See LICENSE for licence details. + +import sys +import re + +from typing import List + +def main(args: List[str]) -> int: + if len(args) != 3: + print("Usage: ./sram-cache-gen.py list-of-srams-1-per-line.txt output-file.json") + print("E.g.: ./sram-cache-gen.py srams.txt sram-cache.json") + return 1 + + list_of_srams = [] # type: List[str] + with open(sys.argv[1]) as f: + for line in f: + list_of_srams.append(line) + + print(str(len(list_of_srams)) + " SRAMs to cache") + + json = [] # type: List[str] + + for sram_name in list_of_srams: + # DFFRAM-generated 1-port rams + if sram_name.startswith("RAM"): + match = re.match(r"RAM(\d+)x(\d+)", sram_name) + if match: + json.append("""{{ + "type" : "sram", + "name" : "{n}", + "depth" : {d}, + "width" : {w}, + "family" : "1rw", + "mask" : "true", + "ports" : [ {{ + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + }} ], + "extra ports" : [] +}}""".format(n=sram_name.strip(), d=match.group(1), w=match.group(2))) + else: + print("Unsupported memory: {n}".format(n=sram_name), file=sys.stderr) + return 1 + # OpenRAM-generated 2-port rams + elif sram_name.startswith("sky130_sram"): + match = re.match(r"sky130_sram_(\d+)kbyte_1rw1r_(\d+)x(\d+)_(\d+)", sram_name) + if match: + json.append(""" +{{ + "type" : "sram", + "name" : "{n}", + "depth" : {d}, + "width" : {w}, + "family" : "1rw1r", + "mask" : "true", + "ports": [ {{ + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }}, {{ + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + }} ], + "extra ports" : [] +}}""".format(n=sram_name.strip(), w=match.group(2), d=match.group(3), m=match.group(4))) + else: + print("Unsupported memory: {n}".format(n=sram_name), file=sys.stderr) + return 1 + else: + print("Unsupported memory: {n}".format(n=sram_name), file=sys.stderr) + return 1 + + json_str = "[\n" + ",\n".join(json) + "]\n" + + with open(sys.argv[2], "w") as f: + f.write(json_str) + + return 0 + +if __name__ == '__main__': + sys.exit(main(sys.argv)) diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json new file mode 100644 index 000000000..b703238ec --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -0,0 +1,301 @@ +[ +{ + "type" : "sram", + "name" : "RAM8x32", + "depth" : 8, + "width" : 32, + "family" : "1rw", + "mask" : "true", + "ports" : [ { + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + } ], + "extra ports" : [] +}, +{ + "type" : "sram", + "name" : "RAM32x32", + "depth" : 32, + "width" : 32, + "family" : "1rw", + "mask" : "true", + "ports" : [ { + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + } ], + "extra ports" : [] +}, +{ + "type" : "sram", + "name" : "RAM128x32", + "depth" : 128, + "width" : 32, + "family" : "1rw", + "mask" : "true", + "ports" : [ { + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + } ], + "extra ports" : [] +}, +{ + "type" : "sram", + "name" : "RAM512x32", + "depth" : 512, + "width" : 32, + "family" : "1rw", + "mask" : "true", + "ports" : [ { + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + } ], + "extra ports" : [] +}, +{ + "type" : "sram", + "name" : "RAM2048x32", + "depth" : 2048, + "width" : 32, + "family" : "1rw", + "mask" : "true", + "ports" : [ { + "address port name" : "A", + "address port polarity" : "active high", + "clock port name" : "CLK", + "clock port polarity" : "positive edge", + "output port name" : "Do", + "output port polarity" : "active high", + "input port name" : "Di", + "input port polarity" : "active high", + "chip enable port name" : "EN", + "chip enable port polarity" : "active high", + "mask port name" : "WE", + "mask port polarity" : "active high", + "mask granularity" : 8 + } ], + "extra ports" : [] +}, + +{ + "type" : "sram", + "name" : "sky130_sram_1kbyte_1rw1r_32x256_8", + "depth" : 256, + "width" : 32, + "family" : "1rw1r", + "mask" : "true", + "ports": [ { + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }, { + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + } ], + "extra ports" : [] +}, + +{ + "type" : "sram", + "name" : "sky130_sram_1kbyte_1rw1r_8x1024_8", + "depth" : 1024, + "width" : 8, + "family" : "1rw1r", + "mask" : "true", + "ports": [ { + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }, { + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + } ], + "extra ports" : [] +}, + +{ + "type" : "sram", + "name" : "sky130_sram_2kbyte_1rw1r_32x512_8", + "depth" : 512, + "width" : 32, + "family" : "1rw1r", + "mask" : "true", + "ports": [ { + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }, { + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + } ], + "extra ports" : [] +}, + +{ + "type" : "sram", + "name" : "sky130_sram_4kbyte_1rw1r_32x1024_8", + "depth" : 1024, + "width" : 32, + "family" : "1rw1r", + "mask" : "true", + "ports": [ { + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }, { + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + } ], + "extra ports" : [] +}, + +{ + "type" : "sram", + "name" : "sky130_sram_8kbyte_1rw1r_32x2048_8", + "depth" : 2048, + "width" : 32, + "family" : "1rw1r", + "mask" : "true", + "ports": [ { + "address port name" : "addr0", + "address port polarity" : "active high", + "clock port name" : "clk0", + "clock port polarity" : "positive edge", + "write enable port name" : "web0", + "write enable port polarity" : "active low", + "output port name" : "dout0", + "output port polarity" : "active high", + "input port name" : "din0", + "input port polarity" : "active high", + "chip enable port name" : "csb0", + "chip enable port polarity" : "active low", + "mask port name" : "wmask0", + "mask port polarity" : "active high", + "mask granularity" : 8 + }, { + "address port name" : "addr1", + "address port polarity" : "active high", + "clock port name" : "clk1", + "clock port polarity" : "positive edge", + "output port name" : "dout1", + "output port polarity" : "active high", + "chip enable port name" : "csb1", + "chip enable port polarity" : "active low" + } ], + "extra ports" : [] +}] diff --git a/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py b/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py new file mode 100644 index 000000000..4abcc58ad --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py @@ -0,0 +1,97 @@ + +import os, tempfile, subprocess + +from hammer_vlsi import MMMCCorner, MMMCCornerType, HammerTool, HammerToolStep, HammerSRAMGeneratorTool, SRAMParameters +from hammer_vlsi.units import VoltageValue, TemperatureValue +from hammer_tech import Library, ExtraLibrary +from typing import NamedTuple, Dict, Any, List +from abc import ABCMeta, abstractmethod + +class SKY130SRAMGenerator(HammerSRAMGeneratorTool): + def tool_config_prefix(self) -> str: + return "sram_generator.sky130" + + def version_number(self, version: str) -> int: + return 0 + + # Run generator for a single sram and corner + def generate_sram(self, params: SRAMParameters, corner: MMMCCorner) -> ExtraLibrary: + tech_cache_dir = os.path.abspath(self.technology.cache_dir) + + #TODO: this is really an abuse of the corner stuff + if corner.type == MMMCCornerType.Setup: + speed_name = "slow" + speed = "SS" + elif corner.type == MMMCCornerType.Hold: + speed_name = "fast" + speed = "FF" + elif corner.type == MMMCCornerType.Extra: + speed_name = "typical" + speed = "TT" + + # Different target memories based on port count + if params.family == "1rw": + self.logger.info("Compiling 1rw memories to DFFRAM instances") + base_dir = self.get_setting("technology.sky130.dffram_lib") + fam_code = params.family + sram_name = "RAM{d}x{w}".format( + d=params.depth, + w=params.width) + #TODO: need real libs (perhaps run Liberate here?) + #For now, use the dummy lib for all corners + corner_str = "" # + lib_path = "{b}/{n}.lib".format( + b=base_dir, + n=sram_name) + if not os.path.exists(lib_path): + self.logger.error("SKY130 1rw1r SRAM cache does not support corner: {c}".format(c=corner_str)) + return ExtraLibrary(prefix=None, library=Library( + name=sram_name, + nldm_liberty_file=lib_path, + lef_file="{b}/{n}/{n}.lef".format(b=base_dir,n=sram_name), + #TODO: GDS not generated. Unclear which DEF to use? + #gds_file="{b}/{n}/{n}.gds".format(b=base_dir,n=sram_name), + spice_file="{b}/{n}/{n}.spice".format(b=base_dir,n=sram_name), + #TODO: Will not work as-is for behav. sim (this is a structural netlist referencing std. cells) + #Need to add std cell behavioral Verilog to sim.inputs.input_files + verilog_sim="{b}/{n}/{n}.nl.v".format(b=base_dir,n=sram_name), + corner={'nmos': speed_name, 'pmos': speed_name, 'temperature': str(corner.temp.value_in_units("C")) + " C"}, + supplies={'VDD': str(corner.voltage.value_in_units("V")) + " V", 'GND': "0 V"}, + provides=[{'lib_type': "sram", 'vt': params.vt}])) + elif params.family == "1rw1r": + self.logger.info("Compiling 1rw1r memories to OpenRAM instances") + base_dir = self.get_setting("technology.sky130.openram_lib") + fam_code = params.family + sram_name = "sky130_sram_{s}kbyte_1rw1r_{w}x{d}_{m}".format( + s=round(params.width*params.depth/8, -3)/1000, # size in kiB + w=params.width, + d=params.depth, + m=8) #TODO: Hammer SRAMParameters doesn't have this info + #TODO: replace this if OpenRAM characterization done for other corners + #For now, use typical lib for all corners + corner_str = "TT_1p8V_25C" + #corner_str = "{speed}_{volt}V_{temp}C".format( + # speed = speed, + # volt = str(corner.voltage.value_in_units("V")).replace(".","p"), + # temp = str(int(corner.temp.value_in_units("C"))).replace(".","p")) + lib_path = "{b}/{n}/{n}_{c}.lib".format( + b=base_dir, + n=sram_name, + c=corner_str) + if not os.path.exists(lib_path): + self.logger.error("SKY130 1rw1r SRAM cache does not support corner: {c}".format(c=corner_str)) + return ExtraLibrary(prefix=None, library=Library( + name=sram_name, + nldm_liberty_file=lib_path, + lef_file="{b}/{n}/{n}.lef".format(b=base_dir,n=sram_name), + gds_file="{b}/{n}/{n}.gds".format(b=base_dir,n=sram_name), + spice_file="{b}/{n}/{n}.lvs.sp".format(b=base_dir,n=sram_name), + verilog_sim="{b}/{n}/{n}.v".format(b=base_dir,n=sram_name), + corner={'nmos': speed_name, 'pmos': speed_name, 'temperature': str(corner.temp.value_in_units("C")) + " C"}, + supplies={'VDD': str(corner.voltage.value_in_units("V")) + " V", 'GND': "0 V"}, + provides=[{'lib_type': "sram", 'vt': params.vt}])) + else: + self.logger.error("SKY130 SRAM cache does not support family:{f}".format(f=params.family)) + return ExtraLibrary(prefix=None, library=None) + +tool=SKY130SRAMGenerator diff --git a/src/hammer-vlsi/technology/sky130/srams.txt b/src/hammer-vlsi/technology/sky130/srams.txt new file mode 100644 index 000000000..e1b44abbd --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/srams.txt @@ -0,0 +1,10 @@ +RAM8x32 +RAM32x32 +RAM128x32 +RAM512x32 +RAM2048x32 +sky130_sram_1kbyte_1rw1r_32x256_8 +sky130_sram_1kbyte_1rw1r_8x1024_8 +sky130_sram_2kbyte_1rw1r_32x512_8 +sky130_sram_4kbyte_1rw1r_32x1024_8 +sky130_sram_8kbyte_1rw1r_32x2048_8 diff --git a/src/test/mypy.sh b/src/test/mypy.sh index 45cd5000d..24f7923be 100755 --- a/src/test/mypy.sh +++ b/src/test/mypy.sh @@ -39,6 +39,8 @@ call_mypy ../hammer-vlsi/lvs/*.py call_mypy ../hammer-vlsi/pcb/generic/__init__.py call_mypy ../hammer-vlsi/technology/asap7/*.py call_mypy ../hammer-vlsi/technology/asap7/sram_compiler/__init__.py +call_mypy ../hammer-vlsi/technology/sky130/*.py +call_mypy ../hammer-vlsi/technology/sky130/sram_compiler/__init__.py # Tool plugins which may or may not exist if [ -f ../../../hammer-synopsys-plugins/sim/vcs/__init__.py ]; then From bb5cbe9b91dcd86d145502cf6f0e1a840e7e64c9 Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Thu, 20 May 2021 12:56:13 -0700 Subject: [PATCH 32/81] Single eFabless SRAM dual-port SRAM posing as single-port --- .../technology/sky130/sram-cache-gen.py | 4 +- .../technology/sky130/sram-cache.json | 349 +++--------------- .../sky130/sram_compiler/__init__.py | 69 ++-- src/hammer-vlsi/technology/sky130/srams.txt | 5 - 4 files changed, 87 insertions(+), 340 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/sram-cache-gen.py b/src/hammer-vlsi/technology/sky130/sram-cache-gen.py index bc2fe903b..9caf01c89 100755 --- a/src/hammer-vlsi/technology/sky130/sram-cache-gen.py +++ b/src/hammer-vlsi/technology/sky130/sram-cache-gen.py @@ -33,7 +33,7 @@ def main(args: List[str]) -> int: json.append("""{{ "type" : "sram", "name" : "{n}", - "depth" : {d}, + "depth" : "{d}", "width" : {w}, "family" : "1rw", "mask" : "true", @@ -65,7 +65,7 @@ def main(args: List[str]) -> int: {{ "type" : "sram", "name" : "{n}", - "depth" : {d}, + "depth" : "{d}", "width" : {w}, "family" : "1rw1r", "mask" : "true", diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json index b703238ec..421880750 100644 --- a/src/hammer-vlsi/technology/sky130/sram-cache.json +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -1,301 +1,50 @@ [ -{ - "type" : "sram", - "name" : "RAM8x32", - "depth" : 8, - "width" : 32, - "family" : "1rw", - "mask" : "true", - "ports" : [ { - "address port name" : "A", - "address port polarity" : "active high", - "clock port name" : "CLK", - "clock port polarity" : "positive edge", - "output port name" : "Do", - "output port polarity" : "active high", - "input port name" : "Di", - "input port polarity" : "active high", - "chip enable port name" : "EN", - "chip enable port polarity" : "active high", - "mask port name" : "WE", - "mask port polarity" : "active high", - "mask granularity" : 8 - } ], - "extra ports" : [] -}, -{ - "type" : "sram", - "name" : "RAM32x32", - "depth" : 32, - "width" : 32, - "family" : "1rw", - "mask" : "true", - "ports" : [ { - "address port name" : "A", - "address port polarity" : "active high", - "clock port name" : "CLK", - "clock port polarity" : "positive edge", - "output port name" : "Do", - "output port polarity" : "active high", - "input port name" : "Di", - "input port polarity" : "active high", - "chip enable port name" : "EN", - "chip enable port polarity" : "active high", - "mask port name" : "WE", - "mask port polarity" : "active high", - "mask granularity" : 8 - } ], - "extra ports" : [] -}, -{ - "type" : "sram", - "name" : "RAM128x32", - "depth" : 128, - "width" : 32, - "family" : "1rw", - "mask" : "true", - "ports" : [ { - "address port name" : "A", - "address port polarity" : "active high", - "clock port name" : "CLK", - "clock port polarity" : "positive edge", - "output port name" : "Do", - "output port polarity" : "active high", - "input port name" : "Di", - "input port polarity" : "active high", - "chip enable port name" : "EN", - "chip enable port polarity" : "active high", - "mask port name" : "WE", - "mask port polarity" : "active high", - "mask granularity" : 8 - } ], - "extra ports" : [] -}, -{ - "type" : "sram", - "name" : "RAM512x32", - "depth" : 512, - "width" : 32, - "family" : "1rw", - "mask" : "true", - "ports" : [ { - "address port name" : "A", - "address port polarity" : "active high", - "clock port name" : "CLK", - "clock port polarity" : "positive edge", - "output port name" : "Do", - "output port polarity" : "active high", - "input port name" : "Di", - "input port polarity" : "active high", - "chip enable port name" : "EN", - "chip enable port polarity" : "active high", - "mask port name" : "WE", - "mask port polarity" : "active high", - "mask granularity" : 8 - } ], - "extra ports" : [] -}, -{ - "type" : "sram", - "name" : "RAM2048x32", - "depth" : 2048, - "width" : 32, - "family" : "1rw", - "mask" : "true", - "ports" : [ { - "address port name" : "A", - "address port polarity" : "active high", - "clock port name" : "CLK", - "clock port polarity" : "positive edge", - "output port name" : "Do", - "output port polarity" : "active high", - "input port name" : "Di", - "input port polarity" : "active high", - "chip enable port name" : "EN", - "chip enable port polarity" : "active high", - "mask port name" : "WE", - "mask port polarity" : "active high", - "mask granularity" : 8 - } ], - "extra ports" : [] -}, - -{ - "type" : "sram", - "name" : "sky130_sram_1kbyte_1rw1r_32x256_8", - "depth" : 256, - "width" : 32, - "family" : "1rw1r", - "mask" : "true", - "ports": [ { - "address port name" : "addr0", - "address port polarity" : "active high", - "clock port name" : "clk0", - "clock port polarity" : "positive edge", - "write enable port name" : "web0", - "write enable port polarity" : "active low", - "output port name" : "dout0", - "output port polarity" : "active high", - "input port name" : "din0", - "input port polarity" : "active high", - "chip enable port name" : "csb0", - "chip enable port polarity" : "active low", - "mask port name" : "wmask0", - "mask port polarity" : "active high", - "mask granularity" : 8 - }, { - "address port name" : "addr1", - "address port polarity" : "active high", - "clock port name" : "clk1", - "clock port polarity" : "positive edge", - "output port name" : "dout1", - "output port polarity" : "active high", - "chip enable port name" : "csb1", - "chip enable port polarity" : "active low" - } ], - "extra ports" : [] -}, - -{ - "type" : "sram", - "name" : "sky130_sram_1kbyte_1rw1r_8x1024_8", - "depth" : 1024, - "width" : 8, - "family" : "1rw1r", - "mask" : "true", - "ports": [ { - "address port name" : "addr0", - "address port polarity" : "active high", - "clock port name" : "clk0", - "clock port polarity" : "positive edge", - "write enable port name" : "web0", - "write enable port polarity" : "active low", - "output port name" : "dout0", - "output port polarity" : "active high", - "input port name" : "din0", - "input port polarity" : "active high", - "chip enable port name" : "csb0", - "chip enable port polarity" : "active low", - "mask port name" : "wmask0", - "mask port polarity" : "active high", - "mask granularity" : 8 - }, { - "address port name" : "addr1", - "address port polarity" : "active high", - "clock port name" : "clk1", - "clock port polarity" : "positive edge", - "output port name" : "dout1", - "output port polarity" : "active high", - "chip enable port name" : "csb1", - "chip enable port polarity" : "active low" - } ], - "extra ports" : [] -}, - -{ - "type" : "sram", - "name" : "sky130_sram_2kbyte_1rw1r_32x512_8", - "depth" : 512, - "width" : 32, - "family" : "1rw1r", - "mask" : "true", - "ports": [ { - "address port name" : "addr0", - "address port polarity" : "active high", - "clock port name" : "clk0", - "clock port polarity" : "positive edge", - "write enable port name" : "web0", - "write enable port polarity" : "active low", - "output port name" : "dout0", - "output port polarity" : "active high", - "input port name" : "din0", - "input port polarity" : "active high", - "chip enable port name" : "csb0", - "chip enable port polarity" : "active low", - "mask port name" : "wmask0", - "mask port polarity" : "active high", - "mask granularity" : 8 - }, { - "address port name" : "addr1", - "address port polarity" : "active high", - "clock port name" : "clk1", - "clock port polarity" : "positive edge", - "output port name" : "dout1", - "output port polarity" : "active high", - "chip enable port name" : "csb1", - "chip enable port polarity" : "active low" - } ], - "extra ports" : [] -}, - -{ - "type" : "sram", - "name" : "sky130_sram_4kbyte_1rw1r_32x1024_8", - "depth" : 1024, - "width" : 32, - "family" : "1rw1r", - "mask" : "true", - "ports": [ { - "address port name" : "addr0", - "address port polarity" : "active high", - "clock port name" : "clk0", - "clock port polarity" : "positive edge", - "write enable port name" : "web0", - "write enable port polarity" : "active low", - "output port name" : "dout0", - "output port polarity" : "active high", - "input port name" : "din0", - "input port polarity" : "active high", - "chip enable port name" : "csb0", - "chip enable port polarity" : "active low", - "mask port name" : "wmask0", - "mask port polarity" : "active high", - "mask granularity" : 8 - }, { - "address port name" : "addr1", - "address port polarity" : "active high", - "clock port name" : "clk1", - "clock port polarity" : "positive edge", - "output port name" : "dout1", - "output port polarity" : "active high", - "chip enable port name" : "csb1", - "chip enable port polarity" : "active low" - } ], - "extra ports" : [] -}, - -{ - "type" : "sram", - "name" : "sky130_sram_8kbyte_1rw1r_32x2048_8", - "depth" : 2048, - "width" : 32, - "family" : "1rw1r", - "mask" : "true", - "ports": [ { - "address port name" : "addr0", - "address port polarity" : "active high", - "clock port name" : "clk0", - "clock port polarity" : "positive edge", - "write enable port name" : "web0", - "write enable port polarity" : "active low", - "output port name" : "dout0", - "output port polarity" : "active high", - "input port name" : "din0", - "input port polarity" : "active high", - "chip enable port name" : "csb0", - "chip enable port polarity" : "active low", - "mask port name" : "wmask0", - "mask port polarity" : "active high", - "mask granularity" : 8 - }, { - "address port name" : "addr1", - "address port polarity" : "active high", - "clock port name" : "clk1", - "clock port polarity" : "positive edge", - "output port name" : "dout1", - "output port polarity" : "active high", - "chip enable port name" : "csb1", - "chip enable port polarity" : "active low" - } ], - "extra ports" : [] -}] + { + "type": "sram", + "name": "sky130_sram_8kbyte_1rw1r_32x2048_8", + "depth": "2048", + "width": 32, + "family": "1rw", + "mask": "true", + "vt": "svt", + "ports": [ + { + "address port name": "addr0", + "address port polarity": "active high", + "clock port name": "clk0", + "clock port polarity": "positive edge", + "write enable port name": "web0", + "write enable port polarity": "active low", + "output port name": "dout0", + "output port polarity": "active high", + "input port name": "din0", + "input port polarity": "active high", + "chip enable port name": "csb0", + "chip enable port polarity": "active low", + "mask port name": "wmask0", + "mask port polarity": "active high", + "mask granularity": 8 + } + ], + "extra ports": [ + { + "name": "clk1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "csb1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "addr1", + "width": 11, + "type": "constant", + "value": 0 + } + ] + } +] \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py b/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py index 4abcc58ad..2283023fb 100644 --- a/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py +++ b/src/hammer-vlsi/technology/sky130/sram_compiler/__init__.py @@ -30,43 +30,46 @@ def generate_sram(self, params: SRAMParameters, corner: MMMCCorner) -> ExtraLibr speed = "TT" # Different target memories based on port count + # if params.family == "1rw": + # self.logger.info("Compiling 1rw memories to DFFRAM instances") + # base_dir = self.get_setting("technology.sky130.dffram_lib") + # fam_code = params.family + # sram_name = "RAM{d}x{w}".format( + # d=params.depth, + # w=params.width) + # #TODO: need real libs (perhaps run Liberate here?) + # #For now, use the dummy lib for all corners + # corner_str = "" # + # lib_path = "{b}/{n}.lib".format( + # b=base_dir, + # n=sram_name) + # if not os.path.exists(lib_path): + # self.logger.error("SKY130 1rw1r SRAM cache does not support corner: {c}".format(c=corner_str)) + # return ExtraLibrary(prefix=None, library=Library( + # name=sram_name, + # nldm_liberty_file=lib_path, + # lef_file="{b}/{n}/{n}.lef".format(b=base_dir,n=sram_name), + # #TODO: GDS not generated. Unclear which DEF to use? + # #gds_file="{b}/{n}/{n}.gds".format(b=base_dir,n=sram_name), + # spice_file="{b}/{n}/{n}.spice".format(b=base_dir,n=sram_name), + # #TODO: Will not work as-is for behav. sim (this is a structural netlist referencing std. cells) + # #Need to add std cell behavioral Verilog to sim.inputs.input_files + # verilog_sim="{b}/{n}/{n}.nl.v".format(b=base_dir,n=sram_name), + # corner={'nmos': speed_name, 'pmos': speed_name, 'temperature': str(corner.temp.value_in_units("C")) + " C"}, + # supplies={'VDD': str(corner.voltage.value_in_units("V")) + " V", 'GND': "0 V"}, + # provides=[{'lib_type': "sram", 'vt': params.vt}])) + # elif params.family == "1rw1r": if params.family == "1rw": - self.logger.info("Compiling 1rw memories to DFFRAM instances") - base_dir = self.get_setting("technology.sky130.dffram_lib") - fam_code = params.family - sram_name = "RAM{d}x{w}".format( - d=params.depth, - w=params.width) - #TODO: need real libs (perhaps run Liberate here?) - #For now, use the dummy lib for all corners - corner_str = "" # - lib_path = "{b}/{n}.lib".format( - b=base_dir, - n=sram_name) - if not os.path.exists(lib_path): - self.logger.error("SKY130 1rw1r SRAM cache does not support corner: {c}".format(c=corner_str)) - return ExtraLibrary(prefix=None, library=Library( - name=sram_name, - nldm_liberty_file=lib_path, - lef_file="{b}/{n}/{n}.lef".format(b=base_dir,n=sram_name), - #TODO: GDS not generated. Unclear which DEF to use? - #gds_file="{b}/{n}/{n}.gds".format(b=base_dir,n=sram_name), - spice_file="{b}/{n}/{n}.spice".format(b=base_dir,n=sram_name), - #TODO: Will not work as-is for behav. sim (this is a structural netlist referencing std. cells) - #Need to add std cell behavioral Verilog to sim.inputs.input_files - verilog_sim="{b}/{n}/{n}.nl.v".format(b=base_dir,n=sram_name), - corner={'nmos': speed_name, 'pmos': speed_name, 'temperature': str(corner.temp.value_in_units("C")) + " C"}, - supplies={'VDD': str(corner.voltage.value_in_units("V")) + " V", 'GND': "0 V"}, - provides=[{'lib_type': "sram", 'vt': params.vt}])) - elif params.family == "1rw1r": self.logger.info("Compiling 1rw1r memories to OpenRAM instances") base_dir = self.get_setting("technology.sky130.openram_lib") fam_code = params.family - sram_name = "sky130_sram_{s}kbyte_1rw1r_{w}x{d}_{m}".format( - s=round(params.width*params.depth/8, -3)/1000, # size in kiB - w=params.width, - d=params.depth, - m=8) #TODO: Hammer SRAMParameters doesn't have this info + s=round(round(params.width*params.depth/8, -3)/1000) # size in kiB + w=params.width + d=params.depth + m=8 + sram_name = f"sky130_sram_{s}kbyte_1rw1r_{w}x{d}_{m}" + print(f"SRAM_NAME: {sram_name}") + #TODO: Hammer SRAMParameters doesn't have this info #TODO: replace this if OpenRAM characterization done for other corners #For now, use typical lib for all corners corner_str = "TT_1p8V_25C" diff --git a/src/hammer-vlsi/technology/sky130/srams.txt b/src/hammer-vlsi/technology/sky130/srams.txt index e1b44abbd..1c9be4b71 100644 --- a/src/hammer-vlsi/technology/sky130/srams.txt +++ b/src/hammer-vlsi/technology/sky130/srams.txt @@ -1,8 +1,3 @@ -RAM8x32 -RAM32x32 -RAM128x32 -RAM512x32 -RAM2048x32 sky130_sram_1kbyte_1rw1r_32x256_8 sky130_sram_1kbyte_1rw1r_8x1024_8 sky130_sram_2kbyte_1rw1r_32x512_8 From 3fc9067807cae47b7e4f638cf1fa7007ee2a69f5 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 20 May 2021 10:32:17 -0700 Subject: [PATCH 33/81] tlef hack --- src/hammer-vlsi/technology/sky130/__init__.py | 237 +++--------------- .../technology/sky130/sky130.tech.json | 169 +++++++------ 2 files changed, 117 insertions(+), 289 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index c017554d9..a16181a08 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -9,9 +9,10 @@ import re import os #import tempfile -import shutil +#import shutil #from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any +import hammer_tech from hammer_tech import HammerTechnology from hammer_vlsi import HammerTool, HammerPlaceAndRouteTool, TCLTool, HammerToolHookAction @@ -21,211 +22,35 @@ class SKY130Tech(HammerTechnology): This class is loaded by function `load_from_json`, and will pass the `try` in `importlib`. """ def post_install_script(self) -> None: - try: - import gdspy # type: ignore - except ImportError: - self.logger.error("Couldn't import gdspy Python package, needed to merge SKY130 gds.") - shutil.rmtree(self.cache_dir) - sys.exit() - # make cache directories for all necessary lib files - #dirs = 'cdl gds lef lib verilog/models'.split() - dir = 'gds'#for dir in dirs: - os.makedirs(os.path.join(self.cache_dir,dir), exist_ok=True) - # make models dirs in parse_models function - - # useful paths/values - base_dir = self.get_setting("technology.sky130.sky130_pdk") - libraries = os.listdir(base_dir+'/libraries/') - library = 'sky130_fd_sc_hd' - libs_path = base_dir+'/libraries/' - lib_path = libs_path+library+'/latest/' - cells = os.listdir(lib_path+'/cells') - - self.combine_gds(lib_path,library,cells) - #self.combine_lef(lib_path,library,cells) - #self.combine_verilog(lib_path,library,cells) - #self.parse_models(lib_path,library) - #self.combine_cdl(lib_path,library,cells) - #self.lib_setup(lib_path,library) - - def lib_setup(self,lib_path,library) -> None: - # set up file - corners = os.listdir(os.path.join(lib_path,'timing')) - # find ccsnoise corners - ccsnoise_corners = [] - for corner in corners: - if corner.endswith('_ccsnoise.lib'): - corner = corner.replace('_ccsnoise','') - ccsnoise_corners.append(corner) - for corner in corners: - if corner.endswith('_ccsnoise.lib'): - continue - # remove ccsnoise info - if corner in ccsnoise_corners: - f = open(os.path.join(self.cache_dir,'lib',corner), 'w') - lib_file = open(os.path.join(lib_path,'timing',corner),'r') - count = 0; # count brackets :( - ccsn = False - for line in lib_file: - if ( ('ccsn_first_stage' in line) or ('ccsn_last_stage' in line) ): - ccsn = True - if (not ccsn): - f.write(line) - else: - count = count + line.count('{') - count = count - line.count('}') - if count == 0: - ccsn = False - f.close() - # copy rest of lib files to tech cache - elif corner.endswith('.lib'): - shutil.copyfile(os.path.join(lib_path,'timing',corner),os.path.join(self.cache_dir,'lib',corner)) - - def combine_gds(self,lib_path,library,cells) -> None: - import gdspy - # create new gds lib - gds_lib = gdspy.GdsLibrary() - # iterate over all cells - for cell in cells: - cell_path = os.path.join(lib_path,'cells',cell) - cell_files = os.listdir(cell_path) - # iterate over all gds files for each cell - for cell_file_path in cell_files: - if cell_file_path.endswith('.gds'): - cell_gds_path = os.path.join(cell_path,cell_file_path) - # import gds file into gds library - cell_gds = gds_lib.read_gds(cell_gds_path) - gds_lib_path = os.path.join(self.cache_dir,'gds',library+'.gds') - gds_lib.write_gds(gds_lib_path) - - def combine_lef(self,lib_path,library,cells) -> None: - # set up file - f = open(os.path.join(self.cache_dir,"lef",library+".lef"), "w") - f.write('VERSION 5.6 ;\nNAMESCASESENSITIVE ON ;\nBUSBITCHARS "[]" ;\nDIVIDERCHAR "/" ;\n\n') - # iterate over cells - for cell in cells: - cell_path = os.path.join(lib_path,'cells',cell) - cell_files = os.listdir(cell_path) - for cell_file_path in cell_files: - if cell_file_path.endswith('.lef') and not cell_file_path.endswith('magic.lef'): - cell_file = open(os.path.join(cell_path,cell_file_path),"r") - writing=False - for line in cell_file: - if line.startswith("END LIBRARY"): - f.write('\n\n') - break - if line.startswith("MACRO"): - writing=True - if writing: - f.write(line) - f.close() - - def combine_verilog2(self,lib_path,library,cells) -> None: - # set up file - f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") - #f.write('`define UNIT_DELAY \n') # WHERE TF IS THIS DEFINED IN PDK?!?!?! - # include udp models - models = os.listdir(os.path.join(lib_path,'models')) - for model in models: - model_path = os.path.join(self.cache_dir,'verilog','models',library+'__'+model+'.v') - f.write('`include "'+model_path+'"\n') - # iterate over cells - for cell in cells: - cell_path = os.path.join(lib_path,'cells',cell) - cell_files = os.listdir(cell_path) - for cell_file_path in cell_files: - if cell_file_path.endswith('.behavioral.v') or \ - ( cell_file_path.endswith('.v') and cell_file_path.startswith(library+'__'+cell+'_') ): - cell_file = open(os.path.join(cell_path,cell_file_path),"r") - f.write('\n\n') # separate modules - for line in cell_file: - # edit these lines - if line.startswith('`default_nettype none\n'): - line = line.replace('none','wire') - # skip these lines - if '*' in line: continue # comments - if line.startswith('`include'): continue # unnecessary imports - if ('wire 1' in line): continue # dunno why this is in some verilog files - - f.write(line) - f.close() - - def combine_verilog(self,lib_path,library,cells) -> None: - # set up file - f = open(os.path.join(self.cache_dir,"verilog",library+".v"), "w") - #f.write('`define UNIT_DELAY \n') # WHERE TF IS THIS DEFINED IN PDK?!?!?! - # include udp models - models = os.listdir(os.path.join(lib_path,'models')) - for model in models: - model_path = os.path.join(self.cache_dir,'verilog','models',library+'__'+model+'.blackbox.v') - f.write('`include "'+model_path+'"\n') - # iterate over cells - for cell in cells: - cell_path = os.path.join(lib_path,'cells',cell) - cell_files = os.listdir(cell_path) - for cell_file_path in cell_files: - if cell_file_path.endswith('.behavioral.v') or \ - ( cell_file_path.endswith('.v') and cell_file_path.startswith(library+'__'+cell+'_') ): - cell_file = open(os.path.join(cell_path,cell_file_path),"r") - f.write('\n\n') # separate modules - for line in cell_file: - # edit these lines - if line.startswith('`default_nettype none\n'): - line = line.replace('none','wire') - # skip these lines - if '*' in line: continue # comments - if line.startswith('`include'): continue # unnecessary imports - if ('wire 1' in line): continue # dunno why this is in some verilog files - - f.write(line) - f.close() - def parse_models(self,lib_path,library) -> None: - model_path = os.path.join(lib_path,'models') - models = os.listdir(model_path) - for model in models: - cache_model_path = os.path.join(self.cache_dir,'verilog','models') - model_filename = library+'__'+model+'.blackbox.v' - f = open(os.path.join(cache_model_path,model_filename),'w') - model_file = open(os.path.join(model_path,model,model_filename)) - for line in model_file: - if line.startswith("`default_nettype none"): - line = line.replace('none','wire') - f.write(line) - f.close() - def parse_models2(self,lib_path,library) -> None: - model_path = os.path.join(lib_path,'models') - models = os.listdir(model_path) - for model in models: - cache_model_path = os.path.join(self.cache_dir,'verilog','models') - model_filename = library+'__'+model+'.v' - f = open(os.path.join(cache_model_path,model_filename),'w') - model_file = open(os.path.join(model_path,model,model_filename)) - for line in model_file: - if line.startswith("`default_nettype none"): - line = line.replace('none','wire') - f.write(line) - f.close() - - def combine_cdl(self,lib_path,library,cells) -> None: - # set up file - f = open(os.path.join(self.cache_dir,"cdl",library+".cdl"), "w") - # iterate over cells - for cell in cells: - cell_path = os.path.join(lib_path,'cells',cell) - cell_files = os.listdir(cell_path) - for cell_file_path in cell_files: - if cell_file_path.endswith('.cdl'): - cell_file = open(os.path.join(cell_path,cell_file_path),"r") - writing=False - for line in cell_file: - if line.startswith(".SUBCKT"): - writing=True - if writing: - f.write(line) - if line.startswith(".ENDS"): - f.write('\n\n') - break - f.close() + # maybe run open_pdks for the user and install in tech cache...? + # this takes a while and ~7Gb + + # hack tlef + sky130A = self.get_setting("technology.sky130.sky130A") + lef_files = self.read_libs([ + hammer_tech.filters.lef_filter + ], hammer_tech.HammerTechnologyUtils.to_plain_item) + tlef_new_path = lef_files[0] + words = tlef_new_path.split('/') + tlef_filename = words[-1] + library_name = tlef_filename.split('.')[0] + tlef_old_path = os.path.join(sky130A,'libs.ref',library_name,'techlef',tlef_filename) + + f_old = open(tlef_old_path,'r') + f_new = open(tlef_new_path,'w') + for line in f_old: + f_new.write(line) + if line.strip() == 'END pwell': + f_new.write(''' +LAYER licon + TYPE CUT ; +END licon +''') + + f_old.close() + f_new.close() + print('Loaded Sky130 Tech') + tech = SKY130Tech() diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 97ce77222..29d0fd6c9 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -15,6 +15,10 @@ "path": "$SKY130_NDA", "base var": "technology.sky130.sky130_nda" }, + { + "path": "$SKY130A", + "base var": "technology.sky130.sky130A" + }, { "path": "tech-sky130-cache", "base var": "" @@ -25,8 +29,7 @@ { "tool name": "calibre", "deck name": "all_drc", - "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules", - "newpath": "tech-sky130-cache/drc/s8_drcRules" + "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" } ], "additional_drc_text": "", @@ -42,7 +45,7 @@ "libraries": [ { - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef", + "lef file": "tech-sky130-cache/techlef/sky130_fd_sc_hd.tlef", "provides": [ { "lib_type": "technology" @@ -51,11 +54,11 @@ }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -73,11 +76,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -95,11 +98,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -117,11 +120,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -139,11 +142,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -161,11 +164,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", "pmos": "fast", @@ -183,11 +186,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -205,11 +208,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -227,11 +230,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -249,11 +252,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -271,11 +274,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -293,11 +296,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -315,11 +318,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -337,11 +340,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", "pmos": "slow", @@ -359,11 +362,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "typical", "pmos": "typical", @@ -381,11 +384,11 @@ ] }, { - "nldm liberty file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", - "verilog sim": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$OPEN_PDKS/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", - "gds file": "tech-sky130-cache/gds/sky130_fd_sc_hd.gds", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "typical", "pmos": "typical", From 16ff7d988d61104029ac29d6631cb81edd94cd5b Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Wed, 26 May 2021 12:23:11 -0700 Subject: [PATCH 34/81] Update sky130.tech.json --- .../technology/sky130/sky130.tech.json | 221 ++++++++++++++---- 1 file changed, 173 insertions(+), 48 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 29d0fd6c9..96182230e 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -7,10 +7,6 @@ "path": "$SKY130_PDK", "base var": "technology.sky130.sky130_pdk" }, - { - "path": "$OPEN_PDKS", - "base var": "technology.sky130.open_pdks" - }, { "path": "$SKY130_NDA", "base var": "technology.sky130.sky130_nda" @@ -24,7 +20,7 @@ "base var": "" } ], - "gds map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "gds map file": "tech-sky130-cache/technology_library.layermap", "drc decks": [ { "tool name": "calibre", @@ -33,7 +29,6 @@ } ], "additional_drc_text": "", - "lvs decks": [ { "tool name": "calibre", @@ -42,17 +37,53 @@ } ], "additional_lvs_text": "", - + "physical only cells list": [ + "sky130_fd_sc_hd__tap_1", + "sky130_fd_sc_hd__tap_2", + "sky130_fd_sc_hd__tapvgnd_1", + "sky130_fd_sc_hd__tapvpwrvgnd_1", + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", + "sky130_fd_sc_hd__decap_3", + "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", + "sky130_fd_sc_hd__decap_8" + ], + "special cells": [ + { + "cell_type": "tapcell", + "name": [ + "sky130_fd_sc_hd__tap_1", + "sky130_fd_sc_hd__tap_2" + ] + }, + { + "cell_type": "stdfiller", + "name": [ + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", + "sky130_fd_sc_hd__decap_3", + "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", + "sky130_fd_sc_hd__decap_8" + ] + } + ], "libraries": [ { - "lef file": "tech-sky130-cache/techlef/sky130_fd_sc_hd.tlef", + "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", "provides": [ { "lib_type": "technology" } ] }, - { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", @@ -71,7 +102,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -93,7 +124,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -115,7 +146,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -137,7 +168,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -159,7 +190,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -181,7 +212,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -203,7 +234,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -225,7 +256,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -247,7 +278,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -269,7 +300,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -291,7 +322,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -313,7 +344,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -335,7 +366,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -357,7 +388,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -379,7 +410,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] }, @@ -401,7 +432,7 @@ "provides": [ { "lib_type": "stdcell", - "vt": "RVT" + "vt": "RVT" } ] } @@ -410,31 +441,125 @@ { "name": "sky130_fd_sc_hd", "metals": [ - {"name": "li1", "index": 1, "direction": "vertical", "min_width": 0.17, "max_width": 2147483.647, "pitch": 0.34, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.17}]}, - {"name": "met1", "index": 2, "direction": "horizontal", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.17, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, - {"name": "met2", "index": 3, "direction": "vertical", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, - {"name": "met3", "index": 4, "direction": "horizontal", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.34, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, - {"name": "met4", "index": 5, "direction": "vertical", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.46, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, - {"name": "met5", "index": 6, "direction": "horizontal", "min_width": 1.6, "max_width": 2147483.647, "pitch": 3.2, "offset": 1.7, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 1.6}]} + { + "name": "li1", + "index": 1, + "direction": "vertical", + "min_width": 0.17, + "max_width": 2147483.647, + "pitch": 0.34, + "offset": 0.23, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.17 + } + ] + }, + { + "name": "met1", + "index": 2, + "direction": "horizontal", + "min_width": 0.14, + "max_width": 2147483.647, + "pitch": 0.28, + "offset": 0.17, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.14 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.28 + } + ] + }, + { + "name": "met2", + "index": 3, + "direction": "vertical", + "min_width": 0.14, + "max_width": 2147483.647, + "pitch": 0.28, + "offset": 0.23, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.14 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.28 + } + ] + }, + { + "name": "met3", + "index": 4, + "direction": "horizontal", + "min_width": 0.3, + "max_width": 2147483.647, + "pitch": 0.6, + "offset": 0.34, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.3 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.4 + } + ] + }, + { + "name": "met4", + "index": 5, + "direction": "vertical", + "min_width": 0.3, + "max_width": 2147483.647, + "pitch": 0.6, + "offset": 0.46, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.3 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.4 + } + ] + }, + { + "name": "met5", + "index": 6, + "direction": "horizontal", + "min_width": 1.6, + "max_width": 2147483.647, + "pitch": 3.2, + "offset": 1.7, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 1.6 + } + ] + } ] } ], "sites": [ - {"name": "unithd", "x": 0.46, "y": 2.72}, - {"name": "unithddbl", "x": 0.46, "y": 5.44} - ], - "physical only cells list": [ - "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", - "sky130_fd_sc_hd__tapvgnd_1", - "sky130_fd_sc_hd__tapvpwrvgnd_1", - "sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8" - ], - "special cells": [ - {"cell_type": "tapcell", "name": ["sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2"]}, - {"cell_type": "stdfiller", "name": ["sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", - "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", - "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8"]} + { + "name": "unithd", + "x": 0.46, + "y": 2.72 + }, + { + "name": "unithddbl", + "x": 0.46, + "y": 5.44 + } ] -} +} \ No newline at end of file From f1bb4cd50ec49427140a11be9b745509d637840a Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Thu, 27 May 2021 12:43:25 -0700 Subject: [PATCH 35/81] Merge Sky130 TLEF Manipulations --- src/hammer-vlsi/technology/sky130/__init__.py | 38 ++++++++++--------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index a16181a08..986028f2a 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -8,8 +8,7 @@ import sys import re import os -#import tempfile -#import shutil +from pathlib import Path #from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any import hammer_tech @@ -25,32 +24,35 @@ def post_install_script(self) -> None: # maybe run open_pdks for the user and install in tech cache...? # this takes a while and ~7Gb - # hack tlef - sky130A = self.get_setting("technology.sky130.sky130A") - lef_files = self.read_libs([ - hammer_tech.filters.lef_filter - ], hammer_tech.HammerTechnologyUtils.to_plain_item) - tlef_new_path = lef_files[0] - words = tlef_new_path.split('/') - tlef_filename = words[-1] - library_name = tlef_filename.split('.')[0] - tlef_old_path = os.path.join(sky130A,'libs.ref',library_name,'techlef',tlef_filename) + # hack tlef, adding this very important `licon` section + setting_dir = self.get_setting("technology.sky130.open_pdks") + setting_dir = Path(setting_dir) + library_name = 'sky130_fd_sc_hd' + tlef_old_path = setting_dir / 'sky130'/ 'sky130A' / 'libs.ref' / library_name / 'techlef' / f'{library_name}.tlef' + if not tlef_old_path.exists(): + raise FileNotFoundError(f"Tech-LEF not found: {tlef_old_path}") + + cache_tech_dir_path = Path(self.cache_dir) / 'techlef' + os.makedirs(cache_tech_dir_path, exist_ok=True) + tlef_new_path = cache_tech_dir_path / f'{library_name}.tlef' f_old = open(tlef_old_path,'r') f_new = open(tlef_new_path,'w') for line in f_old: f_new.write(line) if line.strip() == 'END pwell': - f_new.write(''' -LAYER licon - TYPE CUT ; -END licon -''') - + f_new.write(_the_tlef_edit) + f_old.close() f_new.close() print('Loaded Sky130 Tech') +_the_tlef_edit = ''' +LAYER licon + TYPE CUT ; +END licon +''' + tech = SKY130Tech() From a076c034dbfde46bf32f7d39f242188ffec81bcd Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Thu, 27 May 2021 13:53:57 -0700 Subject: [PATCH 36/81] Add dont_use scan-flops --- src/hammer-vlsi/technology/sky130/defaults.yml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index 724120b0e..d72ef162c 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -9,7 +9,11 @@ technology.sky130: # Set some defaults for this technology. vlsi: # Technology dimension - core.node: 130 + core: + node: 130 + sram_generator_tool: "sram_compiler" + sram_generator_tool_path: ["${HAMMER_HOME}/src/hammer-vlsi/technology/sky130"] + sram_generator_tool_path_meta: "append" inputs: # Supply voltages. supplies: @@ -17,6 +21,8 @@ vlsi: ground: [{name: "VSS", pin: "VGND"}] VDD: "1.8 V" GND: "0 V" + + dont_use_list: ["*sdf*"] # Scan flops go haywire! Avoid them. # mmmc corners config mmmc_corners: [ From a87d316a79de3d66f5ce7202197c334f5201aa12 Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Thu, 27 May 2021 17:06:02 -0700 Subject: [PATCH 37/81] Copy Sky130 Layer-Map --- src/hammer-vlsi/technology/sky130/__init__.py | 24 +++++++++++++++---- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 986028f2a..318f13062 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -7,7 +7,7 @@ import sys import re -import os +import os, shutil from pathlib import Path #from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any @@ -23,8 +23,12 @@ class SKY130Tech(HammerTechnology): def post_install_script(self) -> None: # maybe run open_pdks for the user and install in tech cache...? # this takes a while and ~7Gb + self.setup_techlef() + self.setup_layermap() + print('Loaded Sky130 Tech') - # hack tlef, adding this very important `licon` section + def setup_techlef(self) -> None: + """ Copy and hack the tech-lef, adding this very important `licon` section """ setting_dir = self.get_setting("technology.sky130.open_pdks") setting_dir = Path(setting_dir) library_name = 'sky130_fd_sc_hd' @@ -32,7 +36,7 @@ def post_install_script(self) -> None: if not tlef_old_path.exists(): raise FileNotFoundError(f"Tech-LEF not found: {tlef_old_path}") - cache_tech_dir_path = Path(self.cache_dir) / 'techlef' + cache_tech_dir_path = Path(self.cache_dir) os.makedirs(cache_tech_dir_path, exist_ok=True) tlef_new_path = cache_tech_dir_path / f'{library_name}.tlef' @@ -42,10 +46,20 @@ def post_install_script(self) -> None: f_new.write(line) if line.strip() == 'END pwell': f_new.write(_the_tlef_edit) - f_old.close() f_new.close() - print('Loaded Sky130 Tech') + + def setup_layermap(self) -> None: + """ Copy the layer-map into `self.cache_dir` """ + nda_dir = self.get_setting("technology.sky130.sky130_nda") + nda_dir = Path(nda_dir) + layermap = nda_dir / "s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap" + if not layermap.exists(): + raise FileNotFoundError(f"Layer-map not found: {layermap}") + cache_path = Path(self.cache_dir) + os.makedirs(cache_path, exist_ok=True) + shutil.copy(layermap, cache_path) + _the_tlef_edit = ''' From fd9c89d5d8bceaee13c12bc9fb7821083a5f2a27 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 1 Jun 2021 10:26:07 -0700 Subject: [PATCH 38/81] removed open_pdks variable, added gds map path --- src/hammer-vlsi/technology/sky130/__init__.py | 4 +-- .../technology/sky130/defaults.yml | 3 +- .../technology/sky130/sky130.tech.json | 35 +++++++++++++++++-- 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 318f13062..7ee5ac236 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -29,10 +29,10 @@ def post_install_script(self) -> None: def setup_techlef(self) -> None: """ Copy and hack the tech-lef, adding this very important `licon` section """ - setting_dir = self.get_setting("technology.sky130.open_pdks") + setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) library_name = 'sky130_fd_sc_hd' - tlef_old_path = setting_dir / 'sky130'/ 'sky130A' / 'libs.ref' / library_name / 'techlef' / f'{library_name}.tlef' + tlef_old_path = setting_dir / 'libs.ref' / library_name / 'techlef' / f'{library_name}.tlef' if not tlef_old_path.exists(): raise FileNotFoundError(f"Tech-LEF not found: {tlef_old_path}") diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index d72ef162c..b1bc0a216 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -1,10 +1,11 @@ # Settings for the sky130 technology to be overriden by the project. technology.sky130: sky130_pdk: "PATH_TO_SKY130_PDK" - open_pdks: "PATH_TO_OPEN_PDKS" sky130_nda: "PATH_TO_NDA_FILES" + sky130A: "PATH_TO_SKY130A_DIR" dffram_lib: "PATH_TO_DFFRAM/Compiler/build" openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" + gds_map_file: "PATH_TO_GDS_MAP_FILE (you must write this)" # Set some defaults for this technology. vlsi: diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 96182230e..e74c44fb7 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -15,12 +15,17 @@ "path": "$SKY130A", "base var": "technology.sky130.sky130A" }, + { + "path": "$GDS_MAP_FILE", + "base var": "technology.sky130.gds_map_file" + }, { "path": "tech-sky130-cache", "base var": "" } ], - "gds map file": "tech-sky130-cache/technology_library.layermap", + "gds map file": "$GDS_MAP_FILE", + "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { "tool name": "calibre", @@ -52,12 +57,12 @@ "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8" ], + "dont use list": [], "special cells": [ { "cell_type": "tapcell", "name": [ - "sky130_fd_sc_hd__tap_1", - "sky130_fd_sc_hd__tap_2" + "sky130_fd_sc_hd__tapvpwrvgnd_1" ] }, { @@ -73,11 +78,24 @@ "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8" ] + }, + { + "cell_type": "tielocell", + "name": [ + "sky130_fd_sc_hd__conb_1" + ] + }, + { + "cell_type": "tiehicell", + "name": [ + "sky130_fd_sc_hd__conb_1" + ] } ], "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", + "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", "provides": [ { "lib_type": "technology" @@ -435,6 +453,17 @@ "vt": "RVT" } ] + }, + { + "lef file": "$SKY130A/libs.ref/sky130_fd_pr/lef/sky130_fd_pr.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_pr/cdl/sky130_fd_pr.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_pr/gds/sky130_fd_pr.gds", + "provides": [ + { + "lib_type": "primitives", + "vt": "RVT" + } + ] } ], "stackups": [ From bccd7c8367883084e8584e0237b6cc569b1a4c63 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 1 Jun 2021 10:26:27 -0700 Subject: [PATCH 39/81] removed open_pdks variable, added gds map path --- src/hammer-vlsi/technology/sky130/defaults.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index b1bc0a216..ec7b5ffe5 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -5,7 +5,7 @@ technology.sky130: sky130A: "PATH_TO_SKY130A_DIR" dffram_lib: "PATH_TO_DFFRAM/Compiler/build" openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" - gds_map_file: "PATH_TO_GDS_MAP_FILE (you must write this)" + gds_map_file: "PATH_TO_GDS_MAP_FILE (you must write this file)" # Set some defaults for this technology. vlsi: From 54705ac000e47ec77a661e33cbd6535ed993c5af Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 3 Jun 2021 12:35:18 -0700 Subject: [PATCH 40/81] fixed floating nets and CDL netlist device names --- src/hammer-vlsi/technology/sky130/__init__.py | 126 +++++++++++++++++- .../technology/sky130/defaults.yml | 7 + .../technology/sky130/sky130.tech.json | 32 ++--- 3 files changed, 144 insertions(+), 21 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 7ee5ac236..6e8a9faf2 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -9,7 +9,7 @@ import re import os, shutil from pathlib import Path -#from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any +from typing import NamedTuple, List, Optional, Tuple, Dict, Set, Any import hammer_tech from hammer_tech import HammerTechnology @@ -23,22 +23,59 @@ class SKY130Tech(HammerTechnology): def post_install_script(self) -> None: # maybe run open_pdks for the user and install in tech cache...? # this takes a while and ~7Gb + self.library_name = 'sky130_fd_sc_hd' + self.setup_cdl() self.setup_techlef() self.setup_layermap() + self.setup_lvs_deck() print('Loaded Sky130 Tech') + # Helper functions - copied from TSMC28 plugin + def expand_tech_cache_path(self, path) -> str: + """ Replace occurrences of the cache directory's basename with + the full path to the cache dir.""" + cache_dir_basename = os.path.basename(self.cache_dir) + return path.replace(cache_dir_basename, self.cache_dir) + + def ensure_dirs_exist(self, path) -> None: + dir_name = os.path.dirname(path) + if not os.path.exists(dir_name): + self.logger.info('Creating directory: {}'.format(dir_name)) + os.makedirs(dir_name) + + # Tech setup steps + def setup_cdl(self) -> None: + """ Copy and hack the cdl, replacing pfet_01v8_hvt/nfet_01v8 with phighvt/nshort """ + setting_dir = self.get_setting("technology.sky130.sky130A") + setting_dir = Path(setting_dir) + cdl_old_path = setting_dir / 'libs.ref' / self.library_name / 'cdl' / f'{self.library_name}.cdl' + if not cdl_old_path.exists(): + raise FileNotFoundError(f"CDL not found: {cdl_old_path}") + + cache_tech_dir_path = Path(self.cache_dir) + os.makedirs(cache_tech_dir_path, exist_ok=True) + cdl_new_path = cache_tech_dir_path / f'{self.library_name}.cdl' + + f_old = open(cdl_old_path,'r') + f_new = open(cdl_new_path,'w') + for line in f_old: + new_line = line.replace('pfet_01v8_hvt','phighvt') + new_line = new_line.replace('nfet_01v8', 'nshort') + f_new.write(new_line) + f_old.close() + f_new.close() + def setup_techlef(self) -> None: """ Copy and hack the tech-lef, adding this very important `licon` section """ setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) - library_name = 'sky130_fd_sc_hd' - tlef_old_path = setting_dir / 'libs.ref' / library_name / 'techlef' / f'{library_name}.tlef' + tlef_old_path = setting_dir / 'libs.ref' / self.library_name / 'techlef' / f'{self.library_name}.tlef' if not tlef_old_path.exists(): raise FileNotFoundError(f"Tech-LEF not found: {tlef_old_path}") cache_tech_dir_path = Path(self.cache_dir) os.makedirs(cache_tech_dir_path, exist_ok=True) - tlef_new_path = cache_tech_dir_path / f'{library_name}.tlef' + tlef_new_path = cache_tech_dir_path / f'{self.library_name}.tlef' f_old = open(tlef_old_path,'r') f_new = open(tlef_new_path,'w') @@ -60,7 +97,40 @@ def setup_layermap(self) -> None: os.makedirs(cache_path, exist_ok=True) shutil.copy(layermap, cache_path) - + def setup_lvs_deck(self) -> None: + """Remove conflicting specification statements found in PDK LVS decks.""" + pattern = '.*({}).*\n'.format('|'.join(LVS_DECK_SCRUB_LINES)) + matcher = re.compile(pattern) + + source_paths = self.get_setting('technology.sky130.lvs_deck_sources') + lvs_decks = list(self.config.lvs_decks) + for i in range(len(lvs_decks)): + deck = lvs_decks[i] + try: + source_path = source_paths[i] + except IndexError: + self.logging.error( + 'No corresponding source for LVS deck {}'.format(deck)) + dest_path = self.expand_tech_cache_path(str(deck.path)) + self.ensure_dirs_exist(dest_path) + with open(source_path, 'r') as sf: + with open(dest_path, 'w') as df: + self.logger.info("Modifying LVS deck: {} -> {}".format + (source_path, dest_path)) + df.write(matcher.sub("", sf.read())) + + def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: + hooks = {"innovus": [ + HammerTool.make_post_insertion_hook("init_design", sky130_innovus_settings), + HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), + #HammerTool.make_replacement_hook("power_straps", intech22_innovus.intech22_reference_power_straps), + # HammerTool.make_post_insertion_hook("power_straps", intech22_innovus.intech22_m2_staples), + # HammerTool.make_pre_insertion_hook("clock_tree", intech22_innovus.intech22_cts_options), + # HammerTool.make_replacement_hook("add_fillers", intech22_innovus.intech22_add_fillers), + ]} + return hooks.get(tool_name, []) + + _the_tlef_edit = ''' LAYER licon @@ -68,5 +138,51 @@ def setup_layermap(self) -> None: END licon ''' +LVS_DECK_SCRUB_LINES = [ + "VIRTUAL CONNECT REPORT", + "SOURCE PRIMARY", + "SOURCE SYSTEM SPICE", + "SOURCE PATH", + "ERC", + "LVS REPORT" +] + +# various Innovus database settings +def sky130_innovus_settings(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "Innovus settings can only run on par" + """Settings for every tool invocation""" + ht.append( + ''' +########################################################## +# Routing attributes [get_db -category route] +########################################################## +#------------------------------------------------------------------------------- +set_db route_design_antenna_diode_insertion 1 +set_db route_design_antenna_cell_name "sky130_fd_sc_hd__diode_2" +set_db route_design_bottom_routing_layer 1 + ''' + ) + return True + +# Pair VDD/VPWR and VSS/VGND nets +# these commands are already added in Innovus.write_netlist, +# but must also occur before power straps are placed +def sky130_power_nets(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "Innovus settings can only run on par" + """Settings for every tool invocation""" + ht.append( + ''' +connect_global_net VDD -type net -net_base_name VPWR +connect_global_net VSS -type net -net_base_name VGND + ''' + ) + return True + + + tech = SKY130Tech() diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index ec7b5ffe5..b9ab93582 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -5,7 +5,10 @@ technology.sky130: sky130A: "PATH_TO_SKY130A_DIR" dffram_lib: "PATH_TO_DFFRAM/Compiler/build" openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" + gds_map_file: "PATH_TO_GDS_MAP_FILE (you must write this file)" + lvs_deck_sources: + - "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" # Set some defaults for this technology. vlsi: @@ -65,3 +68,7 @@ technology.core: par.inputs: gds_merge: true + +# Calibre environment variables +mentor.extra_env_vars: + - PDK_HOME: "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1" \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index e74c44fb7..ab574775d 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -106,7 +106,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -128,7 +128,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -150,7 +150,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -172,7 +172,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -194,7 +194,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -216,7 +216,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "fast", @@ -238,7 +238,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -260,7 +260,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -282,7 +282,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -304,7 +304,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -326,7 +326,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -348,7 +348,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -370,7 +370,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -392,7 +392,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "slow", @@ -414,7 +414,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "typical", @@ -436,7 +436,7 @@ "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", "corner": { "nmos": "typical", From 92daf4b826ee5fbb27f9432d61b82bf71d554706 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 3 Jun 2021 14:05:35 -0700 Subject: [PATCH 41/81] set met1 as bottom routing layer --- src/hammer-vlsi/technology/sky130/__init__.py | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 6e8a9faf2..406ce0f84 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -121,8 +121,9 @@ def setup_lvs_deck(self) -> None: def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ - HammerTool.make_post_insertion_hook("init_design", sky130_innovus_settings), - HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), + HammerTool.make_post_insertion_hook("init_design", sky130_innovus_settings), + HammerTool.make_pre_insertion_hook("place_tap_cells", sky130_place_endcaps), + HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), #HammerTool.make_replacement_hook("power_straps", intech22_innovus.intech22_reference_power_straps), # HammerTool.make_post_insertion_hook("power_straps", intech22_innovus.intech22_m2_staples), # HammerTool.make_pre_insertion_hook("clock_tree", intech22_innovus.intech22_cts_options), @@ -161,7 +162,7 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: #------------------------------------------------------------------------------- set_db route_design_antenna_diode_insertion 1 set_db route_design_antenna_cell_name "sky130_fd_sc_hd__diode_2" -set_db route_design_bottom_routing_layer 1 +set_db route_design_bottom_routing_layer 2 ''' ) return True @@ -182,7 +183,20 @@ def sky130_power_nets(ht: HammerTool) -> bool: ) return True - +# reference: /tools/commercial/skywater/swtech130/skywater-src-nda/scs8hd/V0.0.2/scripts +def sky130_place_endcaps(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "endcap insertion can only run on par" + ht.append( + ''' +set_db add_endcaps_boundary_tap true +set_db add_endcaps_left_edge sky130_fd_sc_hd__tap_1 +set_db add_endcaps_right_edge sky130_fd_sc_hd__tap_1 +add_endcaps + ''' + ) + return True tech = SKY130Tech() From 9d7440d5fdc8ad083b85644237fbfbfc246fabf3 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 3 Jun 2021 17:43:50 -0700 Subject: [PATCH 42/81] adding supply pin mapping to defaults file --- .../technology/sky130/defaults.yml | 38 ++++++++++--------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index b9ab93582..a67d80922 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -10,6 +10,10 @@ technology.sky130: lvs_deck_sources: - "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" +# Calibre environment variables +mentor.extra_env_vars: + - PDK_HOME: "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1" + # Set some defaults for this technology. vlsi: # Technology dimension @@ -21,26 +25,30 @@ vlsi: inputs: # Supply voltages. supplies: - power: [{name: "VDD", pin: "VPWR"}] - ground: [{name: "VSS", pin: "VGND"}] - VDD: "1.8 V" - GND: "0 V" + power: [ {name: "VDD", pin: "VDD"}, + {name: "VPWR", pin: "VPWR", tie: "VDD"}, + {name: "VPB", pin: "VPB", tie: "VDD"}] + ground: [ {name: "VSS", pin: "VSS"}, + {name: "VGND", pin: "VGND", tie: "VSS"}, + {name: "VNB", pin: "VNB", tie: "VSS"}] + VDD: "1.8 V" + GND: "0 V" dont_use_list: ["*sdf*"] # Scan flops go haywire! Avoid them. # mmmc corners config mmmc_corners: [ { - "name": "sky130_fd_sc_hd__ss_100C_1v60", - "type": "setup", - "voltage": "1.60 V", - "temp": "100 C" + name: "sky130_fd_sc_hd__ss_100C_1v60", + type: "setup", + voltage: "1.60 V", + temp: "100 C" }, { - "name": "sky130_fd_sc_hd__ff_n40C_1v95", - "type": "hold", - "voltage": "1.95 V", - "temp": "-40 C" + name: "sky130_fd_sc_hd__ff_n40C_1v95", + type: "hold", + voltage: "1.95 V", + temp: "-40 C" } ] technology: @@ -67,8 +75,4 @@ technology.core: par.inputs: gds_merge: true - - -# Calibre environment variables -mentor.extra_env_vars: - - PDK_HOME: "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1" \ No newline at end of file + \ No newline at end of file From 7e6d94e9fe0f6eb1b518e2302bb7382f5ffaaaf4 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 7 Jun 2021 11:08:14 -0700 Subject: [PATCH 43/81] gcd passes LVS --- src/hammer-vlsi/technology/sky130/__init__.py | 56 ++++++++++++++----- .../technology/sky130/defaults.yml | 21 ++++--- .../technology/sky130/sky130.tech.json | 19 ++----- 3 files changed, 60 insertions(+), 36 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 406ce0f84..13f1a9de6 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -59,9 +59,9 @@ def setup_cdl(self) -> None: f_old = open(cdl_old_path,'r') f_new = open(cdl_new_path,'w') for line in f_old: - new_line = line.replace('pfet_01v8_hvt','phighvt') - new_line = new_line.replace('nfet_01v8', 'nshort') - f_new.write(new_line) + line = line.replace('pfet_01v8_hvt','phighvt') + line = line.replace('nfet_01v8', 'nshort') + f_new.write(line) f_old.close() f_new.close() @@ -122,8 +122,10 @@ def setup_lvs_deck(self) -> None: def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ HammerTool.make_post_insertion_hook("init_design", sky130_innovus_settings), - HammerTool.make_pre_insertion_hook("place_tap_cells", sky130_place_endcaps), + HammerTool.make_pre_insertion_hook("place_tap_cells", sky130_add_endcaps), HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), + HammerTool.make_post_insertion_hook("place_opt_design", sky130_add_tieoffs), + HammerTool.make_pre_insertion_hook("write_design", sky130_connect_nets), #HammerTool.make_replacement_hook("power_straps", intech22_innovus.intech22_reference_power_straps), # HammerTool.make_post_insertion_hook("power_straps", intech22_innovus.intech22_m2_staples), # HammerTool.make_pre_insertion_hook("clock_tree", intech22_innovus.intech22_cts_options), @@ -167,14 +169,30 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: ) return True + + +# reference: /tools/commercial/skywater/swtech130/skywater-src-nda/scs8hd/V0.0.2/scripts +def sky130_add_endcaps(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "endcap insertion can only run on par" + ht.append( + ''' +set_db add_endcaps_boundary_tap true +set_db add_endcaps_left_edge sky130_fd_sc_hd__tap_1 +set_db add_endcaps_right_edge sky130_fd_sc_hd__tap_1 +add_endcaps + ''' + ) + return True + # Pair VDD/VPWR and VSS/VGND nets # these commands are already added in Innovus.write_netlist, # but must also occur before power straps are placed def sky130_power_nets(ht: HammerTool) -> bool: assert isinstance( ht, HammerPlaceAndRouteTool - ), "Innovus settings can only run on par" - """Settings for every tool invocation""" + ), "connect global nets can only run on par" ht.append( ''' connect_global_net VDD -type net -net_base_name VPWR @@ -183,17 +201,29 @@ def sky130_power_nets(ht: HammerTool) -> bool: ) return True -# reference: /tools/commercial/skywater/swtech130/skywater-src-nda/scs8hd/V0.0.2/scripts -def sky130_place_endcaps(ht: HammerTool) -> bool: +# TODO: add these two functions into Hammer Innovus plugin +def sky130_add_tieoffs(ht: HammerTool) -> bool: assert isinstance( ht, HammerPlaceAndRouteTool - ), "endcap insertion can only run on par" + ), "tie high/low cell insertion can only run on par" ht.append( ''' -set_db add_endcaps_boundary_tap true -set_db add_endcaps_left_edge sky130_fd_sc_hd__tap_1 -set_db add_endcaps_right_edge sky130_fd_sc_hd__tap_1 -add_endcaps +set_db add_tieoffs_cells sky130_fd_sc_hd__conb_1 +add_tieoffs + ''' + ) + return True + +def sky130_connect_nets(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "connect global nets can only run on par" + ht.append( + ''' +connect_global_net VDD -type pg_pin -pin_base_name VPWR -all +connect_global_net VDD -type pg_pin -pin_base_name VPB -all +connect_global_net VSS -type pg_pin -pin_base_name VGND -all +connect_global_net VSS -type pg_pin -pin_base_name VNB -all ''' ) return True diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index a67d80922..d37146c8d 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -6,7 +6,9 @@ technology.sky130: dffram_lib: "PATH_TO_DFFRAM/Compiler/build" openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" - gds_map_file: "PATH_TO_GDS_MAP_FILE (you must write this file)" + # GDS map file path, not provided by efabless + gds_map_file: "${CHIPYARD_HOME}/vlsi/sky130-files/sky130_lefpin.map" + lvs_deck_sources: - "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" @@ -24,13 +26,14 @@ vlsi: sram_generator_tool_path_meta: "append" inputs: # Supply voltages. + # TODO: add ability to tie pin to net in Hammer Innovus plugin supplies: - power: [ {name: "VDD", pin: "VDD"}, - {name: "VPWR", pin: "VPWR", tie: "VDD"}, - {name: "VPB", pin: "VPB", tie: "VDD"}] - ground: [ {name: "VSS", pin: "VSS"}, - {name: "VGND", pin: "VGND", tie: "VSS"}, - {name: "VNB", pin: "VNB", tie: "VSS"}] + power: [ {name: "VDD", pin: "VDD"}] + # {name: "VPWR", pin: "VPWR", tie: "VDD"}, + # {name: "VPB", pin: "VPB", tie: "VDD"}] + ground: [ {name: "VSS", pin: "VSS"}] + # {name: "VGND", pin: "VGND", tie: "VSS"}, + # {name: "VNB", pin: "VNB", tie: "VSS"}] VDD: "1.8 V" GND: "0 V" @@ -60,8 +63,8 @@ vlsi: bump_block_cut_layer: "via4" # Set the interval and offset for tap cells - # nk - not sure if this is right?? - tap_cell_interval: "27" + # interval value from the eFPGA---RTL-to-GDS-with-SKY130 + tap_cell_interval: "40" tap_cell_offset: "5" technology.core: diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index ab574775d..bb952f7fb 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -38,10 +38,11 @@ { "tool name": "calibre", "deck name": "all_lvs", - "path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8" + "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", + "path": "tech-sky130-cache/lvsControlFile_s8" } ], - "additional_lvs_text": "", + "additional_lvs_text": "\nLVS FILTER D OPEN SOURCE\nLVS FILTER D OPEN LAYOUT", "physical only cells list": [ "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", @@ -51,11 +52,7 @@ "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", - "sky130_fd_sc_hd__decap_3", - "sky130_fd_sc_hd__decap_4", - "sky130_fd_sc_hd__decap_6", - "sky130_fd_sc_hd__decap_8" + "sky130_fd_sc_hd__diode_2" ], "dont use list": [], "special cells": [ @@ -80,13 +77,7 @@ ] }, { - "cell_type": "tielocell", - "name": [ - "sky130_fd_sc_hd__conb_1" - ] - }, - { - "cell_type": "tiehicell", + "cell_type": "tiehilocell", "name": [ "sky130_fd_sc_hd__conb_1" ] From 08a7e12a12a585c0751f57c4dce35afc46488bf2 Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Sun, 6 Jun 2021 16:29:34 -0700 Subject: [PATCH 44/81] Sky130 using 4k rather than less-mature 8k SRAM --- src/hammer-vlsi/technology/sky130/sram-cache.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json index 421880750..22f714698 100644 --- a/src/hammer-vlsi/technology/sky130/sram-cache.json +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -1,8 +1,8 @@ [ { "type": "sram", - "name": "sky130_sram_8kbyte_1rw1r_32x2048_8", - "depth": "2048", + "name": "sky130_sram_4kbyte_1rw1r_32x1024_8", + "depth": "1024", "width": 32, "family": "1rw", "mask": "true", From 325feaa0453718b3f9d13acd4adef252d7e39d24 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 7 Jun 2021 13:02:11 -0700 Subject: [PATCH 45/81] fixed path to gds map file --- src/hammer-vlsi/technology/sky130/defaults.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index d37146c8d..ac0148d08 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -7,7 +7,7 @@ technology.sky130: openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" # GDS map file path, not provided by efabless - gds_map_file: "${CHIPYARD_HOME}/vlsi/sky130-files/sky130_lefpin.map" + gds_map_file: "sky130-files/sky130_lefpin.map" lvs_deck_sources: - "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" From 8202b3b04497b4e9132cf9beb56cb51f687a5558 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 14 Jun 2021 12:08:06 -0700 Subject: [PATCH 46/81] innovus and calibre commands --- src/hammer-vlsi/technology/sky130/__init__.py | 23 +++++++++++++++++++ .../technology/sky130/sky130.tech.json | 10 +++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 13f1a9de6..1ede3a0c2 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -24,6 +24,7 @@ def post_install_script(self) -> None: # maybe run open_pdks for the user and install in tech cache...? # this takes a while and ~7Gb self.library_name = 'sky130_fd_sc_hd' + self.setup_sram_cdl() self.setup_cdl() self.setup_techlef() self.setup_layermap() @@ -42,6 +43,19 @@ def ensure_dirs_exist(self, path) -> None: if not os.path.exists(dir_name): self.logger.info('Creating directory: {}'.format(dir_name)) os.makedirs(dir_name) + + def setup_sram_cdl(self) -> None: + old_path = Path(self.get_setting("technology.sky130.openram_lib")) / 'sky130_sram_4kbyte_1rw1r_32x1024_8' / 'sky130_sram_4kbyte_1rw1r_32x1024_8.lvs.sp' + new_path = self.expand_tech_cache_path('tech-sky130-cache/sky130_sram_4kbyte_1rw1r_32x1024_8/sky130_sram_4kbyte_1rw1r_32x1024_8.lvs.sp') + print(new_path) + self.ensure_dirs_exist(new_path) + with open(old_path,'r') as f_old: + with open(new_path,'w') as f_new: + for line in f_old: + line = line.replace('sky130_fd_pr__pfet_01v8','pshort') + line = line.replace('sky130_fd_pr__nfet_01v8','nshort') + f_new.write(line) + # Tech setup steps def setup_cdl(self) -> None: @@ -118,6 +132,7 @@ def setup_lvs_deck(self) -> None: self.logger.info("Modifying LVS deck: {} -> {}".format (source_path, dest_path)) df.write(matcher.sub("", sf.read())) + df.write(LVS_DECK_INSERT_LINES) def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ @@ -150,6 +165,14 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: "LVS REPORT" ] +# TODO: black boxing sram is temporary!! +LVS_DECK_INSERT_LINES = ''' +LVS FILTER D OPEN SOURCE +LVS FILTER D OPEN LAYOUT + +LVS BOX sky130_sram_4kbyte_1rw1r_32x1024_8 +''' + # various Innovus database settings def sky130_innovus_settings(ht: HammerTool) -> bool: assert isinstance( diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index bb952f7fb..0c19cf51a 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -42,7 +42,7 @@ "path": "tech-sky130-cache/lvsControlFile_s8" } ], - "additional_lvs_text": "\nLVS FILTER D OPEN SOURCE\nLVS FILTER D OPEN LAYOUT", + "additional_lvs_text": "", "physical only cells list": [ "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", @@ -93,6 +93,14 @@ } ] }, + { + "spice file": "/tools/B/nayiri/sky130/chipyard-osci-sky130/vlsi/sky130-files/devices.cdl", + "provides": [ + { + "lib_type": "technology" + } + ] + }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", From 41ca49f6328fd6360d60b502d498647895a779b8 Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Wed, 16 Jun 2021 11:46:51 -0700 Subject: [PATCH 47/81] Move Sky130 to use 1-2kB OpenRAM SRAM macros. Exclude them from DRC runs --- src/hammer-vlsi/technology/sky130/__init__.py | 35 ++++--- .../technology/sky130/sram-cache.json | 98 ++++++++++++++++++- 2 files changed, 120 insertions(+), 13 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 1ede3a0c2..898d814dd 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -44,17 +44,27 @@ def ensure_dirs_exist(self, path) -> None: self.logger.info('Creating directory: {}'.format(dir_name)) os.makedirs(dir_name) + @staticmethod + def openram_sram_names() -> None: + """ Return a list of cell-names of the OpenRAM SRAMs (that we'll use). """ + return [ + # "sky130_sram_4kbyte_1rw1r_32x1024_8", # Eventually to be reinstated, some day + "sky130_sram_1kbyte_1rw1r_32x256_8", + "sky130_sram_1kbyte_1rw1r_8x1024_8", + "sky130_sram_2kbyte_1rw1r_32x512_8" + ] + def setup_sram_cdl(self) -> None: - old_path = Path(self.get_setting("technology.sky130.openram_lib")) / 'sky130_sram_4kbyte_1rw1r_32x1024_8' / 'sky130_sram_4kbyte_1rw1r_32x1024_8.lvs.sp' - new_path = self.expand_tech_cache_path('tech-sky130-cache/sky130_sram_4kbyte_1rw1r_32x1024_8/sky130_sram_4kbyte_1rw1r_32x1024_8.lvs.sp') - print(new_path) - self.ensure_dirs_exist(new_path) - with open(old_path,'r') as f_old: - with open(new_path,'w') as f_new: - for line in f_old: - line = line.replace('sky130_fd_pr__pfet_01v8','pshort') - line = line.replace('sky130_fd_pr__nfet_01v8','nshort') - f_new.write(line) + for sram_name in self.openram_sram_names(): + old_path = Path(self.get_setting("technology.sky130.openram_lib")) / sram_name / f"{sram_name}.lvs.sp" + new_path = self.expand_tech_cache_path(f'tech-sky130-cache/{sram_name}/{sram_name}.lvs.sp') + self.ensure_dirs_exist(new_path) + with open(old_path,'r') as f_old: + with open(new_path,'w') as f_new: + for line in f_old: + line = line.replace('sky130_fd_pr__pfet_01v8','pshort') + line = line.replace('sky130_fd_pr__nfet_01v8','nshort') + f_new.write(line) # Tech setup steps @@ -165,13 +175,14 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: "LVS REPORT" ] -# TODO: black boxing sram is temporary!! LVS_DECK_INSERT_LINES = ''' LVS FILTER D OPEN SOURCE LVS FILTER D OPEN LAYOUT -LVS BOX sky130_sram_4kbyte_1rw1r_32x1024_8 ''' +# TODO: black boxing sram is temporary!! +for name in SKY130Tech.openram_sram_names(): + LVS_DECK_INSERT_LINES += f"LVS BOX {name} \n" # various Innovus database settings def sky130_innovus_settings(ht: HammerTool) -> bool: diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json index 22f714698..5c05e5d2b 100644 --- a/src/hammer-vlsi/technology/sky130/sram-cache.json +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -1,8 +1,104 @@ [ { "type": "sram", - "name": "sky130_sram_4kbyte_1rw1r_32x1024_8", + "name": "sky130_sram_1kbyte_1rw1r_8x1024_8", "depth": "1024", + "width": 8, + "family": "1rw", + "mask": "true", + "vt": "svt", + "ports": [ + { + "address port name": "addr0", + "address port polarity": "active high", + "clock port name": "clk0", + "clock port polarity": "positive edge", + "write enable port name": "web0", + "write enable port polarity": "active low", + "output port name": "dout0", + "output port polarity": "active high", + "input port name": "din0", + "input port polarity": "active high", + "chip enable port name": "csb0", + "chip enable port polarity": "active low", + "mask port name": "wmask0", + "mask port polarity": "active high", + "mask granularity": 8 + } + ], + "extra ports": [ + { + "name": "clk1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "csb1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "addr1", + "width": 11, + "type": "constant", + "value": 0 + } + ] + }, + { + "type": "sram", + "name": "sky130_sram_1kbyte_1rw1r_32x256_8", + "depth": "256", + "width": 32, + "family": "1rw", + "mask": "true", + "vt": "svt", + "ports": [ + { + "address port name": "addr0", + "address port polarity": "active high", + "clock port name": "clk0", + "clock port polarity": "positive edge", + "write enable port name": "web0", + "write enable port polarity": "active low", + "output port name": "dout0", + "output port polarity": "active high", + "input port name": "din0", + "input port polarity": "active high", + "chip enable port name": "csb0", + "chip enable port polarity": "active low", + "mask port name": "wmask0", + "mask port polarity": "active high", + "mask granularity": 8 + } + ], + "extra ports": [ + { + "name": "clk1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "csb1", + "width": 1, + "type": "constant", + "value": 0 + }, + { + "name": "addr1", + "width": 11, + "type": "constant", + "value": 0 + } + ] + }, + { + "type": "sram", + "name": "sky130_sram_2kbyte_1rw1r_32x512_8", + "depth": "512", "width": 32, "family": "1rw", "mask": "true", From 53dc89d8c348e2b469639a22cd17d8500251e58b Mon Sep 17 00:00:00 2001 From: Dan Fritchman Date: Thu, 17 Jun 2021 22:01:02 -0700 Subject: [PATCH 48/81] Bug-fix unused port widths on Sky130 SRAMs --- src/hammer-vlsi/technology/sky130/sram-cache.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json index 5c05e5d2b..fa459914a 100644 --- a/src/hammer-vlsi/technology/sky130/sram-cache.json +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -41,7 +41,7 @@ }, { "name": "addr1", - "width": 11, + "width": 10, "type": "constant", "value": 0 } @@ -89,7 +89,7 @@ }, { "name": "addr1", - "width": 11, + "width": 8, "type": "constant", "value": 0 } @@ -137,7 +137,7 @@ }, { "name": "addr1", - "width": 11, + "width": 9, "type": "constant", "value": 0 } From a689f77bf4357418ad0d83a04481dc51cb52d84c Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 26 Jul 2021 16:25:36 -0700 Subject: [PATCH 49/81] sky130 plugin updates from tapeout --- src/hammer-vlsi/technology/sky130/__init__.py | 130 +++++++++++++++--- .../technology/sky130/defaults.yml | 21 +-- .../technology/sky130/sky130.tech.json | 55 ++++---- 3 files changed, 148 insertions(+), 58 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 898d814dd..f5778840c 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -26,8 +26,8 @@ def post_install_script(self) -> None: self.library_name = 'sky130_fd_sc_hd' self.setup_sram_cdl() self.setup_cdl() + self.setup_verilog() self.setup_techlef() - self.setup_layermap() self.setup_lvs_deck() print('Loaded Sky130 Tech') @@ -70,6 +70,7 @@ def setup_sram_cdl(self) -> None: # Tech setup steps def setup_cdl(self) -> None: """ Copy and hack the cdl, replacing pfet_01v8_hvt/nfet_01v8 with phighvt/nshort """ + # TODO: figure out how to rename the devices to pass Calibre LVS setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) cdl_old_path = setting_dir / 'libs.ref' / self.library_name / 'cdl' / f'{self.library_name}.cdl' @@ -88,6 +89,26 @@ def setup_cdl(self) -> None: f_new.write(line) f_old.close() f_new.close() + + def setup_verilog(self) -> None: + """ Copy and hack the verilog """ + setting_dir = self.get_setting("technology.sky130.sky130A") + setting_dir = Path(setting_dir) + verilog_old_path = setting_dir / 'libs.ref' / self.library_name / 'verilog' / f'{self.library_name}.v' + if not verilog_old_path.exists(): + raise FileNotFoundError(f"Verilog not found: {verilog_old_path}") + + cache_tech_dir_path = Path(self.cache_dir) + os.makedirs(cache_tech_dir_path, exist_ok=True) + verilog_new_path = cache_tech_dir_path / f'{self.library_name}.v' + + f_old = open(verilog_old_path,'r') + f_new = open(verilog_new_path,'w') + for line in f_old: + line = line.replace('wire 1','// wire 1') + f_new.write(line) + f_old.close() + f_new.close() def setup_techlef(self) -> None: """ Copy and hack the tech-lef, adding this very important `licon` section """ @@ -110,16 +131,16 @@ def setup_techlef(self) -> None: f_old.close() f_new.close() - def setup_layermap(self) -> None: - """ Copy the layer-map into `self.cache_dir` """ - nda_dir = self.get_setting("technology.sky130.sky130_nda") - nda_dir = Path(nda_dir) - layermap = nda_dir / "s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap" - if not layermap.exists(): - raise FileNotFoundError(f"Layer-map not found: {layermap}") - cache_path = Path(self.cache_dir) - os.makedirs(cache_path, exist_ok=True) - shutil.copy(layermap, cache_path) + # def setup_layermap(self) -> None: + # """ Copy the layer-map into `self.cache_dir` """ + # nda_dir = self.get_setting("technology.sky130.sky130_nda") + # nda_dir = Path(nda_dir) + # layermap = nda_dir / "s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap" + # if not layermap.exists(): + # raise FileNotFoundError(f"Layer-map not found: {layermap}") + # cache_path = Path(self.cache_dir) + # os.makedirs(cache_path, exist_ok=True) + # shutil.copy(layermap, cache_path) def setup_lvs_deck(self) -> None: """Remove conflicting specification statements found in PDK LVS decks.""" @@ -142,7 +163,7 @@ def setup_lvs_deck(self) -> None: self.logger.info("Modifying LVS deck: {} -> {}".format (source_path, dest_path)) df.write(matcher.sub("", sf.read())) - df.write(LVS_DECK_INSERT_LINES) + # df.write(LVS_DECK_INSERT_LINES) def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ @@ -151,10 +172,6 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), HammerTool.make_post_insertion_hook("place_opt_design", sky130_add_tieoffs), HammerTool.make_pre_insertion_hook("write_design", sky130_connect_nets), - #HammerTool.make_replacement_hook("power_straps", intech22_innovus.intech22_reference_power_straps), - # HammerTool.make_post_insertion_hook("power_straps", intech22_innovus.intech22_m2_staples), - # HammerTool.make_pre_insertion_hook("clock_tree", intech22_innovus.intech22_cts_options), - # HammerTool.make_replacement_hook("add_fillers", intech22_innovus.intech22_add_fillers), ]} return hooks.get(tool_name, []) @@ -178,11 +195,25 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: LVS_DECK_INSERT_LINES = ''' LVS FILTER D OPEN SOURCE LVS FILTER D OPEN LAYOUT - ''' + # TODO: black boxing sram is temporary!! for name in SKY130Tech.openram_sram_names(): LVS_DECK_INSERT_LINES += f"LVS BOX {name} \n" + LVS_DECK_INSERT_LINES += f"LVS FILTER {name} OPEN \n" + +# EXCLUDE CELL sky130_sram_1kbyte_1rw1r_32x256_8 +# EXCLUDE CELL sky130_sram_1kbyte_1rw1r_8x1024_8 +# EXCLUDE CELL sky130_sram_2kbyte_1rw1r_32x512_8 + +# LVS BOX sky130_sram_1kbyte_1rw1r_32x256_8 +# LVS BOX sky130_sram_1kbyte_1rw1r_8x1024_8 +# LVS BOX sky130_sram_2kbyte_1rw1r_32x512_8 + +# LVS FILTER sky130_sram_1kbyte_1rw1r_32x256_8 OPEN +# LVS FILTER sky130_sram_1kbyte_1rw1r_8x1024_8 OPEN +# LVS FILTER sky130_sram_2kbyte_1rw1r_32x512_8 OPEN + # various Innovus database settings def sky130_innovus_settings(ht: HammerTool) -> bool: @@ -192,6 +223,47 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: """Settings for every tool invocation""" ht.append( ''' + +########################################################## +# Placement attributes [get_db -category place] +########################################################## +#------------------------------------------------------------------------------- +set_db place_global_place_io_pins true + +set_db opt_honor_fences true +set_db place_detail_dpt_flow true +set_db place_detail_color_aware_legal true +set_db place_global_solver_effort high +set_db place_detail_check_cut_spacing true +set_db place_global_cong_effort high + +########################################################## +# Optimization attributes [get_db -category opt] +########################################################## +#------------------------------------------------------------------------------- + +set_db opt_fix_fanout_load true +set_db opt_clock_gate_aware false +set_db opt_area_recovery true +set_db opt_post_route_area_reclaim setup_aware +set_db opt_fix_hold_verbose true +# set_db opt_fix_hold_lib_cells "BUFFD0BWP30P140HVT BUFFD1BWP30P140HVT BUFFD2BWP30P140HVT BUFFD3BWP30P140HVT BUFFD4BWP30P140HVT BUFFD6BWP30P140HVT BUFFD8BWP30P140HVT BUFFD12BWP30P140HVT BUFFD16BWP30P140HVT BUFFD20BWP30P140HVT BUFFD24BWP30P140HVT DEL025D1BWP30P140HVT" + + +########################################################## +# Clock attributes [get_db -category cts] +########################################################## +#------------------------------------------------------------------------------- +#set_db cts_target_skew .15 +#set_db cts_target_max_transition_time .3 +#set_db cts_update_io_latency false + +# set_db cts_use_inverters true +# set_db cts_buffer_cells "clkbuf clkdlybuf4s15 clkdlybuf4s18 clkdlybuf4s25 clkdlybuf4s50" +# set_db cts_inverter_cells "clkinv clkinvlp" +# set_db cts_clock_gating_cells "CKLHQD1BWP30P140HVT CKLHQD2BWP30P140HVT CKLHQD3BWP30P140HVT CKLHQD4BWP30P140HVT CKLHQD6BWP30P140HVT CKLHQD8BWP30P140HVT CKLHQD12BWP30P140HVT CKLHQD16BWP30P140HVT CKLHQD20BWP30P140HVT CKLHQD24BWP30P140HVT CKLNQD1BWP30P140HVT CKLNQD2BWP30P140HVT CKLNQD3BWP30P140HVT CKLNQD4BWP30P140HVT CKLNQD6BWP30P140HVT CKLNQD8BWP30P140HVT CKLNQD12BWP30P140HVT CKLNQD16BWP30P140HVT CKLNQD20BWP30P140HVT CKLNQD24BWP30P140HVT" + + ########################################################## # Routing attributes [get_db -category route] ########################################################## @@ -199,6 +271,19 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: set_db route_design_antenna_diode_insertion 1 set_db route_design_antenna_cell_name "sky130_fd_sc_hd__diode_2" set_db route_design_bottom_routing_layer 2 + +set_db route_design_high_freq_search_repair true +set_db route_design_detail_post_route_spread_wire true +set_db route_design_with_si_driven true +set_db route_design_with_timing_driven true +set_db route_design_concurrent_minimize_via_count_effort high +set_db opt_consider_routing_congestion true +set_db route_design_detail_use_multi_cut_via_effort medium + +set_db cts_target_skew 0.03 +set_db cts_max_fanout 10 +set_db opt_setup_target_slack 0.10 +set_db opt_hold_target_slack 0.10 ''' ) return True @@ -235,6 +320,17 @@ def sky130_power_nets(ht: HammerTool) -> bool: ) return True +def sky130_remove_route_blockages(ht: HammerTool) -> bool: + assert isinstance( + ht, HammerPlaceAndRouteTool + ), "removing blockages can only run on par" + ht.append( + ''' +delete_route_blockages -layers {met1 met4} + ''' + ) + return True + # TODO: add these two functions into Hammer Innovus plugin def sky130_add_tieoffs(ht: HammerTool) -> bool: assert isinstance( diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index ac0148d08..4de5e751c 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -28,16 +28,18 @@ vlsi: # Supply voltages. # TODO: add ability to tie pin to net in Hammer Innovus plugin supplies: - power: [ {name: "VDD", pin: "VDD"}] - # {name: "VPWR", pin: "VPWR", tie: "VDD"}, - # {name: "VPB", pin: "VPB", tie: "VDD"}] - ground: [ {name: "VSS", pin: "VSS"}] - # {name: "VGND", pin: "VGND", tie: "VSS"}, - # {name: "VNB", pin: "VNB", tie: "VSS"}] + power: [ {name: "VDD", pin: "VDD"}] + {name: "VPWR", pin: "VPWR", tie: "VDD"}, + {name: "VPB", pin: "VPB" , tie: "VDD"}] + ground: [ {name: "VSS", pin: "VSS"}] + {name: "VGND", pin: "VGND", tie: "VSS"}, + {name: "VNB", pin: "VNB" , tie: "VSS"}] VDD: "1.8 V" GND: "0 V" - dont_use_list: ["*sdf*"] # Scan flops go haywire! Avoid them. + # moved these to json + # dont_use_mode: append + # dont_use_list: ["*sdf*","sky130_fd_sc_hd__probe_p_8"] # Scan flops go haywire! Avoid them. # mmmc corners config mmmc_corners: [ @@ -63,8 +65,7 @@ vlsi: bump_block_cut_layer: "via4" # Set the interval and offset for tap cells - # interval value from the eFPGA---RTL-to-GDS-with-SKY130 - tap_cell_interval: "40" + tap_cell_interval: "15" tap_cell_offset: "5" technology.core: @@ -74,7 +75,7 @@ technology.core: # Note that this is not usually stackup specific; it is based on the std cell libraries themselves std_cell_rail_layer: "met1" # This is used to provide a reference master for generating standard cells - tap_cell_rail_reference: "{sky130_fd_sc_hd__tap*}" + tap_cell_rail_reference: "sky130_fd_sc_hd__tap*" par.inputs: gds_merge: true diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 0c19cf51a..6f802e769 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -26,6 +26,7 @@ ], "gds map file": "$GDS_MAP_FILE", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "other layermap file": "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/VirtuosoOA/libs/s8phirs_10r/s8phirs_10r.layermap", "drc decks": [ { "tool name": "calibre", @@ -33,6 +34,7 @@ "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" } ], + "new additional_drc_text": "EXCLUDE CELL sky130_sram_1kbyte_1rw1r_32x256_8 \n EXCLUDE CELL sky130_sram_1kbyte_1rw1r_8x1024_8 \n EXCLUDE CELL sky130_sram_2kbyte_1rw1r_32x512_8", "additional_drc_text": "", "lvs decks": [ { @@ -42,7 +44,8 @@ "path": "tech-sky130-cache/lvsControlFile_s8" } ], - "additional_lvs_text": "", + "old additional_lvs_text": "LVS FILTER D OPEN SOURCE \n LVS FILTER D OPEN LAYOUT \n LVS BOX sky130_sram_1kbyte_1rw1r_32x256_8 \n LVS BOX sky130_sram_2kbyte_1rw1r_32x512_8", + "additional_lvs_text": "LVS FILTER D OPEN SOURCE \nLVS FILTER D OPEN LAYOUT \nLVS BOX sky130_sram_1kbyte_1rw1r_32x256_8 \nLVS BOX sky130_sram_2kbyte_1rw1r_32x512_8 \nLVS FILTER sky130_sram_1kbyte_1rw1r_32x256_8 OPEN \nLVS FILTER sky130_sram_2kbyte_1rw1r_32x512_8 OPEN", "physical only cells list": [ "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", @@ -54,7 +57,7 @@ "sky130_fd_sc_hd__fill_8", "sky130_fd_sc_hd__diode_2" ], - "dont use list": [], + "dont use list": ["*sdf*","sky130_fd_sc_hd__probe_p_8"], "special cells": [ { "cell_type": "tapcell", @@ -94,16 +97,17 @@ ] }, { - "spice file": "/tools/B/nayiri/sky130/chipyard-osci-sky130/vlsi/sky130-files/devices.cdl", + "spice file": "tech-sky130-cache/sky130-files/devices.cdl", + "verilog sim fake": "tech-sky130-cache/primitives.v", "provides": [ { - "lib_type": "technology" + "lib_type": "extra stuffs" } ] }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -125,7 +129,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -147,7 +151,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -169,7 +173,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -191,7 +195,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -213,7 +217,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -235,7 +239,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -257,7 +261,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -279,7 +283,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -301,7 +305,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -323,7 +327,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -345,7 +349,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -367,7 +371,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -389,7 +393,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -411,7 +415,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -433,7 +437,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -452,17 +456,6 @@ "vt": "RVT" } ] - }, - { - "lef file": "$SKY130A/libs.ref/sky130_fd_pr/lef/sky130_fd_pr.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_pr/cdl/sky130_fd_pr.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_pr/gds/sky130_fd_pr.gds", - "provides": [ - { - "lib_type": "primitives", - "vt": "RVT" - } - ] } ], "stackups": [ From f62caadd8c27b1de754e022272ae95182e9596d1 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 26 Jul 2021 16:31:05 -0700 Subject: [PATCH 50/81] files to generate sky130.tech.json --- .../technology/sky130/tech-json/README | 4 + .../sky130/tech-json/beginning.json | 76 +++ .../sky130/tech-json/generate_json.py | 98 +++ .../technology/sky130/tech-json/sites.json | 6 + .../sky130/tech-json/sky130.tech.json | 585 ++++++++++++++++++ .../technology/sky130/tech-json/stackup.json | 11 + 6 files changed, 780 insertions(+) create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/README create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/beginning.json create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/generate_json.py create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/sites.json create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/stackup.json diff --git a/src/hammer-vlsi/technology/sky130/tech-json/README b/src/hammer-vlsi/technology/sky130/tech-json/README new file mode 100644 index 000000000..e42cce3f5 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/README @@ -0,0 +1,4 @@ +Make sure $HAMMER_HOME points to the Hammer install you're using with Sky130. +Then run: + >> python generate_json.py +This writes the tech json file to ./sky130.tech.json and $HAMMER_HOME/src/hammer-vlsi/technology/sky130/sky130.tech.json diff --git a/src/hammer-vlsi/technology/sky130/tech-json/beginning.json b/src/hammer-vlsi/technology/sky130/tech-json/beginning.json new file mode 100644 index 000000000..8bf75d7a5 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/beginning.json @@ -0,0 +1,76 @@ +{ + "name": "Skywater 130nm Library", + "grid_unit": "0.001", + "time_unit": "1 ps", + "installs": [ + { + "path": "$SKY130_PDK", + "base var": "technology.sky130.sky130_pdk" + }, + { + "path": "$SKY130_NDA", + "base var": "technology.sky130.sky130_nda" + }, + { + "path": "$SKY130A", + "base var": "technology.sky130.sky130A" + }, + { + "path": "$GDS_MAP_FILE", + "base var": "technology.sky130.gds_map_file" + }, + { + "path": "tech-sky130-cache", + "base var": "" + } + ], + "gds map file": "$GDS_MAP_FILE", + "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "drc decks": [ + { + "tool name": "calibre", + "deck name": "all_drc", + "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" + } + ], + "additional_drc_text": "", + + "lvs decks": [ + { + "tool name": "calibre", + "deck name": "all_lvs", + "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", + "path": "tech-sky130-cache/lvsControlFile_s8" + } + ], + "additional_lvs_text": "", + + "physical only cells list": [ + "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", + "sky130_fd_sc_hd__tapvgnd_1", + "sky130_fd_sc_hd__tapvpwrvgnd_1", + "sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__diode_2" + ], + "dont use list": [], + "special cells": [ + {"cell_type": "tapcell", "name": ["sky130_fd_sc_hd__tapvpwrvgnd_1"]}, + {"cell_type": "stdfiller", "name": ["sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8"]}, + {"cell_type": "tiehilocell", "name": ["sky130_fd_sc_hd__conb_1"]} + ], + + "libraries": [ + { + "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", + "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", + "provides": [ + { + "lib_type": "technology" + } + ] + } + ] +} \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py b/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py new file mode 100644 index 000000000..135766e9f --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py @@ -0,0 +1,98 @@ +import json +import os +from pathlib import Path +data = {} + +HAMMER_HOME = os.getenv('HAMMER_HOME') +SKY130A = os.getenv('SKY130A') +JSON_PATH = os.path.join(HAMMER_HOME,'src/hammer-vlsi/technology/sky130/sky130.tech.json') + + +library='sky130_fd_sc_hd' + +with open('beginning.json', 'r') as f: + data = json.load(f) + +SKYWATER_LIBS = os.path.join('$SKY130A','libs.ref',library) +LIBRARY_PATH = os.path.join(SKY130A,'libs.ref',library,'lib') +lib_corners=os.listdir(LIBRARY_PATH) +for cornerfilename in lib_corners: + if (not (library in cornerfilename) ) : continue + if ('ccsnoise' in cornerfilename): continue + + tmp = cornerfilename.replace('.lib','__') + cornername = tmp.split('__')[1] + cornerparts = cornername.split('_') + + speed = cornerparts[0] + if (speed == 'ff'): speed = 'fast' + if (speed == 'tt'): speed = 'typical' + if (speed == 'ss'): speed = 'slow' + + temp = cornerparts[1] + temp = temp.replace('n','-') + temp = temp.split('C')[0]+' C' + + vdd = cornerparts[2] + vdd = vdd.split('v') + vdd = vdd[0]+'.'+vdd[1]+' V' + + lib_entry = { + "nldm liberty file": os.path.join(SKYWATER_LIBS,'lib', cornerfilename), + "verilog sim": os.path.join(SKYWATER_LIBS,'verilog', library+'.v'), + # maybe this instead: + # "verilog sim": os.path.join('tech-sky130-cache', library+'.v'), + "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), + "spice file": os.path.join('tech-sky130-cache', library+'.cdl'), + "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), + "corner": { + "nmos": speed, + "pmos": speed, + "temperature": temp + }, + "supplies": { + "VDD": vdd, + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + } + + data["libraries"].append(lib_entry) + +stackups = {} +with open('stackup.json', 'r') as f: + stackups = json.load(f) +stackups["name"] = library +data["stackups"] = [stackups] + +library='sky130_fd_pr' +SKYWATER_LIBS=os.path.join('$SKY130A',"libs.ref",library) +lib_entry = { + "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), + "spice file": os.path.join(SKYWATER_LIBS,'cdl', library+'.cdl'), + "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), + "provides": [ + { + "lib_type": "primitives", + "vt": "RVT" + } + ] +} + +data["libraries"].append(lib_entry) + +sites = {} +with open('sites.json', 'r') as f: + sites = json.load(f) +data["sites"] = sites["sites"] + +with open('sky130.tech.json', 'w') as f: + json.dump(data, f, indent=2) + +# with open(os.path.join(JSON_PATH), 'w') as f: +# json.dump(data, f, indent=2) \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/tech-json/sites.json b/src/hammer-vlsi/technology/sky130/tech-json/sites.json new file mode 100644 index 000000000..e243250cb --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/sites.json @@ -0,0 +1,6 @@ +{ + "sites": [ + {"name": "unithd", "x": 0.46, "y": 2.72}, + {"name": "unithddbl", "x": 0.46, "y": 5.44} + ] +} \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json b/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json new file mode 100644 index 000000000..f244ff46e --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json @@ -0,0 +1,585 @@ +{ + "name": "Skywater 130nm Library", + "grid_unit": "0.001", + "time_unit": "1 ps", + "installs": [ + { + "path": "$SKY130_PDK", + "base var": "technology.sky130.sky130_pdk" + }, + { + "path": "$SKY130_NDA", + "base var": "technology.sky130.sky130_nda" + }, + { + "path": "$SKY130A", + "base var": "technology.sky130.sky130A" + }, + { + "path": "$GDS_MAP_FILE", + "base var": "technology.sky130.gds_map_file" + }, + { + "path": "tech-sky130-cache", + "base var": "" + } + ], + "gds map file": "$GDS_MAP_FILE", + "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "drc decks": [ + { + "tool name": "calibre", + "deck name": "all_drc", + "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" + } + ], + "additional_drc_text": "", + "lvs decks": [ + { + "tool name": "calibre", + "deck name": "all_lvs", + "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", + "path": "tech-sky130-cache/lvsControlFile_s8" + } + ], + "additional_lvs_text": "", + "physical only cells list": [ + "sky130_fd_sc_hd__tap_1", + "sky130_fd_sc_hd__tap_2", + "sky130_fd_sc_hd__tapvgnd_1", + "sky130_fd_sc_hd__tapvpwrvgnd_1", + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__diode_2" + ], + "dont use list": [], + "special cells": [ + { + "cell_type": "tapcell", + "name": [ + "sky130_fd_sc_hd__tapvpwrvgnd_1" + ] + }, + { + "cell_type": "stdfiller", + "name": [ + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__decap_12", + "sky130_fd_sc_hd__decap_3", + "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", + "sky130_fd_sc_hd__decap_8" + ] + }, + { + "cell_type": "tiehilocell", + "name": [ + "sky130_fd_sc_hd__conb_1" + ] + } + ], + "libraries": [ + { + "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", + "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", + "provides": [ + { + "lib_type": "technology" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.65 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.95 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.56 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.65 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.76 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "fast", + "pmos": "fast", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.95 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.40 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.60 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.28 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.35 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.40 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.44 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.60 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "slow", + "pmos": "slow", + "temperature": "-40 C" + }, + "supplies": { + "VDD": "1.76 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "typical", + "pmos": "typical", + "temperature": "025 C" + }, + "supplies": { + "VDD": "1.80 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", + "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", + "corner": { + "nmos": "typical", + "pmos": "typical", + "temperature": "100 C" + }, + "supplies": { + "VDD": "1.80 V", + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + }, + { + "lef file": "$SKY130A/libs.ref/sky130_fd_pr/lef/sky130_fd_pr.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_pr/cdl/sky130_fd_pr.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_pr/gds/sky130_fd_pr.gds", + "provides": [ + { + "lib_type": "primitives", + "vt": "RVT" + } + ] + } + ], + "stackups": [ + { + "name": "sky130_fd_sc_hd", + "metals": [ + { + "name": "li1", + "index": 1, + "direction": "vertical", + "min_width": 0.17, + "max_width": 2147483.647, + "pitch": 0.34, + "offset": 0.23, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.17 + } + ] + }, + { + "name": "met1", + "index": 2, + "direction": "horizontal", + "min_width": 0.14, + "max_width": 2147483.647, + "pitch": 0.28, + "offset": 0.17, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.14 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.28 + } + ] + }, + { + "name": "met2", + "index": 3, + "direction": "vertical", + "min_width": 0.14, + "max_width": 2147483.647, + "pitch": 0.28, + "offset": 0.23, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.14 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.28 + } + ] + }, + { + "name": "met3", + "index": 4, + "direction": "horizontal", + "min_width": 0.3, + "max_width": 2147483.647, + "pitch": 0.6, + "offset": 0.34, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.3 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.4 + } + ] + }, + { + "name": "met4", + "index": 5, + "direction": "vertical", + "min_width": 0.3, + "max_width": 2147483.647, + "pitch": 0.6, + "offset": 0.46, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 0.3 + }, + { + "width_at_least": 3.0, + "min_spacing": 0.4 + } + ] + }, + { + "name": "met5", + "index": 6, + "direction": "horizontal", + "min_width": 1.6, + "max_width": 2147483.647, + "pitch": 3.2, + "offset": 1.7, + "power_strap_widths_and_spacings": [ + { + "width_at_least": 0.0, + "min_spacing": 1.6 + } + ] + } + ] + } + ], + "sites": [ + { + "name": "unithd", + "x": 0.46, + "y": 2.72 + }, + { + "name": "unithddbl", + "x": 0.46, + "y": 5.44 + } + ] +} \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/tech-json/stackup.json b/src/hammer-vlsi/technology/sky130/tech-json/stackup.json new file mode 100644 index 000000000..13914d9d8 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/stackup.json @@ -0,0 +1,11 @@ + { + "name" : "TODO", + "metals": [ + {"name": "li1", "index": 1, "direction": "vertical", "min_width": 0.17, "max_width": 2147483.647, "pitch": 0.34, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.17}]}, + {"name": "met1", "index": 2, "direction": "horizontal", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.17, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, + {"name": "met2", "index": 3, "direction": "vertical", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, + {"name": "met3", "index": 4, "direction": "horizontal", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.34, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, + {"name": "met4", "index": 5, "direction": "vertical", "min_width": 0.3, "max_width": 2147483.647, "pitch": 0.6, "offset": 0.46, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.3}, {"width_at_least": 3.0, "min_spacing": 0.4}]}, + {"name": "met5", "index": 6, "direction": "horizontal", "min_width": 1.6, "max_width": 2147483.647, "pitch": 3.2, "offset": 1.7, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 1.6}]} + ] + } From cfbf0debf73fd2300448b707711c82466181d1c5 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Thu, 29 Jul 2021 14:54:40 -0700 Subject: [PATCH 51/81] last sky130 plugin tweaks --- src/hammer-vlsi/technology/sky130/__init__.py | 16 ++-------------- src/hammer-vlsi/technology/sky130/defaults.yml | 4 ++-- 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index f5778840c..0876047c6 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -66,7 +66,6 @@ def setup_sram_cdl(self) -> None: line = line.replace('sky130_fd_pr__nfet_01v8','nshort') f_new.write(line) - # Tech setup steps def setup_cdl(self) -> None: """ Copy and hack the cdl, replacing pfet_01v8_hvt/nfet_01v8 with phighvt/nshort """ @@ -131,17 +130,6 @@ def setup_techlef(self) -> None: f_old.close() f_new.close() - # def setup_layermap(self) -> None: - # """ Copy the layer-map into `self.cache_dir` """ - # nda_dir = self.get_setting("technology.sky130.sky130_nda") - # nda_dir = Path(nda_dir) - # layermap = nda_dir / "s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap" - # if not layermap.exists(): - # raise FileNotFoundError(f"Layer-map not found: {layermap}") - # cache_path = Path(self.cache_dir) - # os.makedirs(cache_path, exist_ok=True) - # shutil.copy(layermap, cache_path) - def setup_lvs_deck(self) -> None: """Remove conflicting specification statements found in PDK LVS decks.""" pattern = '.*({}).*\n'.format('|'.join(LVS_DECK_SCRUB_LINES)) @@ -163,7 +151,7 @@ def setup_lvs_deck(self) -> None: self.logger.info("Modifying LVS deck: {} -> {}".format (source_path, dest_path)) df.write(matcher.sub("", sf.read())) - # df.write(LVS_DECK_INSERT_LINES) + df.write(LVS_DECK_INSERT_LINES) def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ @@ -290,7 +278,7 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: -# reference: /tools/commercial/skywater/swtech130/skywater-src-nda/scs8hd/V0.0.2/scripts +# from NDA scripts def sky130_add_endcaps(ht: HammerTool) -> bool: assert isinstance( ht, HammerPlaceAndRouteTool diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index 4de5e751c..c30dc942c 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -28,10 +28,10 @@ vlsi: # Supply voltages. # TODO: add ability to tie pin to net in Hammer Innovus plugin supplies: - power: [ {name: "VDD", pin: "VDD"}] + power: [ {name: "VDD", pin: "VDD"}, {name: "VPWR", pin: "VPWR", tie: "VDD"}, {name: "VPB", pin: "VPB" , tie: "VDD"}] - ground: [ {name: "VSS", pin: "VSS"}] + ground: [ {name: "VSS", pin: "VSS"}, {name: "VGND", pin: "VGND", tie: "VSS"}, {name: "VNB", pin: "VNB" , tie: "VSS"}] VDD: "1.8 V" From 8b56b7cb7beb329cf9f84b31cf8196dc229dc572 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 30 Jul 2021 15:31:51 -0700 Subject: [PATCH 52/81] changed underscore to dash in name --- .../technology/sky130/tech-json/README | 2 +- .../sky130/tech-json/generate-json.py | 98 +++++++++++++++++++ 2 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 src/hammer-vlsi/technology/sky130/tech-json/generate-json.py diff --git a/src/hammer-vlsi/technology/sky130/tech-json/README b/src/hammer-vlsi/technology/sky130/tech-json/README index e42cce3f5..b7c6df966 100644 --- a/src/hammer-vlsi/technology/sky130/tech-json/README +++ b/src/hammer-vlsi/technology/sky130/tech-json/README @@ -1,4 +1,4 @@ Make sure $HAMMER_HOME points to the Hammer install you're using with Sky130. Then run: - >> python generate_json.py + >> python generate-json.py This writes the tech json file to ./sky130.tech.json and $HAMMER_HOME/src/hammer-vlsi/technology/sky130/sky130.tech.json diff --git a/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py b/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py new file mode 100644 index 000000000..135766e9f --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py @@ -0,0 +1,98 @@ +import json +import os +from pathlib import Path +data = {} + +HAMMER_HOME = os.getenv('HAMMER_HOME') +SKY130A = os.getenv('SKY130A') +JSON_PATH = os.path.join(HAMMER_HOME,'src/hammer-vlsi/technology/sky130/sky130.tech.json') + + +library='sky130_fd_sc_hd' + +with open('beginning.json', 'r') as f: + data = json.load(f) + +SKYWATER_LIBS = os.path.join('$SKY130A','libs.ref',library) +LIBRARY_PATH = os.path.join(SKY130A,'libs.ref',library,'lib') +lib_corners=os.listdir(LIBRARY_PATH) +for cornerfilename in lib_corners: + if (not (library in cornerfilename) ) : continue + if ('ccsnoise' in cornerfilename): continue + + tmp = cornerfilename.replace('.lib','__') + cornername = tmp.split('__')[1] + cornerparts = cornername.split('_') + + speed = cornerparts[0] + if (speed == 'ff'): speed = 'fast' + if (speed == 'tt'): speed = 'typical' + if (speed == 'ss'): speed = 'slow' + + temp = cornerparts[1] + temp = temp.replace('n','-') + temp = temp.split('C')[0]+' C' + + vdd = cornerparts[2] + vdd = vdd.split('v') + vdd = vdd[0]+'.'+vdd[1]+' V' + + lib_entry = { + "nldm liberty file": os.path.join(SKYWATER_LIBS,'lib', cornerfilename), + "verilog sim": os.path.join(SKYWATER_LIBS,'verilog', library+'.v'), + # maybe this instead: + # "verilog sim": os.path.join('tech-sky130-cache', library+'.v'), + "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), + "spice file": os.path.join('tech-sky130-cache', library+'.cdl'), + "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), + "corner": { + "nmos": speed, + "pmos": speed, + "temperature": temp + }, + "supplies": { + "VDD": vdd, + "GND": "0 V" + }, + "provides": [ + { + "lib_type": "stdcell", + "vt": "RVT" + } + ] + } + + data["libraries"].append(lib_entry) + +stackups = {} +with open('stackup.json', 'r') as f: + stackups = json.load(f) +stackups["name"] = library +data["stackups"] = [stackups] + +library='sky130_fd_pr' +SKYWATER_LIBS=os.path.join('$SKY130A',"libs.ref",library) +lib_entry = { + "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), + "spice file": os.path.join(SKYWATER_LIBS,'cdl', library+'.cdl'), + "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), + "provides": [ + { + "lib_type": "primitives", + "vt": "RVT" + } + ] +} + +data["libraries"].append(lib_entry) + +sites = {} +with open('sites.json', 'r') as f: + sites = json.load(f) +data["sites"] = sites["sites"] + +with open('sky130.tech.json', 'w') as f: + json.dump(data, f, indent=2) + +# with open(os.path.join(JSON_PATH), 'w') as f: +# json.dump(data, f, indent=2) \ No newline at end of file From 2576010aa968fb748335f9111b5a30ca5a4e4848 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 30 Jul 2021 15:32:49 -0700 Subject: [PATCH 53/81] changed underscore to dash in name --- .../sky130/tech-json/generate_json.py | 98 ------------------- 1 file changed, 98 deletions(-) delete mode 100644 src/hammer-vlsi/technology/sky130/tech-json/generate_json.py diff --git a/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py b/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py deleted file mode 100644 index 135766e9f..000000000 --- a/src/hammer-vlsi/technology/sky130/tech-json/generate_json.py +++ /dev/null @@ -1,98 +0,0 @@ -import json -import os -from pathlib import Path -data = {} - -HAMMER_HOME = os.getenv('HAMMER_HOME') -SKY130A = os.getenv('SKY130A') -JSON_PATH = os.path.join(HAMMER_HOME,'src/hammer-vlsi/technology/sky130/sky130.tech.json') - - -library='sky130_fd_sc_hd' - -with open('beginning.json', 'r') as f: - data = json.load(f) - -SKYWATER_LIBS = os.path.join('$SKY130A','libs.ref',library) -LIBRARY_PATH = os.path.join(SKY130A,'libs.ref',library,'lib') -lib_corners=os.listdir(LIBRARY_PATH) -for cornerfilename in lib_corners: - if (not (library in cornerfilename) ) : continue - if ('ccsnoise' in cornerfilename): continue - - tmp = cornerfilename.replace('.lib','__') - cornername = tmp.split('__')[1] - cornerparts = cornername.split('_') - - speed = cornerparts[0] - if (speed == 'ff'): speed = 'fast' - if (speed == 'tt'): speed = 'typical' - if (speed == 'ss'): speed = 'slow' - - temp = cornerparts[1] - temp = temp.replace('n','-') - temp = temp.split('C')[0]+' C' - - vdd = cornerparts[2] - vdd = vdd.split('v') - vdd = vdd[0]+'.'+vdd[1]+' V' - - lib_entry = { - "nldm liberty file": os.path.join(SKYWATER_LIBS,'lib', cornerfilename), - "verilog sim": os.path.join(SKYWATER_LIBS,'verilog', library+'.v'), - # maybe this instead: - # "verilog sim": os.path.join('tech-sky130-cache', library+'.v'), - "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), - "spice file": os.path.join('tech-sky130-cache', library+'.cdl'), - "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), - "corner": { - "nmos": speed, - "pmos": speed, - "temperature": temp - }, - "supplies": { - "VDD": vdd, - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - } - - data["libraries"].append(lib_entry) - -stackups = {} -with open('stackup.json', 'r') as f: - stackups = json.load(f) -stackups["name"] = library -data["stackups"] = [stackups] - -library='sky130_fd_pr' -SKYWATER_LIBS=os.path.join('$SKY130A',"libs.ref",library) -lib_entry = { - "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), - "spice file": os.path.join(SKYWATER_LIBS,'cdl', library+'.cdl'), - "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), - "provides": [ - { - "lib_type": "primitives", - "vt": "RVT" - } - ] -} - -data["libraries"].append(lib_entry) - -sites = {} -with open('sites.json', 'r') as f: - sites = json.load(f) -data["sites"] = sites["sites"] - -with open('sky130.tech.json', 'w') as f: - json.dump(data, f, indent=2) - -# with open(os.path.join(JSON_PATH), 'w') as f: -# json.dump(data, f, indent=2) \ No newline at end of file From b36a041673b17b807d67d9034a52ad437973d266 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 30 Jul 2021 16:18:19 -0700 Subject: [PATCH 54/81] fixed unit test bug with string formatting --- src/hammer-vlsi/technology/sky130/sram-cache-gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/sram-cache-gen.py b/src/hammer-vlsi/technology/sky130/sram-cache-gen.py index 9caf01c89..5f79353dd 100755 --- a/src/hammer-vlsi/technology/sky130/sram-cache-gen.py +++ b/src/hammer-vlsi/technology/sky130/sram-cache-gen.py @@ -84,7 +84,7 @@ def main(args: List[str]) -> int: "chip enable port polarity" : "active low", "mask port name" : "wmask0", "mask port polarity" : "active high", - "mask granularity" : 8 + "mask granularity" : {m} }}, {{ "address port name" : "addr1", "address port polarity" : "active high", From 3308f90ca9ce5da006cdb32d69d0d0ecc852ddb5 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 2 Aug 2021 09:58:06 -0700 Subject: [PATCH 55/81] minor tweaks --- .../technology/sky130/defaults.yml | 19 +++--- .../technology/sky130/sky130.tech.json | 61 +++++++++---------- .../technology/sky130/sky130_lefpin.map | 50 +++++++++++++++ .../sky130/tech-json/beginning.json | 2 +- .../sky130/tech-json/generate-json.py | 6 +- .../sky130/tech-json/sky130.tech.json | 2 +- 6 files changed, 95 insertions(+), 45 deletions(-) create mode 100644 src/hammer-vlsi/technology/sky130/sky130_lefpin.map diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index c30dc942c..7d98c087d 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -1,25 +1,28 @@ # Settings for the sky130 technology to be overriden by the project. technology.sky130: - sky130_pdk: "PATH_TO_SKY130_PDK" - sky130_nda: "PATH_TO_NDA_FILES" - sky130A: "PATH_TO_SKY130A_DIR" - dffram_lib: "PATH_TO_DFFRAM/Compiler/build" - openram_lib: "PATH_TO_sky130_fd_bd_sram/macros" + sky130_pdk: "PATH-TO-SKY130_PDK" + sky130_nda: "PATH-TO-skywater-src-nda" + sky130A: "PATH-TO-SKY130A_DIR" + openram_lib: "PATH-TO-sky130_fd_bd_sram/macros" + dffram_lib: "PATH-TO-DFFRAM/Compiler/build" # GDS map file path, not provided by efabless - gds_map_file: "sky130-files/sky130_lefpin.map" + gds_map_file: "hammer/src/hammer-vlsi/technology/sky130/sky130_lefpin.map" + gds_map_file_meta: lvs_deck_sources: - - "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" + - "${technology.sky130.sky130_nda}/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" + lvs_deck_sources_meta: lazysubst # Calibre environment variables mentor.extra_env_vars: - - PDK_HOME: "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1" + - PDK_HOME: "${technology.sky130_nda}/s8/V2.0.1" # Set some defaults for this technology. vlsi: # Technology dimension core: + technology: sky130 node: 130 sram_generator_tool: "sram_compiler" sram_generator_tool_path: ["${HAMMER_HOME}/src/hammer-vlsi/technology/sky130"] diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 6f802e769..3da392e6e 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -24,9 +24,8 @@ "base var": "" } ], - "gds map file": "$GDS_MAP_FILE", + "gds map file": "$GDS_MAP_FILE/", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", - "other layermap file": "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1/VirtuosoOA/libs/s8phirs_10r/s8phirs_10r.layermap", "drc decks": [ { "tool name": "calibre", @@ -34,7 +33,6 @@ "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" } ], - "new additional_drc_text": "EXCLUDE CELL sky130_sram_1kbyte_1rw1r_32x256_8 \n EXCLUDE CELL sky130_sram_1kbyte_1rw1r_8x1024_8 \n EXCLUDE CELL sky130_sram_2kbyte_1rw1r_32x512_8", "additional_drc_text": "", "lvs decks": [ { @@ -44,8 +42,7 @@ "path": "tech-sky130-cache/lvsControlFile_s8" } ], - "old additional_lvs_text": "LVS FILTER D OPEN SOURCE \n LVS FILTER D OPEN LAYOUT \n LVS BOX sky130_sram_1kbyte_1rw1r_32x256_8 \n LVS BOX sky130_sram_2kbyte_1rw1r_32x512_8", - "additional_lvs_text": "LVS FILTER D OPEN SOURCE \nLVS FILTER D OPEN LAYOUT \nLVS BOX sky130_sram_1kbyte_1rw1r_32x256_8 \nLVS BOX sky130_sram_2kbyte_1rw1r_32x512_8 \nLVS FILTER sky130_sram_1kbyte_1rw1r_32x256_8 OPEN \nLVS FILTER sky130_sram_2kbyte_1rw1r_32x512_8 OPEN", + "additional_lvs_text": "", "physical only cells list": [ "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", @@ -57,7 +54,7 @@ "sky130_fd_sc_hd__fill_8", "sky130_fd_sc_hd__diode_2" ], - "dont use list": ["*sdf*","sky130_fd_sc_hd__probe_p_8"], + "dont use list": [], "special cells": [ { "cell_type": "tapcell", @@ -96,18 +93,9 @@ } ] }, - { - "spice file": "tech-sky130-cache/sky130-files/devices.cdl", - "verilog sim fake": "tech-sky130-cache/primitives.v", - "provides": [ - { - "lib_type": "extra stuffs" - } - ] - }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -129,7 +117,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -151,7 +139,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -173,7 +161,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -195,7 +183,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -217,7 +205,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -239,7 +227,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -261,7 +249,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -283,7 +271,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -305,7 +293,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -327,7 +315,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -349,7 +337,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -371,7 +359,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -393,7 +381,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -415,7 +403,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -437,7 +425,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", - "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", + "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -456,6 +444,17 @@ "vt": "RVT" } ] + }, + { + "lef file": "$SKY130A/libs.ref/sky130_fd_pr/lef/sky130_fd_pr.lef", + "spice file": "$SKY130A/libs.ref/sky130_fd_pr/cdl/sky130_fd_pr.cdl", + "gds file": "$SKY130A/libs.ref/sky130_fd_pr/gds/sky130_fd_pr.gds", + "provides": [ + { + "lib_type": "primitives", + "vt": "RVT" + } + ] } ], "stackups": [ diff --git a/src/hammer-vlsi/technology/sky130/sky130_lefpin.map b/src/hammer-vlsi/technology/sky130/sky130_lefpin.map new file mode 100644 index 000000000..a2d5dd047 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sky130_lefpin.map @@ -0,0 +1,50 @@ +# CADENCE Stream layer mapping table for Skywater130nm +# + +poly NET,SPNET,VIA 66 20 +poly PIN 66 16 +licon1 VIA 66 44 +licon1 PIN 66 41 +licon1 NET 66 58 +li1 LEFPIN,LEFOBS,PIN,NET,SPNET,VIA 67 20 +li1 PIN 67 16 +mcon VIA 67 44 +mcon PIN 67 41 +mcon NET 67 58 + +met1 LEFPIN,LEFOBS,PIN,NET,SPNET,VIA 68 20 +met1 NET 68 23 +met1 PIN 68 16 +NAME met1/PIN,met1/LEFPIN 68 5 +via LEFPIN,LEFOBS,VIA 68 44 +via PIN 68 41 +via NET 68 58 + +met2 LEFPIN,LEFOBS,PIN,NET,SPNET,VIA 69 20 +met2 NET 69 23 +met2 PIN 69 16 +NAME met2/PIN,met2/LEFPIN 69 5 +via2 LEFPIN,LEFOBS,VIA 69 44 +via2 PIN 69 41 +via2 NET 69 58 + +met3 LEFPIN,LEFOBS,PIN,NET,SPNET,VIA 70 20 +met3 NET 70 23 +met3 PIN 70 16 +NAME met3/PIN,met3/LEFPIN 70 5 +via3 LEFPIN,LEFOBS,VIA 70 44 +via3 PIN 70 41 +via3 NET 70 58 + +met4 LEFPIN,LEFOBS,PIN,NET,SPNET,VIA 71 20 +met4 NET 71 23 +met4 PIN 71 16 +NAME met4/PIN,met4/LEFPIN 71 5 +via4 LEFPIN,LEFOBS,VIA 71 44 +via4 PIN 71 41 +via4 NET 71 58 + +met5 LEFPIN,LEFOBS,PIN,NET,SPNET,VIA 72 20 +met5 NET 72 23 +met5 PIN 72 16 +NAME met5/PIN,met5/LEFPIN 72 5 \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/tech-json/beginning.json b/src/hammer-vlsi/technology/sky130/tech-json/beginning.json index 8bf75d7a5..2b5ce8cae 100644 --- a/src/hammer-vlsi/technology/sky130/tech-json/beginning.json +++ b/src/hammer-vlsi/technology/sky130/tech-json/beginning.json @@ -24,7 +24,7 @@ "base var": "" } ], - "gds map file": "$GDS_MAP_FILE", + "gds map file": "$GDS_MAP_FILE/", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { diff --git a/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py b/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py index 135766e9f..484dc77ef 100644 --- a/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py +++ b/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py @@ -40,8 +40,6 @@ lib_entry = { "nldm liberty file": os.path.join(SKYWATER_LIBS,'lib', cornerfilename), "verilog sim": os.path.join(SKYWATER_LIBS,'verilog', library+'.v'), - # maybe this instead: - # "verilog sim": os.path.join('tech-sky130-cache', library+'.v'), "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), "spice file": os.path.join('tech-sky130-cache', library+'.cdl'), "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), @@ -94,5 +92,5 @@ with open('sky130.tech.json', 'w') as f: json.dump(data, f, indent=2) -# with open(os.path.join(JSON_PATH), 'w') as f: -# json.dump(data, f, indent=2) \ No newline at end of file +with open(os.path.join(JSON_PATH), 'w') as f: + json.dump(data, f, indent=2) \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json b/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json index f244ff46e..3da392e6e 100644 --- a/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json @@ -24,7 +24,7 @@ "base var": "" } ], - "gds map file": "$GDS_MAP_FILE", + "gds map file": "$GDS_MAP_FILE/", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { From 15108a9dd18a398a226b22b1b22ea6988d25b4fc Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 2 Aug 2021 10:16:06 -0700 Subject: [PATCH 56/81] adding README, fixed minor bugs --- src/hammer-vlsi/technology/sky130/README.md | 151 ++++++++++++++++++ .../technology/sky130/defaults.yml | 1 - .../technology/sky130/sky130.tech.json | 11 -- .../sky130/tech-json/generate-json.py | 29 ++-- 4 files changed, 165 insertions(+), 27 deletions(-) create mode 100644 src/hammer-vlsi/technology/sky130/README.md diff --git a/src/hammer-vlsi/technology/sky130/README.md b/src/hammer-vlsi/technology/sky130/README.md new file mode 100644 index 000000000..d9ccb01dc --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/README.md @@ -0,0 +1,151 @@ +Sky130 Technology Library +========================= +HAMMER now supports the Skywater 130nm Technology process. The `SkyWater Open Source PDK `__ is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit (PDK) and related resources, which can be used to create manufacturable designs at SkyWater’s facility. +The Skywater 130nm PDK files are located in a repo called `skywater-pdk `__. A tool called `Open-PDKs (open_pdks) `__ was developed to generate all the files typically found in a PDK. +Open-PDKs uses the contents in ``skywater-pdk``, and outputs files to a directory called ``sky130A``. + +`OpenLANE `__ is an open-source RTL to GDSII VLSI flow that supports Sky130. + + +Before setting up the Sky130 PDK, we recommend familiarizing yourself with the process's documentation, :ref:`VLSI/Sky130-Tutorial/Resources:summarized below`. + +PDK Structure +------------- + +OpenLANE expects a certain file structure for the Sky130 PDK. +We recommend adhering to this file structure for Hammer as well. +All the files reside in a root folder (named something like ``skywater`` or ``sky130``). +The environment variable ``$PDK_ROOT`` should be set to this folder's path: + +.. code-block:: shell + + export PDK_ROOT= + +``$PDK_ROOT`` contains the following: + +* ``skywater-pdk`` + + * Original PDK source files + +* ``open_pdks`` + + * install of Open-PDKs tool + +* ``sky130A`` + + * output files from Open-PDKs compilation process + +NDA Files +--------- +Using commercial VLSI tools with this process requires files that are currently under NDA. +If you have access to these, you will be able to use the Hammer VLSI flow out-of-the-box with the Sky130 process. +Some of these NDA files, such as the Calibre DRC/LVS decks, rely on the environment variable ``$PDK_HOME`` containing the path to the version of the NDA files you are using. +You may set it in the Hammer plugin, or as follows: + +.. code-block:: shell + + export PDK_HOME=/s8/ + +Prerequisites for PDK Setup +--------------------------- + +* `Magic `__ + + * required for ``open_pdks`` file generation + * tricky to install, closely follow the directions on the ``Install`` page of the website + + * as the directions indicate, you will likely need to manually specify the location of the Tcl/Tk package installation using ``--with-tcl`` and ``--with-tk`` + +PDK Setup +--------- +In ``$PDK_ROOT``, clone the skywater-pdk repo and generate the liberty files for each library: + +.. code-block:: shell + + git clone https://github.com/google/skywater-pdk.git + cd skywater-pdk + # Expect a large download! ~7GB at time of writing. + SUBMODULE_VERSION=latest make submodules -j3 || make submodules -j1 + # Regenerate liberty files + make timing + +Again in ``$PDK_ROOT``, clone the open_pdks repo and run the install process to generate the ``sky130A`` directory: + +.. code-block:: shell + + git clone https://github.com/RTimothyEdwards/open_pdks + cd open_pdks + ./configure \ + --enable-sky130-pdk=$PDK_ROOT/skywater-pdk/libraries \ + --with-sky130-local-path=$PDK_ROOT + make + make install + +OpenRAM SRAMs +------------- +TODO: add overview here + +Known DRC Issues +---------------- +The HAMMER flow generates DRC-clean digital logic when run with the Calibre DRC deck and SRAMs excluded. + +TODO: summarize issues with SRAMs and open-source Magic DRC checks. + +Resources +--------- +The good thing about this process being open-source is that most questions about the process are answerable through a google search. +The tradeoff is that the documentation is a bit of a mess, and is currently scattered over a few pages and Github repos. +We try to summarize these below. + +Git repos: + +* `SkyWater Open Source PDK `__ + + * Git repo of the main Skywater 130nm files + +* `Open-PDKs `__ + + * Git repo of Open-PDKs tool that compiles the Sky130 PDK + +* `Git repos on foss-eda-tools `__ + + * Additional useful repos, such as Berkeley Analog Generator (BAG) setup + +Documentation: + +* `SkyWater SKY130 PDK's documentation `__ + + * Main documentation site for the PDK + +* `Join the SkyWater PDK Slack Channel `__ + + * By far the best way to have questions about the process answered, with 80+ channels for different topics + +* `Skywater130 Standard Cell and Primitives Overview `__ + + * Additional useful documentation for the PDK + +* `FOSSi Foundation YouTube Channel `__ + + * Contains informational videos on the Sky130 process, OpenLANE flow, and Efabless Shuttle program + +SRAMs: + +* `OpenRAM `__ + + * Open-source static random access memory (SRAM) compiler + +* `OpenRAM pre-compiled macros `__ + + * Precompiled sizes are 1kbytes, 2kbytes and 4kbytes + +OpenLANE flow: + +* `OpenLANE `__ + + * Open-source RTL to GDSII flow + +* `Magic `__ + + * Open-source VLSI layout tool that handles DRC checks in OpenLANE + \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index 7d98c087d..a01fa59f6 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -8,7 +8,6 @@ technology.sky130: # GDS map file path, not provided by efabless gds_map_file: "hammer/src/hammer-vlsi/technology/sky130/sky130_lefpin.map" - gds_map_file_meta: lvs_deck_sources: - "${technology.sky130.sky130_nda}/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 3da392e6e..d0ddcecb8 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -444,17 +444,6 @@ "vt": "RVT" } ] - }, - { - "lef file": "$SKY130A/libs.ref/sky130_fd_pr/lef/sky130_fd_pr.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_pr/cdl/sky130_fd_pr.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_pr/gds/sky130_fd_pr.gds", - "provides": [ - { - "lib_type": "primitives", - "vt": "RVT" - } - ] } ], "stackups": [ diff --git a/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py b/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py index 484dc77ef..cdbd827b7 100644 --- a/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py +++ b/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py @@ -68,21 +68,20 @@ stackups["name"] = library data["stackups"] = [stackups] -library='sky130_fd_pr' -SKYWATER_LIBS=os.path.join('$SKY130A',"libs.ref",library) -lib_entry = { - "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), - "spice file": os.path.join(SKYWATER_LIBS,'cdl', library+'.cdl'), - "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), - "provides": [ - { - "lib_type": "primitives", - "vt": "RVT" - } - ] -} - -data["libraries"].append(lib_entry) +# library='sky130_fd_pr' +# SKYWATER_LIBS=os.path.join('$SKY130A',"libs.ref",library) +# lib_entry = { +# "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), +# "spice file": os.path.join(SKYWATER_LIBS,'cdl', library+'.cdl'), +# "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), +# "provides": [ +# { +# "lib_type": "primitives", +# "vt": "RVT" +# } +# ] +# } +# data["libraries"].append(lib_entry) sites = {} with open('sites.json', 'r') as f: From 41672a575984ebeea32234fe4834ca9c27659d02 Mon Sep 17 00:00:00 2001 From: Nayiri <38256927+nayiri-k@users.noreply.github.com> Date: Mon, 2 Aug 2021 10:25:53 -0700 Subject: [PATCH 57/81] Update README.md --- src/hammer-vlsi/technology/sky130/README.md | 45 +++++++++------------ 1 file changed, 18 insertions(+), 27 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/README.md b/src/hammer-vlsi/technology/sky130/README.md index d9ccb01dc..4e87eebe9 100644 --- a/src/hammer-vlsi/technology/sky130/README.md +++ b/src/hammer-vlsi/technology/sky130/README.md @@ -1,13 +1,13 @@ Sky130 Technology Library ========================= -HAMMER now supports the Skywater 130nm Technology process. The `SkyWater Open Source PDK `__ is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit (PDK) and related resources, which can be used to create manufacturable designs at SkyWater’s facility. -The Skywater 130nm PDK files are located in a repo called `skywater-pdk `__. A tool called `Open-PDKs (open_pdks) `__ was developed to generate all the files typically found in a PDK. +HAMMER now supports the Skywater 130nm Technology process. The [SkyWater Open Source PDK](https://skywater-pdk.readthedocs.io/) is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit (PDK) and related resources, which can be used to create manufacturable designs at SkyWater’s facility. +The Skywater 130nm PDK files are located in a repo called [skywater-pdk](https://github.com/google/skywater-pdk/) A tool called [Open-PDKs (open_pdks)](https://github.com/RTimothyEdwards/open_pdks/) was developed to generate all the files typically found in a PDK. Open-PDKs uses the contents in ``skywater-pdk``, and outputs files to a directory called ``sky130A``. -`OpenLANE `__ is an open-source RTL to GDSII VLSI flow that supports Sky130. +[OpenLANE](https://github.com/efabless/openlane/) is an open-source RTL to GDSII VLSI flow that supports Sky130. -Before setting up the Sky130 PDK, we recommend familiarizing yourself with the process's documentation, :ref:`VLSI/Sky130-Tutorial/Resources:summarized below`. +Before setting up the Sky130 PDK, we recommend familiarizing yourself with the process's documentation [summarized below](#Resources). PDK Structure ------------- @@ -17,8 +17,6 @@ We recommend adhering to this file structure for Hammer as well. All the files reside in a root folder (named something like ``skywater`` or ``sky130``). The environment variable ``$PDK_ROOT`` should be set to this folder's path: -.. code-block:: shell - export PDK_ROOT= ``$PDK_ROOT`` contains the following: @@ -42,14 +40,12 @@ If you have access to these, you will be able to use the Hammer VLSI flow out-of Some of these NDA files, such as the Calibre DRC/LVS decks, rely on the environment variable ``$PDK_HOME`` containing the path to the version of the NDA files you are using. You may set it in the Hammer plugin, or as follows: -.. code-block:: shell - export PDK_HOME=/s8/ Prerequisites for PDK Setup --------------------------- -* `Magic `__ +* [Magic](http://opencircuitdesign.com/magic/) * required for ``open_pdks`` file generation * tricky to install, closely follow the directions on the ``Install`` page of the website @@ -60,8 +56,6 @@ PDK Setup --------- In ``$PDK_ROOT``, clone the skywater-pdk repo and generate the liberty files for each library: -.. code-block:: shell - git clone https://github.com/google/skywater-pdk.git cd skywater-pdk # Expect a large download! ~7GB at time of writing. @@ -71,8 +65,6 @@ In ``$PDK_ROOT``, clone the skywater-pdk repo and generate the liberty files for Again in ``$PDK_ROOT``, clone the open_pdks repo and run the install process to generate the ``sky130A`` directory: -.. code-block:: shell - git clone https://github.com/RTimothyEdwards/open_pdks cd open_pdks ./configure \ @@ -91,61 +83,60 @@ The HAMMER flow generates DRC-clean digital logic when run with the Calibre DRC TODO: summarize issues with SRAMs and open-source Magic DRC checks. -Resources ---------- +## Resources The good thing about this process being open-source is that most questions about the process are answerable through a google search. The tradeoff is that the documentation is a bit of a mess, and is currently scattered over a few pages and Github repos. We try to summarize these below. Git repos: -* `SkyWater Open Source PDK `__ +* [SkyWater Open Source PDK](https://github.com/google/skywater-pdk/) * Git repo of the main Skywater 130nm files -* `Open-PDKs `__ +* [Open-PDKs](https://github.com/RTimothyEdwards/open_pdks/) * Git repo of Open-PDKs tool that compiles the Sky130 PDK -* `Git repos on foss-eda-tools `__ +* [Git repos on foss-eda-tools](https://foss-eda-tools.googlesource.com/) * Additional useful repos, such as Berkeley Analog Generator (BAG) setup Documentation: -* `SkyWater SKY130 PDK's documentation `__ +* [SkyWater SKY130 PDK's documentation](https://skywater-pdk.readthedocs.io) * Main documentation site for the PDK -* `Join the SkyWater PDK Slack Channel `__ +* [Join the SkyWater PDK Slack Channel](https://join.skywater.tools/) * By far the best way to have questions about the process answered, with 80+ channels for different topics -* `Skywater130 Standard Cell and Primitives Overview `__ +* [Skywater130 Standard Cell and Primitives Overview](http://diychip.org/sky130/) * Additional useful documentation for the PDK -* `FOSSi Foundation YouTube Channel `__ +* [FOSSi Foundation YouTube Channel](https://www.youtube.com/c/FOSSiFoundation/) * Contains informational videos on the Sky130 process, OpenLANE flow, and Efabless Shuttle program SRAMs: -* `OpenRAM `__ +* [OpenRAM](https://github.com/VLSIDA/OpenRAM/) * Open-source static random access memory (SRAM) compiler -* `OpenRAM pre-compiled macros `__ +* [OpenRAM pre-compiled macros](https://github.com/efabless/sky130_sram_macros/) * Precompiled sizes are 1kbytes, 2kbytes and 4kbytes OpenLANE flow: -* `OpenLANE `__ +* [OpenLANE](https://github.com/efabless/openlane/) * Open-source RTL to GDSII flow -* `Magic `__ +* [Magic](http://opencircuitdesign.com/magic/) * Open-source VLSI layout tool that handles DRC checks in OpenLANE - \ No newline at end of file + From 1cecbf437e58630ddface90ec8050b47d62bb059 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 2 Aug 2021 11:44:49 -0700 Subject: [PATCH 58/81] fixed path to gds map file, renamed tech json generation files for better consistency --- .../beginning.json | 6 +- .../sites.json | 0 .../stackup.json | 0 .../generate-json.py => sky130-tech-gen.py} | 29 +- .../technology/sky130/sky130.tech.json | 6 +- .../technology/sky130/tech-json/README | 4 - .../sky130/tech-json/sky130.tech.json | 585 ------------------ 7 files changed, 17 insertions(+), 613 deletions(-) rename src/hammer-vlsi/technology/sky130/{tech-json => sky130-tech-gen-files}/beginning.json (94%) rename src/hammer-vlsi/technology/sky130/{tech-json => sky130-tech-gen-files}/sites.json (100%) rename src/hammer-vlsi/technology/sky130/{tech-json => sky130-tech-gen-files}/stackup.json (100%) rename src/hammer-vlsi/technology/sky130/{tech-json/generate-json.py => sky130-tech-gen.py} (81%) delete mode 100644 src/hammer-vlsi/technology/sky130/tech-json/README delete mode 100644 src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json diff --git a/src/hammer-vlsi/technology/sky130/tech-json/beginning.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json similarity index 94% rename from src/hammer-vlsi/technology/sky130/tech-json/beginning.json rename to src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json index 2b5ce8cae..50cd64ebf 100644 --- a/src/hammer-vlsi/technology/sky130/tech-json/beginning.json +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json @@ -15,16 +15,12 @@ "path": "$SKY130A", "base var": "technology.sky130.sky130A" }, - { - "path": "$GDS_MAP_FILE", - "base var": "technology.sky130.gds_map_file" - }, { "path": "tech-sky130-cache", "base var": "" } ], - "gds map file": "$GDS_MAP_FILE/", + "gds map file": "hammer/src/hammer-vlsi/technology/sky130/sky130_lefpin.map", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { diff --git a/src/hammer-vlsi/technology/sky130/tech-json/sites.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/sites.json similarity index 100% rename from src/hammer-vlsi/technology/sky130/tech-json/sites.json rename to src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/sites.json diff --git a/src/hammer-vlsi/technology/sky130/tech-json/stackup.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/stackup.json similarity index 100% rename from src/hammer-vlsi/technology/sky130/tech-json/stackup.json rename to src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/stackup.json diff --git a/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py similarity index 81% rename from src/hammer-vlsi/technology/sky130/tech-json/generate-json.py rename to src/hammer-vlsi/technology/sky130/sky130-tech-gen.py index cdbd827b7..ce2aedd89 100644 --- a/src/hammer-vlsi/technology/sky130/tech-json/generate-json.py +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py @@ -1,16 +1,21 @@ +# usage: +# >> export PDK_ROOT= +# >> python sky130-tech-gen.py + import json import os from pathlib import Path -data = {} - -HAMMER_HOME = os.getenv('HAMMER_HOME') -SKY130A = os.getenv('SKY130A') -JSON_PATH = os.path.join(HAMMER_HOME,'src/hammer-vlsi/technology/sky130/sky130.tech.json') - library='sky130_fd_sc_hd' -with open('beginning.json', 'r') as f: +PDK_ROOT = os.getenv('PDK_ROOT') +if PDK_ROOT is None: + print("Error: Must set $PDK_ROOT to the directory that contains the sky130A directory.") + exit() +SKY130A = os.path.join(PDK_ROOT, 'sky130A') + +data = {} +with open('sky130-tech-gen-files/beginning.json', 'r') as f: data = json.load(f) SKYWATER_LIBS = os.path.join('$SKY130A','libs.ref',library) @@ -34,8 +39,7 @@ temp = temp.split('C')[0]+' C' vdd = cornerparts[2] - vdd = vdd.split('v') - vdd = vdd[0]+'.'+vdd[1]+' V' + vdd = vdd.split('v')[0]+'.'+vdd.split('v')[1]+' V' lib_entry = { "nldm liberty file": os.path.join(SKYWATER_LIBS,'lib', cornerfilename), @@ -63,7 +67,7 @@ data["libraries"].append(lib_entry) stackups = {} -with open('stackup.json', 'r') as f: +with open('sky130-tech-gen-files/stackup.json', 'r') as f: stackups = json.load(f) stackups["name"] = library data["stackups"] = [stackups] @@ -84,12 +88,9 @@ # data["libraries"].append(lib_entry) sites = {} -with open('sites.json', 'r') as f: +with open('sky130-tech-gen-files/sites.json', 'r') as f: sites = json.load(f) data["sites"] = sites["sites"] with open('sky130.tech.json', 'w') as f: - json.dump(data, f, indent=2) - -with open(os.path.join(JSON_PATH), 'w') as f: json.dump(data, f, indent=2) \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index d0ddcecb8..7ad798c73 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -15,16 +15,12 @@ "path": "$SKY130A", "base var": "technology.sky130.sky130A" }, - { - "path": "$GDS_MAP_FILE", - "base var": "technology.sky130.gds_map_file" - }, { "path": "tech-sky130-cache", "base var": "" } ], - "gds map file": "$GDS_MAP_FILE/", + "gds map file": "hammer/src/hammer-vlsi/technology/sky130/sky130_lefpin.map", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { diff --git a/src/hammer-vlsi/technology/sky130/tech-json/README b/src/hammer-vlsi/technology/sky130/tech-json/README deleted file mode 100644 index b7c6df966..000000000 --- a/src/hammer-vlsi/technology/sky130/tech-json/README +++ /dev/null @@ -1,4 +0,0 @@ -Make sure $HAMMER_HOME points to the Hammer install you're using with Sky130. -Then run: - >> python generate-json.py -This writes the tech json file to ./sky130.tech.json and $HAMMER_HOME/src/hammer-vlsi/technology/sky130/sky130.tech.json diff --git a/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json b/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json deleted file mode 100644 index 3da392e6e..000000000 --- a/src/hammer-vlsi/technology/sky130/tech-json/sky130.tech.json +++ /dev/null @@ -1,585 +0,0 @@ -{ - "name": "Skywater 130nm Library", - "grid_unit": "0.001", - "time_unit": "1 ps", - "installs": [ - { - "path": "$SKY130_PDK", - "base var": "technology.sky130.sky130_pdk" - }, - { - "path": "$SKY130_NDA", - "base var": "technology.sky130.sky130_nda" - }, - { - "path": "$SKY130A", - "base var": "technology.sky130.sky130A" - }, - { - "path": "$GDS_MAP_FILE", - "base var": "technology.sky130.gds_map_file" - }, - { - "path": "tech-sky130-cache", - "base var": "" - } - ], - "gds map file": "$GDS_MAP_FILE/", - "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", - "drc decks": [ - { - "tool name": "calibre", - "deck name": "all_drc", - "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" - } - ], - "additional_drc_text": "", - "lvs decks": [ - { - "tool name": "calibre", - "deck name": "all_lvs", - "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", - "path": "tech-sky130-cache/lvsControlFile_s8" - } - ], - "additional_lvs_text": "", - "physical only cells list": [ - "sky130_fd_sc_hd__tap_1", - "sky130_fd_sc_hd__tap_2", - "sky130_fd_sc_hd__tapvgnd_1", - "sky130_fd_sc_hd__tapvpwrvgnd_1", - "sky130_fd_sc_hd__fill_1", - "sky130_fd_sc_hd__fill_2", - "sky130_fd_sc_hd__fill_4", - "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__diode_2" - ], - "dont use list": [], - "special cells": [ - { - "cell_type": "tapcell", - "name": [ - "sky130_fd_sc_hd__tapvpwrvgnd_1" - ] - }, - { - "cell_type": "stdfiller", - "name": [ - "sky130_fd_sc_hd__fill_1", - "sky130_fd_sc_hd__fill_2", - "sky130_fd_sc_hd__fill_4", - "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", - "sky130_fd_sc_hd__decap_3", - "sky130_fd_sc_hd__decap_4", - "sky130_fd_sc_hd__decap_6", - "sky130_fd_sc_hd__decap_8" - ] - }, - { - "cell_type": "tiehilocell", - "name": [ - "sky130_fd_sc_hd__conb_1" - ] - } - ], - "libraries": [ - { - "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", - "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", - "provides": [ - { - "lib_type": "technology" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "fast", - "pmos": "fast", - "temperature": "100 C" - }, - "supplies": { - "VDD": "1.65 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "fast", - "pmos": "fast", - "temperature": "100 C" - }, - "supplies": { - "VDD": "1.95 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "fast", - "pmos": "fast", - "temperature": "-40 C" - }, - "supplies": { - "VDD": "1.56 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "fast", - "pmos": "fast", - "temperature": "-40 C" - }, - "supplies": { - "VDD": "1.65 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "fast", - "pmos": "fast", - "temperature": "-40 C" - }, - "supplies": { - "VDD": "1.76 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "fast", - "pmos": "fast", - "temperature": "-40 C" - }, - "supplies": { - "VDD": "1.95 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "slow", - "pmos": "slow", - "temperature": "100 C" - }, - "supplies": { - "VDD": "1.40 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "slow", - "pmos": "slow", - "temperature": "100 C" - }, - "supplies": { - "VDD": "1.60 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "slow", - "pmos": "slow", - "temperature": "-40 C" - }, - "supplies": { - "VDD": "1.28 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "slow", - "pmos": "slow", - "temperature": "-40 C" - }, - "supplies": { - "VDD": "1.35 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "slow", - "pmos": "slow", - "temperature": "-40 C" - }, - "supplies": { - "VDD": "1.40 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "slow", - "pmos": "slow", - "temperature": "-40 C" - }, - "supplies": { - "VDD": "1.44 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "slow", - "pmos": "slow", - "temperature": "-40 C" - }, - "supplies": { - "VDD": "1.60 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "slow", - "pmos": "slow", - "temperature": "-40 C" - }, - "supplies": { - "VDD": "1.76 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "typical", - "pmos": "typical", - "temperature": "025 C" - }, - "supplies": { - "VDD": "1.80 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", - "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", - "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", - "corner": { - "nmos": "typical", - "pmos": "typical", - "temperature": "100 C" - }, - "supplies": { - "VDD": "1.80 V", - "GND": "0 V" - }, - "provides": [ - { - "lib_type": "stdcell", - "vt": "RVT" - } - ] - }, - { - "lef file": "$SKY130A/libs.ref/sky130_fd_pr/lef/sky130_fd_pr.lef", - "spice file": "$SKY130A/libs.ref/sky130_fd_pr/cdl/sky130_fd_pr.cdl", - "gds file": "$SKY130A/libs.ref/sky130_fd_pr/gds/sky130_fd_pr.gds", - "provides": [ - { - "lib_type": "primitives", - "vt": "RVT" - } - ] - } - ], - "stackups": [ - { - "name": "sky130_fd_sc_hd", - "metals": [ - { - "name": "li1", - "index": 1, - "direction": "vertical", - "min_width": 0.17, - "max_width": 2147483.647, - "pitch": 0.34, - "offset": 0.23, - "power_strap_widths_and_spacings": [ - { - "width_at_least": 0.0, - "min_spacing": 0.17 - } - ] - }, - { - "name": "met1", - "index": 2, - "direction": "horizontal", - "min_width": 0.14, - "max_width": 2147483.647, - "pitch": 0.28, - "offset": 0.17, - "power_strap_widths_and_spacings": [ - { - "width_at_least": 0.0, - "min_spacing": 0.14 - }, - { - "width_at_least": 3.0, - "min_spacing": 0.28 - } - ] - }, - { - "name": "met2", - "index": 3, - "direction": "vertical", - "min_width": 0.14, - "max_width": 2147483.647, - "pitch": 0.28, - "offset": 0.23, - "power_strap_widths_and_spacings": [ - { - "width_at_least": 0.0, - "min_spacing": 0.14 - }, - { - "width_at_least": 3.0, - "min_spacing": 0.28 - } - ] - }, - { - "name": "met3", - "index": 4, - "direction": "horizontal", - "min_width": 0.3, - "max_width": 2147483.647, - "pitch": 0.6, - "offset": 0.34, - "power_strap_widths_and_spacings": [ - { - "width_at_least": 0.0, - "min_spacing": 0.3 - }, - { - "width_at_least": 3.0, - "min_spacing": 0.4 - } - ] - }, - { - "name": "met4", - "index": 5, - "direction": "vertical", - "min_width": 0.3, - "max_width": 2147483.647, - "pitch": 0.6, - "offset": 0.46, - "power_strap_widths_and_spacings": [ - { - "width_at_least": 0.0, - "min_spacing": 0.3 - }, - { - "width_at_least": 3.0, - "min_spacing": 0.4 - } - ] - }, - { - "name": "met5", - "index": 6, - "direction": "horizontal", - "min_width": 1.6, - "max_width": 2147483.647, - "pitch": 3.2, - "offset": 1.7, - "power_strap_widths_and_spacings": [ - { - "width_at_least": 0.0, - "min_spacing": 1.6 - } - ] - } - ] - } - ], - "sites": [ - { - "name": "unithd", - "x": 0.46, - "y": 2.72 - }, - { - "name": "unithddbl", - "x": 0.46, - "y": 5.44 - } - ] -} \ No newline at end of file From ce797d55507830e832ae3247d64575c3ebfd5cc6 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 2 Aug 2021 12:07:40 -0700 Subject: [PATCH 59/81] fixing type issues found in hammer unit tests --- src/hammer-vlsi/technology/sky130/__init__.py | 4 ++-- src/hammer-vlsi/technology/sky130/sky130-tech-gen.py | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 0876047c6..bdbe49aac 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -45,7 +45,7 @@ def ensure_dirs_exist(self, path) -> None: os.makedirs(dir_name) @staticmethod - def openram_sram_names() -> None: + def openram_sram_names() -> List[str]: """ Return a list of cell-names of the OpenRAM SRAMs (that we'll use). """ return [ # "sky130_sram_4kbyte_1rw1r_32x1024_8", # Eventually to be reinstated, some day @@ -142,7 +142,7 @@ def setup_lvs_deck(self) -> None: try: source_path = source_paths[i] except IndexError: - self.logging.error( + self.logger.error( 'No corresponding source for LVS deck {}'.format(deck)) dest_path = self.expand_tech_cache_path(str(deck.path)) self.ensure_dirs_exist(dest_path) diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py index ce2aedd89..cd39061ff 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py @@ -14,7 +14,7 @@ exit() SKY130A = os.path.join(PDK_ROOT, 'sky130A') -data = {} +# data = {} with open('sky130-tech-gen-files/beginning.json', 'r') as f: data = json.load(f) @@ -66,7 +66,7 @@ data["libraries"].append(lib_entry) -stackups = {} +# stackups = {} with open('sky130-tech-gen-files/stackup.json', 'r') as f: stackups = json.load(f) stackups["name"] = library @@ -87,7 +87,7 @@ # } # data["libraries"].append(lib_entry) -sites = {} +# sites = {} with open('sky130-tech-gen-files/sites.json', 'r') as f: sites = json.load(f) data["sites"] = sites["sites"] From 11d5ff8e3a55aed85d591ce31a5dad1eb8644798 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Mon, 2 Aug 2021 13:44:46 -0700 Subject: [PATCH 60/81] adding assert ht is TCLTool --- src/hammer-vlsi/technology/sky130/__init__.py | 30 ++++++++----------- 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index bdbe49aac..90ea516f1 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -205,9 +205,8 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: # various Innovus database settings def sky130_innovus_settings(ht: HammerTool) -> bool: - assert isinstance( - ht, HammerPlaceAndRouteTool - ), "Innovus settings can only run on par" + assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" + assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" """Settings for every tool invocation""" ht.append( ''' @@ -280,9 +279,8 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: # from NDA scripts def sky130_add_endcaps(ht: HammerTool) -> bool: - assert isinstance( - ht, HammerPlaceAndRouteTool - ), "endcap insertion can only run on par" + assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" + assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" ht.append( ''' set_db add_endcaps_boundary_tap true @@ -297,9 +295,8 @@ def sky130_add_endcaps(ht: HammerTool) -> bool: # these commands are already added in Innovus.write_netlist, # but must also occur before power straps are placed def sky130_power_nets(ht: HammerTool) -> bool: - assert isinstance( - ht, HammerPlaceAndRouteTool - ), "connect global nets can only run on par" + assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" + assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" ht.append( ''' connect_global_net VDD -type net -net_base_name VPWR @@ -309,9 +306,8 @@ def sky130_power_nets(ht: HammerTool) -> bool: return True def sky130_remove_route_blockages(ht: HammerTool) -> bool: - assert isinstance( - ht, HammerPlaceAndRouteTool - ), "removing blockages can only run on par" + assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" + assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" ht.append( ''' delete_route_blockages -layers {met1 met4} @@ -321,9 +317,8 @@ def sky130_remove_route_blockages(ht: HammerTool) -> bool: # TODO: add these two functions into Hammer Innovus plugin def sky130_add_tieoffs(ht: HammerTool) -> bool: - assert isinstance( - ht, HammerPlaceAndRouteTool - ), "tie high/low cell insertion can only run on par" + assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" + assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" ht.append( ''' set_db add_tieoffs_cells sky130_fd_sc_hd__conb_1 @@ -333,9 +328,8 @@ def sky130_add_tieoffs(ht: HammerTool) -> bool: return True def sky130_connect_nets(ht: HammerTool) -> bool: - assert isinstance( - ht, HammerPlaceAndRouteTool - ), "connect global nets can only run on par" + assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" + assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" ht.append( ''' connect_global_net VDD -type pg_pin -pin_base_name VPWR -all From 9278470acc25a41e9ad7e30c48e80ffc94ca7ad5 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Wed, 4 Aug 2021 18:52:53 -0700 Subject: [PATCH 61/81] fixing many PR comments --- src/hammer-vlsi/technology/sky130/__init__.py | 89 +++++++---------- .../technology/sky130/defaults.yml | 37 +++---- .../sky130-tech-gen-files/beginning.json | 19 +--- .../sky130/sky130-tech-gen-files/cells.json | 18 ++++ .../{stackup.json => stackups.json} | 2 +- .../technology/sky130/sky130-tech-gen.py | 27 ++---- .../technology/sky130/sky130.tech.json | 96 +++++++++++-------- 7 files changed, 136 insertions(+), 152 deletions(-) create mode 100644 src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/cells.json rename src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/{stackup.json => stackups.json} (97%) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 90ea516f1..543e9c0ed 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -21,9 +21,8 @@ class SKY130Tech(HammerTechnology): This class is loaded by function `load_from_json`, and will pass the `try` in `importlib`. """ def post_install_script(self) -> None: - # maybe run open_pdks for the user and install in tech cache...? - # this takes a while and ~7Gb self.library_name = 'sky130_fd_sc_hd' + self.use_openram = (self.get_setting("technology.sky130.openram_lib") is not "") self.setup_sram_cdl() self.setup_cdl() self.setup_verilog() @@ -31,7 +30,8 @@ def post_install_script(self) -> None: self.setup_lvs_deck() print('Loaded Sky130 Tech') - # Helper functions - copied from TSMC28 plugin + # Helper functions + # TODO: add to HammerTechnology def expand_tech_cache_path(self, path) -> str: """ Replace occurrences of the cache directory's basename with the full path to the cache dir.""" @@ -43,33 +43,10 @@ def ensure_dirs_exist(self, path) -> None: if not os.path.exists(dir_name): self.logger.info('Creating directory: {}'.format(dir_name)) os.makedirs(dir_name) - - @staticmethod - def openram_sram_names() -> List[str]: - """ Return a list of cell-names of the OpenRAM SRAMs (that we'll use). """ - return [ - # "sky130_sram_4kbyte_1rw1r_32x1024_8", # Eventually to be reinstated, some day - "sky130_sram_1kbyte_1rw1r_32x256_8", - "sky130_sram_1kbyte_1rw1r_8x1024_8", - "sky130_sram_2kbyte_1rw1r_32x512_8" - ] - - def setup_sram_cdl(self) -> None: - for sram_name in self.openram_sram_names(): - old_path = Path(self.get_setting("technology.sky130.openram_lib")) / sram_name / f"{sram_name}.lvs.sp" - new_path = self.expand_tech_cache_path(f'tech-sky130-cache/{sram_name}/{sram_name}.lvs.sp') - self.ensure_dirs_exist(new_path) - with open(old_path,'r') as f_old: - with open(new_path,'w') as f_new: - for line in f_old: - line = line.replace('sky130_fd_pr__pfet_01v8','pshort') - line = line.replace('sky130_fd_pr__nfet_01v8','nshort') - f_new.write(line) # Tech setup steps def setup_cdl(self) -> None: """ Copy and hack the cdl, replacing pfet_01v8_hvt/nfet_01v8 with phighvt/nshort """ - # TODO: figure out how to rename the devices to pass Calibre LVS setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) cdl_old_path = setting_dir / 'libs.ref' / self.library_name / 'cdl' / f'{self.library_name}.cdl' @@ -132,6 +109,13 @@ def setup_techlef(self) -> None: def setup_lvs_deck(self) -> None: """Remove conflicting specification statements found in PDK LVS decks.""" + + # if using OpenRAM SRAMs, LVS BOX these to ignore in LVS check + # if self.use_openram: + # for name in SKY130Tech.openram_sram_names(): + # LVS_DECK_INSERT_LINES += f"LVS BOX {name} \n" + # LVS_DECK_INSERT_LINES += f"LVS FILTER {name} OPEN \n" + pattern = '.*({}).*\n'.format('|'.join(LVS_DECK_SCRUB_LINES)) matcher = re.compile(pattern) @@ -163,7 +147,29 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: ]} return hooks.get(tool_name, []) + ''' >>>>>>>> OpenRAM SRAM-specific functions ''' + @staticmethod + def openram_sram_names() -> List[str]: + """ Return a list of cell-names of the OpenRAM SRAMs (that we'll use). """ + return [ + "sky130_sram_1kbyte_1rw1r_32x256_8", + "sky130_sram_1kbyte_1rw1r_8x1024_8", + "sky130_sram_2kbyte_1rw1r_32x512_8" + ] + def setup_sram_cdl(self) -> None: + if not self.use_openram: return + for sram_name in self.openram_sram_names(): + old_path = Path(self.get_setting("technology.sky130.openram_lib")) / sram_name / f"{sram_name}.lvs.sp" + new_path = self.expand_tech_cache_path(f'tech-sky130-cache/{sram_name}/{sram_name}.lvs.sp') + self.ensure_dirs_exist(new_path) + with open(old_path,'r') as f_old: + with open(new_path,'w') as f_new: + for line in f_old: + line = line.replace('sky130_fd_pr__pfet_01v8','pshort') + line = line.replace('sky130_fd_pr__nfet_01v8','nshort') + f_new.write(line) + ''' <<<<<<< END OpenRAM SRAM-specific functions ''' _the_tlef_edit = ''' LAYER licon @@ -185,24 +191,6 @@ def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: LVS FILTER D OPEN LAYOUT ''' -# TODO: black boxing sram is temporary!! -for name in SKY130Tech.openram_sram_names(): - LVS_DECK_INSERT_LINES += f"LVS BOX {name} \n" - LVS_DECK_INSERT_LINES += f"LVS FILTER {name} OPEN \n" - -# EXCLUDE CELL sky130_sram_1kbyte_1rw1r_32x256_8 -# EXCLUDE CELL sky130_sram_1kbyte_1rw1r_8x1024_8 -# EXCLUDE CELL sky130_sram_2kbyte_1rw1r_32x512_8 - -# LVS BOX sky130_sram_1kbyte_1rw1r_32x256_8 -# LVS BOX sky130_sram_1kbyte_1rw1r_8x1024_8 -# LVS BOX sky130_sram_2kbyte_1rw1r_32x512_8 - -# LVS FILTER sky130_sram_1kbyte_1rw1r_32x256_8 OPEN -# LVS FILTER sky130_sram_1kbyte_1rw1r_8x1024_8 OPEN -# LVS FILTER sky130_sram_2kbyte_1rw1r_32x512_8 OPEN - - # various Innovus database settings def sky130_innovus_settings(ht: HammerTool) -> bool: assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" @@ -277,7 +265,7 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: -# from NDA scripts +# TODO: move to Innovus plugin def sky130_add_endcaps(ht: HammerTool) -> bool: assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" @@ -294,6 +282,7 @@ def sky130_add_endcaps(ht: HammerTool) -> bool: # Pair VDD/VPWR and VSS/VGND nets # these commands are already added in Innovus.write_netlist, # but must also occur before power straps are placed +# TODO: move to Innovus plugin def sky130_power_nets(ht: HammerTool) -> bool: assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" @@ -305,16 +294,6 @@ def sky130_power_nets(ht: HammerTool) -> bool: ) return True -def sky130_remove_route_blockages(ht: HammerTool) -> bool: - assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" - assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" - ht.append( - ''' -delete_route_blockages -layers {met1 met4} - ''' - ) - return True - # TODO: add these two functions into Hammer Innovus plugin def sky130_add_tieoffs(ht: HammerTool) -> bool: assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index a01fa59f6..bb6347ef5 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -1,21 +1,27 @@ -# Settings for the sky130 technology to be overriden by the project. +# Settings for the sky130 technology technology.sky130: + # Override these in project sky130_pdk: "PATH-TO-SKY130_PDK" sky130_nda: "PATH-TO-skywater-src-nda" sky130A: "PATH-TO-SKY130A_DIR" - openram_lib: "PATH-TO-sky130_fd_bd_sram/macros" - dffram_lib: "PATH-TO-DFFRAM/Compiler/build" - - # GDS map file path, not provided by efabless - gds_map_file: "hammer/src/hammer-vlsi/technology/sky130/sky130_lefpin.map" + # Set one of these if using SRAMs + # DFFRAM currently not supported + openram_lib: "" # path to sky130_fd_bd_sram/macros + dffram_lib: "" # path to dffram/compiler/build + + # Shouldn't need to change these + pdk_home: "${technology.sky130.sky130_nda}/s8/V2.0.1" + pdk_home_meta: lazysubst + lvs_deck_sources: - - "${technology.sky130.sky130_nda}/s8/V2.0.1/LVS/Calibre/lvsControlFile_s8" + - "${technology.sky130.pdk_home}/LVS/Calibre/lvsControlFile_s8" lvs_deck_sources_meta: lazysubst -# Calibre environment variables +# Mentor environment variables +# Override this in project mentor.extra_env_vars: - - PDK_HOME: "${technology.sky130_nda}/s8/V2.0.1" + - PDK_HOME: "/s8/" # Set some defaults for this technology. vlsi: @@ -24,8 +30,8 @@ vlsi: technology: sky130 node: 130 sram_generator_tool: "sram_compiler" - sram_generator_tool_path: ["${HAMMER_HOME}/src/hammer-vlsi/technology/sky130"] - sram_generator_tool_path_meta: "append" + sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/sky130"] + sram_generator_tool_path_meta: ["append", "lazysubst"] inputs: # Supply voltages. # TODO: add ability to tie pin to net in Hammer Innovus plugin @@ -39,10 +45,6 @@ vlsi: VDD: "1.8 V" GND: "0 V" - # moved these to json - # dont_use_mode: append - # dont_use_list: ["*sdf*","sky130_fd_sc_hd__probe_p_8"] # Scan flops go haywire! Avoid them. - # mmmc corners config mmmc_corners: [ { @@ -63,7 +65,6 @@ vlsi: placement_site: "unithd" # Set the layer that blocks vias under bumps - # nk - not sure if this is right?? bump_block_cut_layer: "via4" # Set the interval and offset for tap cells @@ -81,4 +82,6 @@ technology.core: par.inputs: gds_merge: true - \ No newline at end of file + gds_map_mode: manual + gds_map_file: "${vlsi.builtins.hammer_vlsi_path}/technology/sky130/sky130_lefpin.map" + gds_map_file_meta: lazysubst \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json index 50cd64ebf..0165dca20 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json @@ -20,7 +20,7 @@ "base var": "" } ], - "gds map file": "hammer/src/hammer-vlsi/technology/sky130/sky130_lefpin.map", + "gds map file": "specified-in-defaults.yml", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { @@ -40,23 +40,6 @@ } ], "additional_lvs_text": "", - - "physical only cells list": [ - "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", - "sky130_fd_sc_hd__tapvgnd_1", - "sky130_fd_sc_hd__tapvpwrvgnd_1", - "sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__diode_2" - ], - "dont use list": [], - "special cells": [ - {"cell_type": "tapcell", "name": ["sky130_fd_sc_hd__tapvpwrvgnd_1"]}, - {"cell_type": "stdfiller", "name": ["sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", - "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", "sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", - "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8"]}, - {"cell_type": "tiehilocell", "name": ["sky130_fd_sc_hd__conb_1"]} - ], "libraries": [ { diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/cells.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/cells.json new file mode 100644 index 000000000..64e578d39 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/cells.json @@ -0,0 +1,18 @@ +{ + "physical only cells list": [ + "sky130_fd_sc_hd__tap_1", "sky130_fd_sc_hd__tap_2", "sky130_fd_sc_hd__tapvgnd_1", "sky130_fd_sc_hd__tapvpwrvgnd_1", + "sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__diode_2" + ], + "dont use list": [ + "*sdf*", + "sky130_fd_sc_hd__probe_p_8" + ], + "special cells": [ + {"cell_type": "tiehilocell", "name": ["sky130_fd_sc_hd__conb_1"]}, + {"cell_type": "endcap", "name": ["sky130_fd_sc_hd__tap_1"]}, + {"cell_type": "tapcell", "name": ["sky130_fd_sc_hd__tapvpwrvgnd_1"]}, + {"cell_type": "stdfiller", "name": ["sky130_fd_sc_hd__fill_1", "sky130_fd_sc_hd__fill_2", "sky130_fd_sc_hd__fill_4", "sky130_fd_sc_hd__fill_8"]}, + {"cell_type": "decap", "name": ["sky130_fd_sc_hd__decap_3", "sky130_fd_sc_hd__decap_4", "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_8", "sky130_fd_sc_hd__decap_12"]} + ] +} \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/stackup.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/stackups.json similarity index 97% rename from src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/stackup.json rename to src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/stackups.json index 13914d9d8..7e2e3d1e6 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/stackup.json +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/stackups.json @@ -1,5 +1,5 @@ { - "name" : "TODO", + "name" : "sky130_fd_sc_hd", "metals": [ {"name": "li1", "index": 1, "direction": "vertical", "min_width": 0.17, "max_width": 2147483.647, "pitch": 0.34, "offset": 0.23, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.17}]}, {"name": "met1", "index": 2, "direction": "horizontal", "min_width": 0.14, "max_width": 2147483.647, "pitch": 0.28, "offset": 0.17, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.14}, {"width_at_least": 3.0, "min_spacing": 0.28}]}, diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py index cd39061ff..37c5626f5 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py @@ -14,10 +14,15 @@ exit() SKY130A = os.path.join(PDK_ROOT, 'sky130A') -# data = {} with open('sky130-tech-gen-files/beginning.json', 'r') as f: data = json.load(f) +with open('sky130-tech-gen-files/cells.json', 'r') as f: + cells = json.load(f) +data["physical only cells list"] = cells["physical only cells list"] +data["dont use list"] = cells["dont use list"] +data["special cells"] = cells["special cells"] + SKYWATER_LIBS = os.path.join('$SKY130A','libs.ref',library) LIBRARY_PATH = os.path.join(SKY130A,'libs.ref',library,'lib') lib_corners=os.listdir(LIBRARY_PATH) @@ -66,28 +71,10 @@ data["libraries"].append(lib_entry) -# stackups = {} -with open('sky130-tech-gen-files/stackup.json', 'r') as f: +with open('sky130-tech-gen-files/stackups.json', 'r') as f: stackups = json.load(f) -stackups["name"] = library data["stackups"] = [stackups] -# library='sky130_fd_pr' -# SKYWATER_LIBS=os.path.join('$SKY130A',"libs.ref",library) -# lib_entry = { -# "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), -# "spice file": os.path.join(SKYWATER_LIBS,'cdl', library+'.cdl'), -# "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), -# "provides": [ -# { -# "lib_type": "primitives", -# "vt": "RVT" -# } -# ] -# } -# data["libraries"].append(lib_entry) - -# sites = {} with open('sky130-tech-gen-files/sites.json', 'r') as f: sites = json.load(f) data["sites"] = sites["sites"] diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 7ad798c73..0ca7f5bb0 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -20,7 +20,7 @@ "base var": "" } ], - "gds map file": "hammer/src/hammer-vlsi/technology/sky130/sky130_lefpin.map", + "gds map file": "specified-in-defaults.yml", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { @@ -39,46 +39,6 @@ } ], "additional_lvs_text": "", - "physical only cells list": [ - "sky130_fd_sc_hd__tap_1", - "sky130_fd_sc_hd__tap_2", - "sky130_fd_sc_hd__tapvgnd_1", - "sky130_fd_sc_hd__tapvpwrvgnd_1", - "sky130_fd_sc_hd__fill_1", - "sky130_fd_sc_hd__fill_2", - "sky130_fd_sc_hd__fill_4", - "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__diode_2" - ], - "dont use list": [], - "special cells": [ - { - "cell_type": "tapcell", - "name": [ - "sky130_fd_sc_hd__tapvpwrvgnd_1" - ] - }, - { - "cell_type": "stdfiller", - "name": [ - "sky130_fd_sc_hd__fill_1", - "sky130_fd_sc_hd__fill_2", - "sky130_fd_sc_hd__fill_4", - "sky130_fd_sc_hd__fill_8", - "sky130_fd_sc_hd__decap_12", - "sky130_fd_sc_hd__decap_3", - "sky130_fd_sc_hd__decap_4", - "sky130_fd_sc_hd__decap_6", - "sky130_fd_sc_hd__decap_8" - ] - }, - { - "cell_type": "tiehilocell", - "name": [ - "sky130_fd_sc_hd__conb_1" - ] - } - ], "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", @@ -442,6 +402,60 @@ ] } ], + "physical only cells list": [ + "sky130_fd_sc_hd__tap_1", + "sky130_fd_sc_hd__tap_2", + "sky130_fd_sc_hd__tapvgnd_1", + "sky130_fd_sc_hd__tapvpwrvgnd_1", + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8", + "sky130_fd_sc_hd__diode_2" + ], + "dont use list": [ + "*sdf*", + "sky130_fd_sc_hd__probe_p_8" + ], + "special cells": [ + { + "cell_type": "tiehilocell", + "name": [ + "sky130_fd_sc_hd__conb_1" + ] + }, + { + "cell_type": "endcap", + "name": [ + "sky130_fd_sc_hd__tap_1" + ] + }, + { + "cell_type": "tapcell", + "name": [ + "sky130_fd_sc_hd__tapvpwrvgnd_1" + ] + }, + { + "cell_type": "stdfiller", + "name": [ + "sky130_fd_sc_hd__fill_1", + "sky130_fd_sc_hd__fill_2", + "sky130_fd_sc_hd__fill_4", + "sky130_fd_sc_hd__fill_8" + ] + }, + { + "cell_type": "decap", + "name": [ + "sky130_fd_sc_hd__decap_3", + "sky130_fd_sc_hd__decap_4", + "sky130_fd_sc_hd__decap_6", + "sky130_fd_sc_hd__decap_8", + "sky130_fd_sc_hd__decap_12" + ] + } + ], "stackups": [ { "name": "sky130_fd_sc_hd", From 54e409b0d8cee130b24f4b9b151e4295662ee8e8 Mon Sep 17 00:00:00 2001 From: Nayiri <38256927+nayiri-k@users.noreply.github.com> Date: Tue, 24 Aug 2021 12:36:33 -0700 Subject: [PATCH 62/81] Update README.md --- src/hammer-vlsi/technology/sky130/README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/README.md b/src/hammer-vlsi/technology/sky130/README.md index 4e87eebe9..56723663a 100644 --- a/src/hammer-vlsi/technology/sky130/README.md +++ b/src/hammer-vlsi/technology/sky130/README.md @@ -65,7 +65,7 @@ In ``$PDK_ROOT``, clone the skywater-pdk repo and generate the liberty files for Again in ``$PDK_ROOT``, clone the open_pdks repo and run the install process to generate the ``sky130A`` directory: - git clone https://github.com/RTimothyEdwards/open_pdks + git clone https://github.com/RTimothyEdwards/open_pdks.git cd open_pdks ./configure \ --enable-sky130-pdk=$PDK_ROOT/skywater-pdk/libraries \ @@ -77,6 +77,8 @@ OpenRAM SRAMs ------------- TODO: add overview here + git clone https://github.com/efabless/sky130_sram_macros.git + Known DRC Issues ---------------- The HAMMER flow generates DRC-clean digital logic when run with the Calibre DRC deck and SRAMs excluded. From 8b22d340bd2add5901f55bd11192eaab12886ad4 Mon Sep 17 00:00:00 2001 From: Nayiri <38256927+nayiri-k@users.noreply.github.com> Date: Tue, 24 Aug 2021 13:39:13 -0700 Subject: [PATCH 63/81] Update README.md --- src/hammer-vlsi/technology/sky130/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/README.md b/src/hammer-vlsi/technology/sky130/README.md index 56723663a..10031a921 100644 --- a/src/hammer-vlsi/technology/sky130/README.md +++ b/src/hammer-vlsi/technology/sky130/README.md @@ -69,7 +69,7 @@ Again in ``$PDK_ROOT``, clone the open_pdks repo and run the install process to cd open_pdks ./configure \ --enable-sky130-pdk=$PDK_ROOT/skywater-pdk/libraries \ - --with-sky130-local-path=$PDK_ROOT + --prefix=$PDK_ROOT make make install From 0174899791ae06ad57af0eadd3f5b81865c87c4c Mon Sep 17 00:00:00 2001 From: Nayiri <38256927+nayiri-k@users.noreply.github.com> Date: Wed, 25 Aug 2021 12:14:35 -0700 Subject: [PATCH 64/81] Update README.md --- src/hammer-vlsi/technology/sky130/README.md | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/README.md b/src/hammer-vlsi/technology/sky130/README.md index 10031a921..ce663b871 100644 --- a/src/hammer-vlsi/technology/sky130/README.md +++ b/src/hammer-vlsi/technology/sky130/README.md @@ -51,6 +51,12 @@ Prerequisites for PDK Setup * tricky to install, closely follow the directions on the ``Install`` page of the website * as the directions indicate, you will likely need to manually specify the location of the Tcl/Tk package installation using ``--with-tcl`` and ``--with-tk`` + + If using conda, these installs alone caused the Magic install to work: + + conda install -c intel tcl + conda install -c anaconda tk + conda install -c anaconda libglu PDK Setup --------- @@ -59,7 +65,8 @@ In ``$PDK_ROOT``, clone the skywater-pdk repo and generate the liberty files for git clone https://github.com/google/skywater-pdk.git cd skywater-pdk # Expect a large download! ~7GB at time of writing. - SUBMODULE_VERSION=latest make submodules -j3 || make submodules -j1 + git submodule init libraries/*/latest + git submodule update # Regenerate liberty files make timing @@ -69,7 +76,8 @@ Again in ``$PDK_ROOT``, clone the open_pdks repo and run the install process to cd open_pdks ./configure \ --enable-sky130-pdk=$PDK_ROOT/skywater-pdk/libraries \ - --prefix=$PDK_ROOT + --prefix=$PDK_ROOT \ + --enable-sram-sky130=$PDK_ROOT/sky130_sram_macros # if using SRAMs make make install From d2c650d9d27d96449bab8430f1c8becb4da64657 Mon Sep 17 00:00:00 2001 From: Nayiri Date: Tue, 7 Sep 2021 10:09:12 -0700 Subject: [PATCH 65/81] hack sky130 verilog primitives --- src/hammer-vlsi/technology/sky130/__init__.py | 20 +++++++++ .../sky130-tech-gen-files/beginning.json | 10 ++++- .../technology/sky130/sky130-tech-gen.py | 2 +- .../technology/sky130/sky130.tech.json | 42 +++++++++++-------- .../technology/sky130/sram-cache.json | 3 ++ 5 files changed, 58 insertions(+), 19 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 543e9c0ed..f57c9cebc 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -70,6 +70,8 @@ def setup_verilog(self) -> None: """ Copy and hack the verilog """ setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) + + # fix up .v verilog_old_path = setting_dir / 'libs.ref' / self.library_name / 'verilog' / f'{self.library_name}.v' if not verilog_old_path.exists(): raise FileNotFoundError(f"Verilog not found: {verilog_old_path}") @@ -82,6 +84,24 @@ def setup_verilog(self) -> None: f_new = open(verilog_new_path,'w') for line in f_old: line = line.replace('wire 1','// wire 1') + line = line.replace('`endif SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V','`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V') + f_new.write(line) + f_old.close() + f_new.close() + + # fix up primitives.v + verilog_old_path = setting_dir / 'libs.ref' / self.library_name / 'verilog' / 'primitives.v' + if not verilog_old_path.exists(): + raise FileNotFoundError(f"Verilog not found: {verilog_old_path}") + + cache_tech_dir_path = Path(self.cache_dir) + os.makedirs(cache_tech_dir_path, exist_ok=True) + verilog_new_path = cache_tech_dir_path / 'primitives.v' + + f_old = open(verilog_old_path,'r') + f_new = open(verilog_new_path,'w') + for line in f_old: + line = line.replace('`default_nettype none','`default_nettype wire') f_new.write(line) f_old.close() f_new.close() diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json index 0165dca20..6225136db 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json @@ -44,12 +44,20 @@ "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", - "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", "provides": [ { "lib_type": "technology" } ] + }, + { + "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", + "verilog sim": "tech-sky130-cache/primitives.v", + "provides": [ + { + "lib_type": "extra" + } + ] } ] } \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py index 37c5626f5..158e426ea 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py @@ -48,7 +48,7 @@ lib_entry = { "nldm liberty file": os.path.join(SKYWATER_LIBS,'lib', cornerfilename), - "verilog sim": os.path.join(SKYWATER_LIBS,'verilog', library+'.v'), + "verilog sim": os.path.join('tech-sky130-cache', library+'.v'), "lef file": os.path.join(SKYWATER_LIBS,'lef', library+'.lef'), "spice file": os.path.join('tech-sky130-cache', library+'.cdl'), "gds file": os.path.join(SKYWATER_LIBS,'gds', library+'.gds'), diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 0ca7f5bb0..b8f4c4eb0 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -42,16 +42,24 @@ "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", - "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", "provides": [ { "lib_type": "technology" } ] }, + { + "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", + "verilog sim": "tech-sky130-cache/primitives.v", + "provides": [ + { + "lib_type": "extra" + } + ] + }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -73,7 +81,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v95.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -95,7 +103,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -117,7 +125,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v65.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -139,7 +147,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v76.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -161,7 +169,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -183,7 +191,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v40.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -205,7 +213,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -227,7 +235,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v28.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -249,7 +257,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v35.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -271,7 +279,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v40.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -293,7 +301,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v44.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -315,7 +323,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -337,7 +345,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v76.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -359,7 +367,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", @@ -381,7 +389,7 @@ }, { "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib", - "verilog sim": "$SKY130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v", + "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", "gds file": "$SKY130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds", diff --git a/src/hammer-vlsi/technology/sky130/sram-cache.json b/src/hammer-vlsi/technology/sky130/sram-cache.json index fa459914a..c8fe66ee9 100644 --- a/src/hammer-vlsi/technology/sky130/sram-cache.json +++ b/src/hammer-vlsi/technology/sky130/sram-cache.json @@ -7,6 +7,7 @@ "family": "1rw", "mask": "true", "vt": "svt", + "mux" : 1, "ports": [ { "address port name": "addr0", @@ -55,6 +56,7 @@ "family": "1rw", "mask": "true", "vt": "svt", + "mux" : 1, "ports": [ { "address port name": "addr0", @@ -103,6 +105,7 @@ "family": "1rw", "mask": "true", "vt": "svt", + "mux" : 1, "ports": [ { "address port name": "addr0", From f666255c203d1942a8bd2e7fb2f78a5ad67e2232 Mon Sep 17 00:00:00 2001 From: Nayiri Date: Tue, 7 Sep 2021 10:37:01 -0700 Subject: [PATCH 66/81] sim files to technology lib_type --- .../sky130/sky130-tech-gen-files/beginning.json | 9 +-------- src/hammer-vlsi/technology/sky130/sky130.tech.json | 9 +-------- 2 files changed, 2 insertions(+), 16 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json index 6225136db..0c34d59d3 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json @@ -44,18 +44,11 @@ "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", - "provides": [ - { - "lib_type": "technology" - } - ] - }, - { "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", "verilog sim": "tech-sky130-cache/primitives.v", "provides": [ { - "lib_type": "extra" + "lib_type": "technology" } ] } diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index b8f4c4eb0..af43c3f08 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -42,18 +42,11 @@ "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", - "provides": [ - { - "lib_type": "technology" - } - ] - }, - { "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", "verilog sim": "tech-sky130-cache/primitives.v", "provides": [ { - "lib_type": "extra" + "lib_type": "technology" } ] }, From fbed3cfa680c5022fdeb708c7db3be93ffcdad1a Mon Sep 17 00:00:00 2001 From: Nayiri Date: Mon, 20 Sep 2021 14:05:55 -0700 Subject: [PATCH 67/81] shortened corner names to be consistent with other PDKs, changed time_unit from 1ps to 1ns to get correct units in synthesis timing reports --- src/hammer-vlsi/technology/sky130/defaults.yml | 4 ++-- src/hammer-vlsi/technology/sky130/sky130.tech.json | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index bb6347ef5..d42f55656 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -48,13 +48,13 @@ vlsi: # mmmc corners config mmmc_corners: [ { - name: "sky130_fd_sc_hd__ss_100C_1v60", + name: "ss_100C_1v60", type: "setup", voltage: "1.60 V", temp: "100 C" }, { - name: "sky130_fd_sc_hd__ff_n40C_1v95", + name: "ff_n40C_1v95", type: "hold", voltage: "1.95 V", temp: "-40 C" diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index af43c3f08..188983f67 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -1,7 +1,7 @@ { "name": "Skywater 130nm Library", "grid_unit": "0.001", - "time_unit": "1 ps", + "time_unit": "1 ns", "installs": [ { "path": "$SKY130_PDK", From efbb86ae3ddc00fadca3f3a67d8ee777413da7cd Mon Sep 17 00:00:00 2001 From: Nayiri Date: Mon, 20 Sep 2021 14:06:31 -0700 Subject: [PATCH 68/81] shortened corner names to be consistent with other PDKs, changed time_unit from 1ps to 1ns to get correct units in synthesis timing reports --- .../technology/sky130/sky130-tech-gen-files/beginning.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json index 0c34d59d3..302e2b5ee 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json @@ -1,7 +1,7 @@ { "name": "Skywater 130nm Library", "grid_unit": "0.001", - "time_unit": "1 ps", + "time_unit": "1 ns", "installs": [ { "path": "$SKY130_PDK", From 69118417a6859a334077dcc2c1378f214a39cd57 Mon Sep 17 00:00:00 2001 From: Nayiri Date: Mon, 20 Sep 2021 14:29:57 -0700 Subject: [PATCH 69/81] removing gds file field in tech json (forgot to remove when switched to using par.inputs.gds_map_file field --- .../technology/sky130/sky130-tech-gen-files/beginning.json | 3 --- src/hammer-vlsi/technology/sky130/sky130.tech.json | 1 - 2 files changed, 4 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json index 302e2b5ee..ca6cf1c66 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json @@ -20,7 +20,6 @@ "base var": "" } ], - "gds map file": "specified-in-defaults.yml", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { @@ -30,7 +29,6 @@ } ], "additional_drc_text": "", - "lvs decks": [ { "tool name": "calibre", @@ -40,7 +38,6 @@ } ], "additional_lvs_text": "", - "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 188983f67..068994db3 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -20,7 +20,6 @@ "base var": "" } ], - "gds map file": "specified-in-defaults.yml", "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", "drc decks": [ { From 504732fe41cbd93ee6068d3f7f3cc852a3c2a0da Mon Sep 17 00:00:00 2001 From: Nayiri Date: Thu, 23 Sep 2021 10:36:44 -0700 Subject: [PATCH 70/81] added checks for whether file exists --- src/hammer-vlsi/technology/sky130/__init__.py | 13 ++++++++++--- src/hammer-vlsi/technology/sky130/defaults.yml | 10 ++++------ 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index f57c9cebc..e53e1818d 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -22,7 +22,9 @@ class SKY130Tech(HammerTechnology): """ def post_install_script(self) -> None: self.library_name = 'sky130_fd_sc_hd' - self.use_openram = (self.get_setting("technology.sky130.openram_lib") is not "") + # check whether variables were overriden to point to a valid path + self.use_openram = os.path.exists(self.get_setting("technology.sky130.openram_lib")) + self.use_nda_files = (os.path.exists(self.get_setting("technology.sky130.sky130_nda"))) self.setup_sram_cdl() self.setup_cdl() self.setup_verilog() @@ -135,7 +137,8 @@ def setup_lvs_deck(self) -> None: # for name in SKY130Tech.openram_sram_names(): # LVS_DECK_INSERT_LINES += f"LVS BOX {name} \n" # LVS_DECK_INSERT_LINES += f"LVS FILTER {name} OPEN \n" - + + if not self.use_nda_files: return pattern = '.*({}).*\n'.format('|'.join(LVS_DECK_SCRUB_LINES)) matcher = re.compile(pattern) @@ -144,10 +147,12 @@ def setup_lvs_deck(self) -> None: for i in range(len(lvs_decks)): deck = lvs_decks[i] try: - source_path = source_paths[i] + source_path = Path(source_paths[i]) except IndexError: self.logger.error( 'No corresponding source for LVS deck {}'.format(deck)) + if not source_path.exists(): + raise FileNotFoundError(f"LVS deck not found: {source_path}") dest_path = self.expand_tech_cache_path(str(deck.path)) self.ensure_dirs_exist(dest_path) with open(source_path, 'r') as sf: @@ -182,6 +187,8 @@ def setup_sram_cdl(self) -> None: for sram_name in self.openram_sram_names(): old_path = Path(self.get_setting("technology.sky130.openram_lib")) / sram_name / f"{sram_name}.lvs.sp" new_path = self.expand_tech_cache_path(f'tech-sky130-cache/{sram_name}/{sram_name}.lvs.sp') + if not old_path.exists(): + raise FileNotFoundError(f"SRAM CDL file not found: {old_path}") self.ensure_dirs_exist(new_path) with open(old_path,'r') as f_old: with open(new_path,'w') as f_new: diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index d42f55656..a6fd7e1dd 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -1,19 +1,17 @@ # Settings for the sky130 technology technology.sky130: # Override these in project - sky130_pdk: "PATH-TO-SKY130_PDK" + sky130A: "PATH-TO-sky130A" # required + sky130_pdk: "PATH-TO-skywater-pdk" sky130_nda: "PATH-TO-skywater-src-nda" - sky130A: "PATH-TO-SKY130A_DIR" - # Set one of these if using SRAMs # DFFRAM currently not supported - openram_lib: "" # path to sky130_fd_bd_sram/macros - dffram_lib: "" # path to dffram/compiler/build + openram_lib: "PATH-TO-sky130_fd_bd_sram/macros" + dffram_lib: "PATH-TO-dffram/compiler/build" # Shouldn't need to change these pdk_home: "${technology.sky130.sky130_nda}/s8/V2.0.1" pdk_home_meta: lazysubst - lvs_deck_sources: - "${technology.sky130.pdk_home}/LVS/Calibre/lvsControlFile_s8" lvs_deck_sources_meta: lazysubst From 7b475984733ecc851f0fe160fe5e527f0c16d23a Mon Sep 17 00:00:00 2001 From: Nayiri Date: Thu, 23 Sep 2021 10:59:15 -0700 Subject: [PATCH 71/81] making nda files optional in PDK setup --- .../sky130-tech-gen-files/beginning.json | 27 ---------- .../sky130-tech-gen-files/beginning_nda.json | 49 +++++++++++++++++++ .../technology/sky130/sky130-tech-gen.py | 13 +++-- .../technology/sky130/sky130.tech.json | 4 -- 4 files changed, 57 insertions(+), 36 deletions(-) create mode 100644 src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning_nda.json diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json index ca6cf1c66..aa27bf74f 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json @@ -3,14 +3,6 @@ "grid_unit": "0.001", "time_unit": "1 ns", "installs": [ - { - "path": "$SKY130_PDK", - "base var": "technology.sky130.sky130_pdk" - }, - { - "path": "$SKY130_NDA", - "base var": "technology.sky130.sky130_nda" - }, { "path": "$SKY130A", "base var": "technology.sky130.sky130A" @@ -20,28 +12,9 @@ "base var": "" } ], - "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", - "drc decks": [ - { - "tool name": "calibre", - "deck name": "all_drc", - "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" - } - ], - "additional_drc_text": "", - "lvs decks": [ - { - "tool name": "calibre", - "deck name": "all_lvs", - "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", - "path": "tech-sky130-cache/lvsControlFile_s8" - } - ], - "additional_lvs_text": "", "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", - "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", "verilog sim": "tech-sky130-cache/primitives.v", "provides": [ { diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning_nda.json b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning_nda.json new file mode 100644 index 000000000..d3a27a59a --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning_nda.json @@ -0,0 +1,49 @@ +{ + "name": "Skywater 130nm Library", + "grid_unit": "0.001", + "time_unit": "1 ns", + "installs": [ + { + "path": "$SKY130_NDA", + "base var": "technology.sky130.sky130_nda" + }, + { + "path": "$SKY130A", + "base var": "technology.sky130.sky130A" + }, + { + "path": "tech-sky130-cache", + "base var": "" + } + ], + "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "drc decks": [ + { + "tool name": "calibre", + "deck name": "all_drc", + "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" + } + ], + "additional_drc_text": "", + "lvs decks": [ + { + "tool name": "calibre", + "deck name": "all_lvs", + "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", + "path": "tech-sky130-cache/lvsControlFile_s8" + } + ], + "additional_lvs_text": "", + "libraries": [ + { + "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", + "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", + "verilog sim": "tech-sky130-cache/primitives.v", + "provides": [ + { + "lib_type": "technology" + } + ] + } + ] +} \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py index 158e426ea..4dfc57751 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py @@ -6,16 +6,19 @@ import os from pathlib import Path +use_nda_files=False library='sky130_fd_sc_hd' PDK_ROOT = os.getenv('PDK_ROOT') if PDK_ROOT is None: - print("Error: Must set $PDK_ROOT to the directory that contains the sky130A directory.") - exit() -SKY130A = os.path.join(PDK_ROOT, 'sky130A') + print("Error: Must set $PDK_ROOT to the directory that contains skywater-pdk and the root of the sky130A install.") + exit() +SKY130A = os.path.join(PDK_ROOT, 'share/pdk/sky130A') -with open('sky130-tech-gen-files/beginning.json', 'r') as f: - data = json.load(f) +if use_nda_files: + with open('sky130-tech-gen-files/beginning_nda.json', 'r') as f: data = json.load(f) +else: + with open('sky130-tech-gen-files/beginning.json', 'r') as f: data = json.load(f) with open('sky130-tech-gen-files/cells.json', 'r') as f: cells = json.load(f) diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index 068994db3..c08e2dc9c 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -3,10 +3,6 @@ "grid_unit": "0.001", "time_unit": "1 ns", "installs": [ - { - "path": "$SKY130_PDK", - "base var": "technology.sky130.sky130_pdk" - }, { "path": "$SKY130_NDA", "base var": "technology.sky130.sky130_nda" From 436335dac117aab4ad5e4d3c4531ec579d671697 Mon Sep 17 00:00:00 2001 From: Nayiri Date: Thu, 23 Sep 2021 11:00:54 -0700 Subject: [PATCH 72/81] making nda files optional in PDK setup --- src/hammer-vlsi/technology/sky130/sky130-tech-gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py index 4dfc57751..f2a93b0f1 100644 --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py +++ b/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py @@ -6,7 +6,7 @@ import os from pathlib import Path -use_nda_files=False +use_nda_files=True library='sky130_fd_sc_hd' PDK_ROOT = os.getenv('PDK_ROOT') From ab16d9951ac88d4f19d40bd2d920498bfed6633b Mon Sep 17 00:00:00 2001 From: Nayiri <38256927+nayiri-k@users.noreply.github.com> Date: Fri, 24 Sep 2021 11:55:18 -0700 Subject: [PATCH 73/81] Update README.md --- src/hammer-vlsi/technology/sky130/README.md | 39 +++++++++++---------- 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/README.md b/src/hammer-vlsi/technology/sky130/README.md index ce663b871..a81f06ffb 100644 --- a/src/hammer-vlsi/technology/sky130/README.md +++ b/src/hammer-vlsi/technology/sky130/README.md @@ -2,7 +2,7 @@ Sky130 Technology Library ========================= HAMMER now supports the Skywater 130nm Technology process. The [SkyWater Open Source PDK](https://skywater-pdk.readthedocs.io/) is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit (PDK) and related resources, which can be used to create manufacturable designs at SkyWater’s facility. The Skywater 130nm PDK files are located in a repo called [skywater-pdk](https://github.com/google/skywater-pdk/) A tool called [Open-PDKs (open_pdks)](https://github.com/RTimothyEdwards/open_pdks/) was developed to generate all the files typically found in a PDK. -Open-PDKs uses the contents in ``skywater-pdk``, and outputs files to a directory called ``sky130A``. +Open-PDKs uses the contents in `skywater-pdk`, and outputs files to a directory called `sky130A`. [OpenLANE](https://github.com/efabless/openlane/) is an open-source RTL to GDSII VLSI flow that supports Sky130. @@ -14,22 +14,22 @@ PDK Structure OpenLANE expects a certain file structure for the Sky130 PDK. We recommend adhering to this file structure for Hammer as well. -All the files reside in a root folder (named something like ``skywater`` or ``sky130``). -The environment variable ``$PDK_ROOT`` should be set to this folder's path: +All the files reside in a root folder (named something like `skywater` or `sky130`). +The environment variable `$PDK_ROOT` should be set to this folder's path: export PDK_ROOT= -``$PDK_ROOT`` contains the following: +`$PDK_ROOT` contains the following: -* ``skywater-pdk`` +* `skywater-pdk` * Original PDK source files -* ``open_pdks`` +* `open_pdks` * install of Open-PDKs tool -* ``sky130A`` +* `share/pdk/sky130A` * output files from Open-PDKs compilation process @@ -37,7 +37,7 @@ NDA Files --------- Using commercial VLSI tools with this process requires files that are currently under NDA. If you have access to these, you will be able to use the Hammer VLSI flow out-of-the-box with the Sky130 process. -Some of these NDA files, such as the Calibre DRC/LVS decks, rely on the environment variable ``$PDK_HOME`` containing the path to the version of the NDA files you are using. +Some of these NDA files, such as the Calibre DRC/LVS decks, rely on the environment variable `$PDK_HOME` containing the path to the version of the NDA files you are using. You may set it in the Hammer plugin, or as follows: export PDK_HOME=/s8/ @@ -47,10 +47,10 @@ Prerequisites for PDK Setup * [Magic](http://opencircuitdesign.com/magic/) - * required for ``open_pdks`` file generation - * tricky to install, closely follow the directions on the ``Install`` page of the website + * required for `open_pdks` file generation + * tricky to install, closely follow the directions on the `Install` page of the website - * as the directions indicate, you will likely need to manually specify the location of the Tcl/Tk package installation using ``--with-tcl`` and ``--with-tk`` + * as the directions indicate, you will likely need to manually specify the location of the Tcl/Tk package installation using `--with-tcl` and `--with-tk` If using conda, these installs alone caused the Magic install to work: @@ -58,9 +58,16 @@ Prerequisites for PDK Setup conda install -c anaconda tk conda install -c anaconda libglu +OpenRAM SRAMs +------------- +TODO: add overview here + + git clone https://github.com/efabless/sky130_sram_macros.git + + PDK Setup --------- -In ``$PDK_ROOT``, clone the skywater-pdk repo and generate the liberty files for each library: +In `$PDK_ROOT`, clone the skywater-pdk repo and generate the liberty files for each library: git clone https://github.com/google/skywater-pdk.git cd skywater-pdk @@ -70,7 +77,7 @@ In ``$PDK_ROOT``, clone the skywater-pdk repo and generate the liberty files for # Regenerate liberty files make timing -Again in ``$PDK_ROOT``, clone the open_pdks repo and run the install process to generate the ``sky130A`` directory: +Again in `$PDK_ROOT`, clone the open_pdks repo and run the install process to generate the `sky130A` directory: git clone https://github.com/RTimothyEdwards/open_pdks.git cd open_pdks @@ -81,11 +88,7 @@ Again in ``$PDK_ROOT``, clone the open_pdks repo and run the install process to make make install -OpenRAM SRAMs -------------- -TODO: add overview here - - git clone https://github.com/efabless/sky130_sram_macros.git +This generates all the Sky130 PDK files and installs them to `$PDK_ROOT/share/pdk/sky130A` Known DRC Issues ---------------- From 6fc4b3306723749f22029088f784cf17f872f00c Mon Sep 17 00:00:00 2001 From: Nayiri Date: Sun, 10 Oct 2021 14:26:38 -0700 Subject: [PATCH 74/81] moved files to extra directory --- src/hammer-vlsi/technology/sky130/__init__.py | 8 +- .../technology/sky130/extra/cells-gen.py | 27 ++ .../technology/sky130/extra/cells.txt | 437 ++++++++++++++++++ .../sky130-tech-gen-files/beginning.json | 0 .../sky130-tech-gen-files/beginning_nda.json | 0 .../sky130-tech-gen-files/cells.json | 0 .../sky130-tech-gen-files/sites.json | 0 .../sky130-tech-gen-files/stackups.json | 0 .../sky130/{ => extra}/sky130-tech-gen.py | 24 +- .../sky130/{ => extra}/sky130_lefpin.map | 0 .../sky130/{ => extra}/sram-cache-gen.py | 0 .../technology/sky130/{ => extra}/srams.txt | 0 .../technology/sky130/sky130.tech.json | 27 +- 13 files changed, 486 insertions(+), 37 deletions(-) create mode 100644 src/hammer-vlsi/technology/sky130/extra/cells-gen.py create mode 100644 src/hammer-vlsi/technology/sky130/extra/cells.txt rename src/hammer-vlsi/technology/sky130/{ => extra}/sky130-tech-gen-files/beginning.json (100%) rename src/hammer-vlsi/technology/sky130/{ => extra}/sky130-tech-gen-files/beginning_nda.json (100%) rename src/hammer-vlsi/technology/sky130/{ => extra}/sky130-tech-gen-files/cells.json (100%) rename src/hammer-vlsi/technology/sky130/{ => extra}/sky130-tech-gen-files/sites.json (100%) rename src/hammer-vlsi/technology/sky130/{ => extra}/sky130-tech-gen-files/stackups.json (100%) rename src/hammer-vlsi/technology/sky130/{ => extra}/sky130-tech-gen.py (78%) mode change 100644 => 100755 rename src/hammer-vlsi/technology/sky130/{ => extra}/sky130_lefpin.map (100%) rename src/hammer-vlsi/technology/sky130/{ => extra}/sram-cache-gen.py (100%) rename src/hammer-vlsi/technology/sky130/{ => extra}/srams.txt (100%) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index e53e1818d..b7f8067af 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -256,12 +256,12 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: # Clock attributes [get_db -category cts] ########################################################## #------------------------------------------------------------------------------- -#set_db cts_target_skew .15 -#set_db cts_target_max_transition_time .3 -#set_db cts_update_io_latency false +set_db cts_target_skew .15 +set_db cts_target_max_transition_time .3 +set_db cts_update_io_latency false # set_db cts_use_inverters true -# set_db cts_buffer_cells "clkbuf clkdlybuf4s15 clkdlybuf4s18 clkdlybuf4s25 clkdlybuf4s50" +# set_db cts_buffer_cells "sky130_fd_sc_hd__clkbuf_1 sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_16" # set_db cts_inverter_cells "clkinv clkinvlp" # set_db cts_clock_gating_cells "CKLHQD1BWP30P140HVT CKLHQD2BWP30P140HVT CKLHQD3BWP30P140HVT CKLHQD4BWP30P140HVT CKLHQD6BWP30P140HVT CKLHQD8BWP30P140HVT CKLHQD12BWP30P140HVT CKLHQD16BWP30P140HVT CKLHQD20BWP30P140HVT CKLHQD24BWP30P140HVT CKLNQD1BWP30P140HVT CKLNQD2BWP30P140HVT CKLNQD3BWP30P140HVT CKLNQD4BWP30P140HVT CKLNQD6BWP30P140HVT CKLNQD8BWP30P140HVT CKLNQD12BWP30P140HVT CKLNQD16BWP30P140HVT CKLNQD20BWP30P140HVT CKLNQD24BWP30P140HVT" diff --git a/src/hammer-vlsi/technology/sky130/extra/cells-gen.py b/src/hammer-vlsi/technology/sky130/extra/cells-gen.py new file mode 100644 index 000000000..3c0feaf68 --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/extra/cells-gen.py @@ -0,0 +1,27 @@ +''' + Purpose: generate list of standard cells in skywater library + Usage: + export PDK_ROOT= + python cells-gen.py + Output: + cells.txt: list of all cell names, one per line. +''' +import os +PDK_ROOT = os.getenv('PDK_ROOT') +if PDK_ROOT is None: + print("Error: Must set $PDK_ROOT to the directory that contains skywater-pdk and the root of the sky130A install.") + exit() + +SKYWATER_PDK = os.path.join(PDK_ROOT, 'skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells') +cells = os.listdir(SKYWATER_PDK) +cell_names = [] +for cell in cells: + files = os.listdir(os.path.join(SKYWATER_PDK,cell)) + for f in files: + if '.gds' in f: + cell_name = f.split('.')[0] + cell_names.append(cell_name) + +with open('cells.txt','w') as f: + for cell_name in cell_names: + f.write(cell_name+'\n') \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/extra/cells.txt b/src/hammer-vlsi/technology/sky130/extra/cells.txt new file mode 100644 index 000000000..79810c5cd --- /dev/null +++ b/src/hammer-vlsi/technology/sky130/extra/cells.txt @@ -0,0 +1,437 @@ +sky130_fd_sc_hd__a2111o_1 +sky130_fd_sc_hd__a2111o_2 +sky130_fd_sc_hd__a2111o_4 +sky130_fd_sc_hd__a2111oi_0 +sky130_fd_sc_hd__a2111oi_1 +sky130_fd_sc_hd__a2111oi_2 +sky130_fd_sc_hd__a2111oi_4 +sky130_fd_sc_hd__a211o_1 +sky130_fd_sc_hd__a211o_2 +sky130_fd_sc_hd__a211o_4 +sky130_fd_sc_hd__a211oi_1 +sky130_fd_sc_hd__a211oi_2 +sky130_fd_sc_hd__a211oi_4 +sky130_fd_sc_hd__a21bo_1 +sky130_fd_sc_hd__a21bo_2 +sky130_fd_sc_hd__a21bo_4 +sky130_fd_sc_hd__a21boi_0 +sky130_fd_sc_hd__a21boi_1 +sky130_fd_sc_hd__a21boi_2 +sky130_fd_sc_hd__a21boi_4 +sky130_fd_sc_hd__a21o_1 +sky130_fd_sc_hd__a21o_2 +sky130_fd_sc_hd__a21o_4 +sky130_fd_sc_hd__a21oi_1 +sky130_fd_sc_hd__a21oi_2 +sky130_fd_sc_hd__a21oi_4 +sky130_fd_sc_hd__a221o_1 +sky130_fd_sc_hd__a221o_2 +sky130_fd_sc_hd__a221o_4 +sky130_fd_sc_hd__a221oi_1 +sky130_fd_sc_hd__a221oi_2 +sky130_fd_sc_hd__a221oi_4 +sky130_fd_sc_hd__a222oi_1 +sky130_fd_sc_hd__a22o_1 +sky130_fd_sc_hd__a22o_2 +sky130_fd_sc_hd__a22o_4 +sky130_fd_sc_hd__a22oi_1 +sky130_fd_sc_hd__a22oi_2 +sky130_fd_sc_hd__a22oi_4 +sky130_fd_sc_hd__a2bb2o_1 +sky130_fd_sc_hd__a2bb2o_2 +sky130_fd_sc_hd__a2bb2o_4 +sky130_fd_sc_hd__a2bb2oi_1 +sky130_fd_sc_hd__a2bb2oi_2 +sky130_fd_sc_hd__a2bb2oi_4 +sky130_fd_sc_hd__a311o_1 +sky130_fd_sc_hd__a311o_2 +sky130_fd_sc_hd__a311o_4 +sky130_fd_sc_hd__a311oi_1 +sky130_fd_sc_hd__a311oi_2 +sky130_fd_sc_hd__a311oi_4 +sky130_fd_sc_hd__a31o_1 +sky130_fd_sc_hd__a31o_2 +sky130_fd_sc_hd__a31o_4 +sky130_fd_sc_hd__a31oi_1 +sky130_fd_sc_hd__a31oi_2 +sky130_fd_sc_hd__a31oi_4 +sky130_fd_sc_hd__a32o_1 +sky130_fd_sc_hd__a32o_2 +sky130_fd_sc_hd__a32o_4 +sky130_fd_sc_hd__a32oi_1 +sky130_fd_sc_hd__a32oi_2 +sky130_fd_sc_hd__a32oi_4 +sky130_fd_sc_hd__a41o_1 +sky130_fd_sc_hd__a41o_2 +sky130_fd_sc_hd__a41o_4 +sky130_fd_sc_hd__a41oi_1 +sky130_fd_sc_hd__a41oi_2 +sky130_fd_sc_hd__a41oi_4 +sky130_fd_sc_hd__and2_0 +sky130_fd_sc_hd__and2_1 +sky130_fd_sc_hd__and2_2 +sky130_fd_sc_hd__and2_4 +sky130_fd_sc_hd__and2b_1 +sky130_fd_sc_hd__and2b_2 +sky130_fd_sc_hd__and2b_4 +sky130_fd_sc_hd__and3_1 +sky130_fd_sc_hd__and3_2 +sky130_fd_sc_hd__and3_4 +sky130_fd_sc_hd__and3b_1 +sky130_fd_sc_hd__and3b_2 +sky130_fd_sc_hd__and3b_4 +sky130_fd_sc_hd__and4_1 +sky130_fd_sc_hd__and4_2 +sky130_fd_sc_hd__and4_4 +sky130_fd_sc_hd__and4b_1 +sky130_fd_sc_hd__and4b_2 +sky130_fd_sc_hd__and4b_4 +sky130_fd_sc_hd__and4bb_1 +sky130_fd_sc_hd__and4bb_2 +sky130_fd_sc_hd__and4bb_4 +sky130_fd_sc_hd__buf_1 +sky130_fd_sc_hd__buf_12 +sky130_fd_sc_hd__buf_16 +sky130_fd_sc_hd__buf_2 +sky130_fd_sc_hd__buf_4 +sky130_fd_sc_hd__buf_6 +sky130_fd_sc_hd__buf_8 +sky130_fd_sc_hd__bufbuf_16 +sky130_fd_sc_hd__bufbuf_8 +sky130_fd_sc_hd__bufinv_16 +sky130_fd_sc_hd__bufinv_8 +sky130_fd_sc_hd__clkbuf_1 +sky130_fd_sc_hd__clkbuf_16 +sky130_fd_sc_hd__clkbuf_2 +sky130_fd_sc_hd__clkbuf_4 +sky130_fd_sc_hd__clkbuf_8 +sky130_fd_sc_hd__clkdlybuf4s15_1 +sky130_fd_sc_hd__clkdlybuf4s15_2 +sky130_fd_sc_hd__clkdlybuf4s18_1 +sky130_fd_sc_hd__clkdlybuf4s18_2 +sky130_fd_sc_hd__clkdlybuf4s25_1 +sky130_fd_sc_hd__clkdlybuf4s25_2 +sky130_fd_sc_hd__clkdlybuf4s50_1 +sky130_fd_sc_hd__clkdlybuf4s50_2 +sky130_fd_sc_hd__clkinv_1 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--git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json b/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen-files/beginning.json similarity index 100% rename from src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning.json rename to src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen-files/beginning.json diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning_nda.json b/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen-files/beginning_nda.json similarity index 100% rename from src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/beginning_nda.json rename to src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen-files/beginning_nda.json diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/cells.json b/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen-files/cells.json similarity index 100% rename from src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/cells.json rename to src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen-files/cells.json diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/sites.json b/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen-files/sites.json similarity index 100% rename from src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/sites.json rename to src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen-files/sites.json diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/stackups.json b/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen-files/stackups.json similarity index 100% rename from src/hammer-vlsi/technology/sky130/sky130-tech-gen-files/stackups.json rename to src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen-files/stackups.json diff --git a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py b/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen.py old mode 100644 new mode 100755 similarity index 78% rename from src/hammer-vlsi/technology/sky130/sky130-tech-gen.py rename to src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen.py index f2a93b0f1..f61364bac --- a/src/hammer-vlsi/technology/sky130/sky130-tech-gen.py +++ b/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen.py @@ -1,12 +1,17 @@ -# usage: -# >> export PDK_ROOT= -# >> python sky130-tech-gen.py +''' + Purpose: generate the json file required by the Hammer Sky130 tech plugin + Usage: + export PDK_ROOT= + python sky130-tech-gen.py + Output: + sky130.tech.json: specifies Sky130 PDK file locations and various details +''' import json import os from pathlib import Path -use_nda_files=True +use_nda_files=False library='sky130_fd_sc_hd' PDK_ROOT = os.getenv('PDK_ROOT') @@ -28,12 +33,15 @@ SKYWATER_LIBS = os.path.join('$SKY130A','libs.ref',library) LIBRARY_PATH = os.path.join(SKY130A,'libs.ref',library,'lib') -lib_corners=os.listdir(LIBRARY_PATH) -for cornerfilename in lib_corners: +lib_corner_files=os.listdir(LIBRARY_PATH) +for cornerfilename in lib_corner_files: if (not (library in cornerfilename) ) : continue - if ('ccsnoise' in cornerfilename): continue + if ('ccsnoise' in cornerfilename): continue # ignore duplicate corner.lib/corner_ccsnoise.lib files + + tmp = cornerfilename.replace('.lib','') + if (tmp+'_ccsnoise.lib' in lib_corner_files): + cornerfilename=tmp+'_ccsnoise.lib' # use ccsnoise version of lib file - tmp = cornerfilename.replace('.lib','__') cornername = tmp.split('__')[1] cornerparts = cornername.split('_') diff --git a/src/hammer-vlsi/technology/sky130/sky130_lefpin.map b/src/hammer-vlsi/technology/sky130/extra/sky130_lefpin.map similarity index 100% rename from src/hammer-vlsi/technology/sky130/sky130_lefpin.map rename to src/hammer-vlsi/technology/sky130/extra/sky130_lefpin.map diff --git a/src/hammer-vlsi/technology/sky130/sram-cache-gen.py b/src/hammer-vlsi/technology/sky130/extra/sram-cache-gen.py similarity index 100% rename from src/hammer-vlsi/technology/sky130/sram-cache-gen.py rename to src/hammer-vlsi/technology/sky130/extra/sram-cache-gen.py diff --git a/src/hammer-vlsi/technology/sky130/srams.txt b/src/hammer-vlsi/technology/sky130/extra/srams.txt similarity index 100% rename from src/hammer-vlsi/technology/sky130/srams.txt rename to src/hammer-vlsi/technology/sky130/extra/srams.txt diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index c08e2dc9c..dc6fff49d 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -3,10 +3,6 @@ "grid_unit": "0.001", "time_unit": "1 ns", "installs": [ - { - "path": "$SKY130_NDA", - "base var": "technology.sky130.sky130_nda" - }, { "path": "$SKY130A", "base var": "technology.sky130.sky130A" @@ -16,28 +12,9 @@ "base var": "" } ], - "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", - "drc decks": [ - { - "tool name": "calibre", - "deck name": "all_drc", - "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" - } - ], - "additional_drc_text": "", - "lvs decks": [ - { - "tool name": "calibre", - "deck name": "all_lvs", - "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", - "path": "tech-sky130-cache/lvsControlFile_s8" - } - ], - "additional_lvs_text": "", "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", - "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", "verilog sim": "tech-sky130-cache/primitives.v", "provides": [ { @@ -156,7 +133,7 @@ ] }, { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95_ccsnoise.lib", "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", @@ -310,7 +287,7 @@ ] }, { - "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60.lib", + "nldm liberty file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_n40C_1v60_ccsnoise.lib", "verilog sim": "tech-sky130-cache/sky130_fd_sc_hd.v", "lef file": "$SKY130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "spice file": "tech-sky130-cache/sky130_fd_sc_hd.cdl", From 34ba6e7cc07d4a3191a812badd3a44ca76471855 Mon Sep 17 00:00:00 2001 From: Nayiri Date: Sun, 10 Oct 2021 14:27:10 -0700 Subject: [PATCH 75/81] moved files to extra directory --- src/hammer-vlsi/technology/sky130/defaults.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index a6fd7e1dd..d7b6d37d5 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -81,5 +81,5 @@ technology.core: par.inputs: gds_merge: true gds_map_mode: manual - gds_map_file: "${vlsi.builtins.hammer_vlsi_path}/technology/sky130/sky130_lefpin.map" + gds_map_file: "${vlsi.builtins.hammer_vlsi_path}/technology/sky130/extra/sky130_lefpin.map" gds_map_file_meta: lazysubst \ No newline at end of file From 6f84a71278996aa6ee1f75f5fe06c33bdaefb32a Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 15 Oct 2021 16:04:31 -0700 Subject: [PATCH 76/81] merged new master changes --- .../sky130/extra/sky130-tech-gen.py | 4 ++-- .../technology/sky130/sky130.tech.json | 23 +++++++++++++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen.py b/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen.py index f61364bac..81fedb424 100755 --- a/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen.py +++ b/src/hammer-vlsi/technology/sky130/extra/sky130-tech-gen.py @@ -11,7 +11,7 @@ import os from pathlib import Path -use_nda_files=False +use_nda_files=True library='sky130_fd_sc_hd' PDK_ROOT = os.getenv('PDK_ROOT') @@ -90,5 +90,5 @@ sites = json.load(f) data["sites"] = sites["sites"] -with open('sky130.tech.json', 'w') as f: +with open('../sky130.tech.json', 'w') as f: json.dump(data, f, indent=2) \ No newline at end of file diff --git a/src/hammer-vlsi/technology/sky130/sky130.tech.json b/src/hammer-vlsi/technology/sky130/sky130.tech.json index dc6fff49d..3365668bd 100644 --- a/src/hammer-vlsi/technology/sky130/sky130.tech.json +++ b/src/hammer-vlsi/technology/sky130/sky130.tech.json @@ -3,6 +3,10 @@ "grid_unit": "0.001", "time_unit": "1 ns", "installs": [ + { + "path": "$SKY130_NDA", + "base var": "technology.sky130.sky130_nda" + }, { "path": "$SKY130A", "base var": "technology.sky130.sky130A" @@ -12,9 +16,28 @@ "base var": "" } ], + "layer map file": "$SKY130_NDA/s8/V2.0.1/VirtuosoOA/libs/technology_library/technology_library.layermap", + "drc decks": [ + { + "tool name": "calibre", + "deck name": "all_drc", + "path": "$SKY130_NDA/s8/V2.0.1/DRC/Calibre/s8_drcRules" + } + ], + "additional_drc_text": "", + "lvs decks": [ + { + "tool name": "calibre", + "deck name": "all_lvs", + "old path": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/lvsRules_s8", + "path": "tech-sky130-cache/lvsControlFile_s8" + } + ], + "additional_lvs_text": "", "libraries": [ { "lef file": "tech-sky130-cache/sky130_fd_sc_hd.tlef", + "spice file": "$SKY130_NDA/s8/V2.0.1/LVS/Calibre/source.cdl", "verilog sim": "tech-sky130-cache/primitives.v", "provides": [ { From 60376b7d097350bffb4dc0dd67d3ad5278c1ad0d Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 15 Oct 2021 16:11:40 -0700 Subject: [PATCH 77/81] adding typical corner to mmmc --- src/hammer-vlsi/technology/sky130/defaults.yml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index d7b6d37d5..e78769f79 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -56,6 +56,12 @@ vlsi: type: "hold", voltage: "1.95 V", temp: "-40 C" + }, + { + name: "tt_025C_1v80", + type: "typical", + voltage: "1.80 V", + temp: "25 C" } ] technology: From 5b18c53464161801f5b802d8f3d33f07f5626c54 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 15 Oct 2021 16:25:39 -0700 Subject: [PATCH 78/81] adding typical corner to mmmc --- src/hammer-vlsi/technology/sky130/defaults.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hammer-vlsi/technology/sky130/defaults.yml b/src/hammer-vlsi/technology/sky130/defaults.yml index e78769f79..ab35e5aae 100644 --- a/src/hammer-vlsi/technology/sky130/defaults.yml +++ b/src/hammer-vlsi/technology/sky130/defaults.yml @@ -59,7 +59,7 @@ vlsi: }, { name: "tt_025C_1v80", - type: "typical", + type: "extra", voltage: "1.80 V", temp: "25 C" } From 1d34eebf1c717de459aa0070f90e8c132b304ee4 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 15 Oct 2021 23:12:12 -0700 Subject: [PATCH 79/81] moved helper functions to HammerTechnology --- src/hammer-tech/hammer_tech.py | 14 ++ src/hammer-vlsi/technology/sky130/__init__.py | 132 ++++-------------- 2 files changed, 43 insertions(+), 103 deletions(-) diff --git a/src/hammer-tech/hammer_tech.py b/src/hammer-tech/hammer_tech.py index f113c6b70..b3dc3fc5a 100644 --- a/src/hammer-tech/hammer_tech.py +++ b/src/hammer-tech/hammer_tech.py @@ -361,6 +361,20 @@ def cache_dir(self, value: str) -> None: self._cachedir = value # type: str # Ensure the cache_dir exists. os.makedirs(value, mode=0o700, exist_ok=True) + + # @classmethod + def expand_tech_cache_path(self, path) -> str: + """ Replace occurrences of the cache directory's basename with + the full path to the cache dir.""" + cache_dir_basename = os.path.basename(self.cache_dir) + return path.replace(cache_dir_basename, self.cache_dir) + + # @classmethod + def ensure_dirs_exist(self, path) -> None: + dir_name = os.path.dirname(path) + if not os.path.exists(dir_name): + self.logger.info('Creating directory: {}'.format(dir_name)) + os.makedirs(dir_name) # hammer-vlsi properties. # TODO: deduplicate/put these into an interface to share with HammerTool? diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index b7f8067af..9d60fad68 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -32,23 +32,9 @@ def post_install_script(self) -> None: self.setup_lvs_deck() print('Loaded Sky130 Tech') - # Helper functions - # TODO: add to HammerTechnology - def expand_tech_cache_path(self, path) -> str: - """ Replace occurrences of the cache directory's basename with - the full path to the cache dir.""" - cache_dir_basename = os.path.basename(self.cache_dir) - return path.replace(cache_dir_basename, self.cache_dir) - - def ensure_dirs_exist(self, path) -> None: - dir_name = os.path.dirname(path) - if not os.path.exists(dir_name): - self.logger.info('Creating directory: {}'.format(dir_name)) - os.makedirs(dir_name) - - # Tech setup steps + + # Copy and hack the cdl, replacing pfet_01v8_hvt/nfet_01v8 with phighvt/nshort def setup_cdl(self) -> None: - """ Copy and hack the cdl, replacing pfet_01v8_hvt/nfet_01v8 with phighvt/nshort """ setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) cdl_old_path = setting_dir / 'libs.ref' / self.library_name / 'cdl' / f'{self.library_name}.cdl' @@ -68,12 +54,15 @@ def setup_cdl(self) -> None: f_old.close() f_new.close() + # Copy and hack the verilog + # - .v: remove 'wire 1' and one endif line to fix syntax errors + # - primitives.v: set default nettype to 'wire' instead of 'none' + # (the open-source RTL sim tools don't treat undeclared signals as errors) def setup_verilog(self) -> None: - """ Copy and hack the verilog """ setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) - # fix up .v + # .v verilog_old_path = setting_dir / 'libs.ref' / self.library_name / 'verilog' / f'{self.library_name}.v' if not verilog_old_path.exists(): raise FileNotFoundError(f"Verilog not found: {verilog_old_path}") @@ -91,7 +80,7 @@ def setup_verilog(self) -> None: f_old.close() f_new.close() - # fix up primitives.v + # primitives.v verilog_old_path = setting_dir / 'libs.ref' / self.library_name / 'verilog' / 'primitives.v' if not verilog_old_path.exists(): raise FileNotFoundError(f"Verilog not found: {verilog_old_path}") @@ -108,8 +97,8 @@ def setup_verilog(self) -> None: f_old.close() f_new.close() + # Copy and hack the tech-lef, adding this very important `licon` section def setup_techlef(self) -> None: - """ Copy and hack the tech-lef, adding this very important `licon` section """ setting_dir = self.get_setting("technology.sky130.sky130A") setting_dir = Path(setting_dir) tlef_old_path = setting_dir / 'libs.ref' / self.library_name / 'techlef' / f'{self.library_name}.tlef' @@ -129,15 +118,8 @@ def setup_techlef(self) -> None: f_old.close() f_new.close() + # Remove conflicting specification statements found in PDK LVS decks def setup_lvs_deck(self) -> None: - """Remove conflicting specification statements found in PDK LVS decks.""" - - # if using OpenRAM SRAMs, LVS BOX these to ignore in LVS check - # if self.use_openram: - # for name in SKY130Tech.openram_sram_names(): - # LVS_DECK_INSERT_LINES += f"LVS BOX {name} \n" - # LVS_DECK_INSERT_LINES += f"LVS FILTER {name} OPEN \n" - if not self.use_nda_files: return pattern = '.*({}).*\n'.format('|'.join(LVS_DECK_SCRUB_LINES)) matcher = re.compile(pattern) @@ -165,10 +147,7 @@ def setup_lvs_deck(self) -> None: def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]: hooks = {"innovus": [ HammerTool.make_post_insertion_hook("init_design", sky130_innovus_settings), - HammerTool.make_pre_insertion_hook("place_tap_cells", sky130_add_endcaps), - HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets), - HammerTool.make_post_insertion_hook("place_opt_design", sky130_add_tieoffs), - HammerTool.make_pre_insertion_hook("write_design", sky130_connect_nets), + HammerTool.make_pre_insertion_hook("power_straps", sky130_power_nets) ]} return hooks.get(tool_name, []) @@ -218,6 +197,11 @@ def setup_sram_cdl(self) -> None: LVS FILTER D OPEN LAYOUT ''' +# black-box SRAMs during LVS +for name in SKY130Tech.openram_sram_names(): + LVS_DECK_INSERT_LINES += f"LVS BOX {name} \n" + LVS_DECK_INSERT_LINES += f"LVS FILTER {name} OPEN \n" + # various Innovus database settings def sky130_innovus_settings(ht: HammerTool) -> bool: assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" @@ -249,101 +233,43 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: set_db opt_area_recovery true set_db opt_post_route_area_reclaim setup_aware set_db opt_fix_hold_verbose true -# set_db opt_fix_hold_lib_cells "BUFFD0BWP30P140HVT BUFFD1BWP30P140HVT BUFFD2BWP30P140HVT BUFFD3BWP30P140HVT BUFFD4BWP30P140HVT BUFFD6BWP30P140HVT BUFFD8BWP30P140HVT BUFFD12BWP30P140HVT BUFFD16BWP30P140HVT BUFFD20BWP30P140HVT BUFFD24BWP30P140HVT DEL025D1BWP30P140HVT" - ########################################################## # Clock attributes [get_db -category cts] ########################################################## #------------------------------------------------------------------------------- -set_db cts_target_skew .15 +set_db cts_target_skew 0.03 +set_db cts_max_fanout 10 set_db cts_target_max_transition_time .3 set_db cts_update_io_latency false - -# set_db cts_use_inverters true -# set_db cts_buffer_cells "sky130_fd_sc_hd__clkbuf_1 sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_16" -# set_db cts_inverter_cells "clkinv clkinvlp" -# set_db cts_clock_gating_cells "CKLHQD1BWP30P140HVT CKLHQD2BWP30P140HVT CKLHQD3BWP30P140HVT CKLHQD4BWP30P140HVT CKLHQD6BWP30P140HVT CKLHQD8BWP30P140HVT CKLHQD12BWP30P140HVT CKLHQD16BWP30P140HVT CKLHQD20BWP30P140HVT CKLHQD24BWP30P140HVT CKLNQD1BWP30P140HVT CKLNQD2BWP30P140HVT CKLNQD3BWP30P140HVT CKLNQD4BWP30P140HVT CKLNQD6BWP30P140HVT CKLNQD8BWP30P140HVT CKLNQD12BWP30P140HVT CKLNQD16BWP30P140HVT CKLNQD20BWP30P140HVT CKLNQD24BWP30P140HVT" - +set_db opt_setup_target_slack 0.10 +set_db opt_hold_target_slack 0.10 ########################################################## # Routing attributes [get_db -category route] ########################################################## #------------------------------------------------------------------------------- -set_db route_design_antenna_diode_insertion 1 -set_db route_design_antenna_cell_name "sky130_fd_sc_hd__diode_2" set_db route_design_bottom_routing_layer 2 - -set_db route_design_high_freq_search_repair true -set_db route_design_detail_post_route_spread_wire true -set_db route_design_with_si_driven true -set_db route_design_with_timing_driven true -set_db route_design_concurrent_minimize_via_count_effort high -set_db opt_consider_routing_congestion true -set_db route_design_detail_use_multi_cut_via_effort medium - -set_db cts_target_skew 0.03 -set_db cts_max_fanout 10 -set_db opt_setup_target_slack 0.10 -set_db opt_hold_target_slack 0.10 ''' ) return True - -# TODO: move to Innovus plugin -def sky130_add_endcaps(ht: HammerTool) -> bool: - assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" - assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" - ht.append( - ''' -set_db add_endcaps_boundary_tap true -set_db add_endcaps_left_edge sky130_fd_sc_hd__tap_1 -set_db add_endcaps_right_edge sky130_fd_sc_hd__tap_1 -add_endcaps - ''' - ) - return True - # Pair VDD/VPWR and VSS/VGND nets # these commands are already added in Innovus.write_netlist, # but must also occur before power straps are placed -# TODO: move to Innovus plugin def sky130_power_nets(ht: HammerTool) -> bool: assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" - ht.append( - ''' -connect_global_net VDD -type net -net_base_name VPWR -connect_global_net VSS -type net -net_base_name VGND - ''' - ) - return True - -# TODO: add these two functions into Hammer Innovus plugin -def sky130_add_tieoffs(ht: HammerTool) -> bool: - assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" - assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" - ht.append( - ''' -set_db add_tieoffs_cells sky130_fd_sc_hd__conb_1 -add_tieoffs - ''' - ) - return True - -def sky130_connect_nets(ht: HammerTool) -> bool: - assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par" - assert isinstance(ht, TCLTool), "innovus settings can only run on TCL tools" - ht.append( - ''' -connect_global_net VDD -type pg_pin -pin_base_name VPWR -all -connect_global_net VDD -type pg_pin -pin_base_name VPB -all -connect_global_net VSS -type pg_pin -pin_base_name VGND -all -connect_global_net VSS -type pg_pin -pin_base_name VNB -all - ''' - ) + for pwr_gnd_net in (ht.get_all_power_nets() + ht.get_all_ground_nets()): + if pwr_gnd_net.tie is not None: + ht.verbose_append("connect_global_net {tie} -type net -net_base_name {net}".format(tie=pwr_gnd_net.tie, net=pwr_gnd_net.name)) +# ht.append( +# f''' +# connect_global_net VDD -type net -net_base_name VPWR +# connect_global_net VSS -type net -net_base_name VGND +# ''' +# ) return True tech = SKY130Tech() From 639b6e42d717ee7fbaacf630889471459b7f0396 Mon Sep 17 00:00:00 2001 From: nayiri-k Date: Fri, 15 Oct 2021 23:17:47 -0700 Subject: [PATCH 80/81] reference to sky130 plugin in Hammer docs --- doc/Technology/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/Technology/index.rst b/doc/Technology/index.rst index 341d9b64c..acb01e2b1 100644 --- a/doc/Technology/index.rst +++ b/doc/Technology/index.rst @@ -5,7 +5,7 @@ Technology Setup and Use These guides will walk you through how to set up a technology to be used in Hammer. -You may use the included `free ASAP7 PDK example `__ as a reference when building your own technology plugin. +You may use the included `free ASAP7 PDK `__ or the `open-source Sky130 PDK `__ plugins as reference when building your own technology plugin. .. toctree:: :maxdepth: 2 From 6242b403b61dcd24098226632f623869a097d809 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 15 Oct 2021 23:24:18 -0700 Subject: [PATCH 81/81] small change --- src/hammer-vlsi/technology/sky130/__init__.py | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/hammer-vlsi/technology/sky130/__init__.py b/src/hammer-vlsi/technology/sky130/__init__.py index 9d60fad68..121e1d2d8 100644 --- a/src/hammer-vlsi/technology/sky130/__init__.py +++ b/src/hammer-vlsi/technology/sky130/__init__.py @@ -241,7 +241,6 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: set_db cts_target_skew 0.03 set_db cts_max_fanout 10 set_db cts_target_max_transition_time .3 -set_db cts_update_io_latency false set_db opt_setup_target_slack 0.10 set_db opt_hold_target_slack 0.10 @@ -254,7 +253,6 @@ def sky130_innovus_settings(ht: HammerTool) -> bool: ) return True - # Pair VDD/VPWR and VSS/VGND nets # these commands are already added in Innovus.write_netlist, # but must also occur before power straps are placed @@ -264,12 +262,6 @@ def sky130_power_nets(ht: HammerTool) -> bool: for pwr_gnd_net in (ht.get_all_power_nets() + ht.get_all_ground_nets()): if pwr_gnd_net.tie is not None: ht.verbose_append("connect_global_net {tie} -type net -net_base_name {net}".format(tie=pwr_gnd_net.tie, net=pwr_gnd_net.name)) -# ht.append( -# f''' -# connect_global_net VDD -type net -net_base_name VPWR -# connect_global_net VSS -type net -net_base_name VGND -# ''' -# ) return True tech = SKY130Tech()