diff --git a/build.sbt b/build.sbt index fa75695..6a8ef18 100644 --- a/build.sbt +++ b/build.sbt @@ -4,4 +4,4 @@ version := "1.2" name := "hwacha" -scalaVersion := "2.12.10" +scalaVersion := "2.13.10" diff --git a/src/main/scala/TopLevelConfigs.scala b/src/main/scala/TopLevelConfigs.scala index 63b8e88..413edcc 100644 --- a/src/main/scala/TopLevelConfigs.scala +++ b/src/main/scala/TopLevelConfigs.scala @@ -18,14 +18,17 @@ class WithNLanes(n: Int) extends Config((site, here, up) => { }) class With32BtbEntires extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site) map { r => - r.copy(btb = r.btb.map(_.copy(nEntries = 32))) + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + btb = tp.tileParams.btb.map(_.copy(nEntries = 32)))) } }) class Process28nmConfig extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site) map { r => - r.copy(core = r.core.copy(fpu = r.core.fpu.map(_.copy(sfmaLatency = 3, dfmaLatency = 4)))) + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy( + fpu = tp.tileParams.core.fpu.map(_.copy(sfmaLatency = 3, dfmaLatency = 4))))) } }) diff --git a/src/main/scala/dcc-mem.scala b/src/main/scala/dcc-mem.scala index bbf51c4..1a17efd 100644 --- a/src/main/scala/dcc-mem.scala +++ b/src/main/scala/dcc-mem.scala @@ -128,7 +128,7 @@ class VPU(implicit p: Parameters) extends VXUModule()(p) with BankLogic { opq.suggestName("opqInst") opq.io.enq <> io.op - val bpqs = (io.bpqs zipWithIndex) map { case (enq, i) => + val bpqs = (io.bpqs.zipWithIndex) map { case (enq, i) => val bpq = Module(new Queue(new BPQEntry, nBPQ)) bpq.suggestName("bpqInst") val placntr = Module(new LookAheadCounter(nBPQ, nBPQ)) @@ -152,7 +152,7 @@ class VPU(implicit p: Parameters) extends VXUModule()(p) with BankLogic { val vlen_next = op.vlen - strip val deq_bpqs = strip_to_bmask(strip) - val mask_bpqs_valid = (bpqs_deq zipWithIndex) map { case (bpq, i) => + val mask_bpqs_valid = (bpqs_deq.zipWithIndex) map { case (bpq, i) => !deq_bpqs(i) || bpq.valid } val enq_lpred = op.active.enq_vlu() val enq_spred = op.active.enq_vsu() @@ -187,13 +187,13 @@ class VPU(implicit p: Parameters) extends VXUModule()(p) with BankLogic { } } - (bpqs_deq zipWithIndex) map { case (bpq, i) => + (bpqs_deq.zipWithIndex) map { case (bpq, i) => bpq.ready := fire(mask_bpqs_valid(i), deq_bpqs(i)) } io.pred.valid := fire(io.pred.ready) io.lpred.valid := fire(mask_lpred_ready, enq_lpred) io.spred.valid := fire(mask_spred_ready, enq_spred) - val pred = Vec((bpqs_deq zipWithIndex) map { case (bpq, i) => + val pred = Vec((bpqs_deq.zipWithIndex) map { case (bpq, i) => dgate(deq_bpqs(i), bpq.bits.pred(nSlices-1,0)) }).asUInt io.pred.bits.pred := pred io.lpred.bits := pred diff --git a/src/main/scala/expander.scala b/src/main/scala/expander.scala index bd71690..0f85c84 100644 --- a/src/main/scala/expander.scala +++ b/src/main/scala/expander.scala @@ -185,7 +185,7 @@ class Expander(implicit p: Parameters) extends VXUModule()(p) { } def mark_sram_reads = { - (Seq(preg_vs1, preg_vs2, preg_vs3) zipWithIndex) foreach { + (Seq(preg_vs1, preg_vs2, preg_vs3).zipWithIndex) foreach { case (fn, idx) => { val read_idx = rport_idx(idx) when (rport_valid(idx)) { @@ -415,7 +415,7 @@ class Expander(implicit p: Parameters) extends VXUModule()(p) { } def mark_lop_sreg(sreg: Vec[Bool], nregs: Int) = { - (Seq(preg_vs1, preg_vs2, preg_vs3) zipWithIndex) map { case (fn, i) => + (Seq(preg_vs1, preg_vs2, preg_vs3).zipWithIndex) map { case (fn, i) => if (nregs > i) { val rinfo = fn(seq_exp.reg) sreg(i) := rinfo.valid && rinfo.is_scalar() @@ -441,7 +441,7 @@ class Expander(implicit p: Parameters) extends VXUModule()(p) { (lop: VFVULaneOp) => { lop.fn := seq_exp.fn.vfvu(); mark_lop_sreg(lop.sreg, 1) }) def mark_vipu = { - (Seq(preg_vs1, preg_vs2, preg_vs3) zipWithIndex) foreach { case (fn, idx) => + (Seq(preg_vs1, preg_vs2, preg_vs3).zipWithIndex) foreach { case (fn, idx) => check_assert("pred read" + idx, tick_pred_read(idx), UInt(0)) assert(fn(seq_vipu.reg).valid, "pred op with no predicate") val e = tick_pred_read(idx).s(0) diff --git a/src/main/scala/hwacha.scala b/src/main/scala/hwacha.scala index f9ad5e3..753cf29 100644 --- a/src/main/scala/hwacha.scala +++ b/src/main/scala/hwacha.scala @@ -39,7 +39,9 @@ abstract class HwachaModule(clock: Clock = null, _reset: Bool = null) abstract class HwachaBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with UsesHwachaParameters -abstract trait UsesHwachaParameters extends freechips.rocketchip.tile.HasCoreParameters with UsesHwachaOnlyParameters +abstract trait UsesHwachaParameters extends freechips.rocketchip.tile.HasCoreParameters with UsesHwachaOnlyParameters { + val aluFn = new freechips.rocketchip.rocket.ALUFN +} abstract trait UsesHwachaOnlyParameters { implicit val p: Parameters @@ -250,7 +252,7 @@ class HwachaImp(outer: Hwacha)(implicit p: Parameters) extends LazyRoCCModuleImp mseq.io.op.valid := fire_vxu(mseq.io.op.ready) mseq.io.op.bits <> scalar.io.vxu.bits - (mseq.io.master.clear zipWithIndex) map { case (c, r) => + (mseq.io.master.clear.zipWithIndex) map { case (c, r) => c := vus.map(_.io.mseq.clear(r)).reduce(_&&_) } scalar.io.pending.mseq <> mseq.io.pending @@ -273,7 +275,7 @@ class HwachaImp(outer: Hwacha)(implicit p: Parameters) extends LazyRoCCModuleImp (vus zip mou.io.check.vus) map { case (vu, mocheck) => vu.io.mocheck <> mocheck } (scalar.io.pending.mrt.vus zip vus) map { case (pending, vu) => pending <> vu.io.pending } - (vus zipWithIndex) map { case (vu, i) => + (vus.zipWithIndex) map { case (vu, i) => vu.io.id := UInt(i) vu.io.cfg <> rocc.io.cfg diff --git a/src/main/scala/lane.scala b/src/main/scala/lane.scala index 322ce5c..d8f6ccc 100644 --- a/src/main/scala/lane.scala +++ b/src/main/scala/lane.scala @@ -307,7 +307,7 @@ class Lane(implicit p: Parameters) extends VXUModule()(p) with Packing with Rate banksrw.map { b => b.wpred.pred := Vec(vfcus.map(_.bits.cmp)).asUInt b.wpred.mask := vfcu_vals - (b.wdata zipWithIndex) map { case (bwdata, i) => + (b.wdata.zipWithIndex) map { case (bwdata, i) => bwdata.data := wdata(i) bwdata.pred := wdata_pred(i) } diff --git a/src/main/scala/scalar-decode.scala b/src/main/scala/scalar-decode.scala index d28f629..9a94fc4 100644 --- a/src/main/scala/scalar-decode.scala +++ b/src/main/scala/scalar-decode.scala @@ -3,7 +3,6 @@ package hwacha import Chisel._ import freechips.rocketchip.config._ import HwachaElementInstructions._ -import freechips.rocketchip.rocket.ALU._ import freechips.rocketchip.util._ import ScalarFPUDecode._ @@ -31,7 +30,7 @@ class IntCtrlSigs(implicit p: Parameters) extends HwachaBundle()(p) { val vp_val = Bool() val vp_neg = Bool() val sel_imm = Bits(width = IMM_X.getWidth) - val alu_fn = Bits(width = FN_X.getWidth) + val alu_fn = Bits(width = aluFn.FN_X.getWidth) val alu_dw = Bool() val alu_sel2 = Bits(width = A2_X.getWidth) val alu_sel1 = Bits(width = A1_X.getWidth) @@ -153,267 +152,267 @@ class IntCtrlSigs(implicit p: Parameters) extends HwachaBundle()(p) { } abstract trait VFDecodeTable { - + val aluFn = new freechips.rocketchip.rocket.ALUFN val default: List[BitPat] = - // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? - // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn - // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - List(N,N,N,N,N,RX,N,N,RX,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX + // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? + // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn + // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + List(N,N,N,N,N,RX,N,N,RX,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX val table: Array[(BitPat, List[BitPat])] } object ScalarDecode extends VFDecodeTable { val table: Array[(BitPat, List[BitPat])] = Array( - // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? - // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn - // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - VLSB ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSH ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSD ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSBU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_BU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSHU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_HU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSWU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_WU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSSB ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RS,N,Y,RS,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSSH ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RS,N,Y,RS,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSSW ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RS,N,Y,RS,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSSD ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RS,N,Y,RS,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLAB ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLAH ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLAW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLAD ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLABU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_BU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLAHU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_HU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLAWU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_WU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSAB ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RA,N,Y,RS,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSAH ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RA,N,Y,RS,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSAW ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RA,N,Y,RS,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSAD ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RA,N,Y,RS,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? + // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn + // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + VLSB ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSH ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSD ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSBU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_BU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSHU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_HU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSWU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_WU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSSB ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RS,N,Y,RS,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSSH ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RS,N,Y,RS,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSSW ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RS,N,Y,RS,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSSD ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RS,N,Y,RS,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLAB ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLAH ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLAW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLAD ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLABU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_BU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLAHU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_HU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLAWU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RA,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_L,MT_WU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSAB ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RA,N,Y,RS,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSAH ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RA,N,Y,RS,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSAW ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RA,N,Y,RS,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSAD ->(List[BitPat](Y,Y,N,N,N,RX,N,Y,RA,N,Y,RS,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, Y,SM_S,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLUI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_L,FN_ADD, DW64,A1_ZERO,A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAUIPC ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_L,FN_ADD, DW64,A1_PC, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VADDI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_ADD, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSLLI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_SL, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSLTI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_SLT, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSLTIU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_SLTU,DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VXORI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_XOR, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSRLI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_SR, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSRAI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_SRA, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VORI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_OR, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VANDI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_AND, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VADDIW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_ADD, DW32,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSLLIW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_SL, DW32,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSRLIW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_SR, DW32,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSRAIW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,FN_SRA, DW32,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLUI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_L,aluFn.FN_ADD, DW64,A1_ZERO,A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAUIPC ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_L,aluFn.FN_ADD, DW64,A1_PC, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VADDI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_ADD, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSLLI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_SL, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSLTI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_SLT, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSLTIU ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_SLTU,DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VXORI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_XOR, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSRLI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_SR, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSRAI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_SRA, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VORI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_OR, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VANDI ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_AND, DW64,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VADDIW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_ADD, DW32,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSLLIW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_SL, DW32,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSRLIW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_SR, DW32,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSRAIW ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,N,IMM_I,aluFn.FN_SRA, DW32,A1_RS1, A2_IMM, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VCJAL ->(List[BitPat](Y,Y,N,N,Y,RS,N,N,RX,N,N,RX,N,N,RX,N,Y,IMM_U,FN_ADD, DW64,A1_PC, A2_8, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, Y,N) ++ FX), - VCJALR ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,Y,IMM_U,FN_ADD, DW64,A1_PC, A2_8, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, Y,N) ++ FX), - VFIRST ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,Y) ++ FX), - VFENCE ->(List[BitPat](Y,Y,Y,N,N,RX,N,N,RX,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSTOP ->(List[BitPat](Y,Y,N,Y,N,RX,N,N,RX,N,N,RX,N,N,RX,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX)) + VCJAL ->(List[BitPat](Y,Y,N,N,Y,RS,N,N,RX,N,N,RX,N,N,RX,N,Y,IMM_U,aluFn.FN_ADD, DW64,A1_PC, A2_8, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, Y,N) ++ FX), + VCJALR ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RS,N,N,RX,N,N,RX,N,Y,IMM_U,aluFn.FN_ADD, DW64,A1_PC, A2_8, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, Y,N) ++ FX), + VFIRST ->(List[BitPat](Y,Y,N,N,Y,RS,N,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,Y) ++ FX), + VFENCE ->(List[BitPat](Y,Y,Y,N,N,RX,N,N,RX,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSTOP ->(List[BitPat](Y,Y,N,Y,N,RX,N,N,RX,N,N,RX,N,N,RX,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX)) } object VectorMemoryDecode extends VFDecodeTable { val table: Array[(BitPat, List[BitPat])] = Array( - // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? - // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn - // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - VLB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLBU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_BU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLHU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_HU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLWU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_WU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XWR, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XWR, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XWR, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XWR, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? + // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn + // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + VLB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLBU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_BU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLHU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_HU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLWU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XRD, N,SM_X,MT_WU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XWR, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XWR, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XWR, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_U,M_XWR, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSTB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSTH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSTW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSTD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSTBU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_BU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSTHU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_HU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLSTWU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_WU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSSTB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XWR, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSSTH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XWR, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSSTW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XWR, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSSTD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XWR, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSTB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSTH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSTW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSTD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSTBU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_BU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSTHU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_HU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLSTWU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XRD, N,SM_X,MT_WU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSSTB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XWR, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSSTH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XWR, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSSTW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XWR, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSSTD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RA,N,Y,RA,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_S,M_XWR, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLXB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLXH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLXW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLXD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLXBU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_BU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLXHU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_HU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VLXWU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_WU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSXB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XWR, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSXH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XWR, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSXW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XWR, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSXD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XWR, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLXB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLXH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLXW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLXD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLXBU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_BU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLXHU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_HU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VLXWU ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XRD, N,SM_X,MT_WU,N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSXB ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XWR, N,SM_X,MT_B, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSXH ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XWR, N,SM_X,MT_H, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSXW ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XWR, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSXD ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RS,N,Y,RV,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XWR, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOSWAP_W->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_SWAP,N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOADD_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_ADD, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOXOR_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_XOR, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOAND_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_AND, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOOR_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_OR, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOMIN_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MIN, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOMAX_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MAX, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOMINU_W->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MINU,N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOMAXU_W->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MAXU,N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOSWAP_D->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_SWAP,N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOADD_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_ADD, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOXOR_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_XOR, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOAND_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_AND, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOOR_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_OR, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOMIN_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MIN, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOMAX_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MAX, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOMINU_D->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MINU,N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAMOMAXU_D->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MAXU,N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX)) + VAMOSWAP_W->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_SWAP,N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOADD_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_ADD, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOXOR_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_XOR, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOAND_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_AND, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOOR_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_OR, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOMIN_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MIN, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOMAX_W ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MAX, N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOMINU_W->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MINU,N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOMAXU_W->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MAXU,N,SM_X,MT_W, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOSWAP_D->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_SWAP,N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOADD_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_ADD, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOXOR_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_XOR, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOAND_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_AND, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOOR_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_OR, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOMIN_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MIN, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOMAX_D ->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MAX, N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOMINU_D->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MINU,N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAMOMAXU_D->(List[BitPat](Y,N,N,N,Y,RV,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,Y,VM_I,M_XA_MAXU,N,SM_X,MT_D, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX)) } object VectorArithmeticDecode extends VFDecodeTable { val table: Array[(BitPat, List[BitPat])] = Array( // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? - // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn - // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - VEIDX ->(List[BitPat](Y,N,N,N,Y,RV,N,N,RX,N,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_IDX, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VADD ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_ADD, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_ADD, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VADDU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_ADD, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_ADDU,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSUB ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_SUB, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SUB, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSLL ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_SL, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SLL, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSLT ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_SLT, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SLT, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSLTU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_SLTU,DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SLTU,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VXOR ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_XOR, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_XOR, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSRL ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_SR, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SRL, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSRA ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_SRA, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SRA, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VOR ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_OR, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_OR, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VAND ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_AND, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_AND, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VMUL ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, Y,IM_M, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VMULH ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, Y,IM_MH, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VMULHSU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, Y,IM_MHSU,N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VMULHU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, Y,IM_MHU, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VDIV ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_DIV, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VDIVU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_DIVU,N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VREM ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_REM, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VREMU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_REMU,N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VADDW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_ADD, DW32,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_ADD, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSUBW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_SUB, DW32,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SUB, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSLLW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_SL, DW32,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SLL, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSRLW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_SR, DW32,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SRL, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VSRAW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_SRA, DW32,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SRA, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VMULW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW32,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, Y,IM_M, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VDIVW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW32,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_DIV, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VDIVUW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW32,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_DIVU,N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VREMW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW32,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_REM, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VREMUW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW32,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_REMU,N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn + // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + VEIDX ->(List[BitPat](Y,N,N,N,Y,RV,N,N,RX,N,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_IDX, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VADD ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_ADD, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_ADD, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VADDU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_ADD, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_ADDU,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSUB ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_SUB, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SUB, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSLL ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_SL, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SLL, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSLT ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_SLT, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SLT, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSLTU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_SLTU,DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SLTU,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VXOR ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_XOR, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_XOR, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSRL ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_SR, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SRL, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSRA ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_SRA, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SRA, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VOR ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_OR, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_OR, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VAND ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_AND, DW64,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_AND, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VMUL ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, Y,IM_M, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VMULH ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, Y,IM_MH, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VMULHSU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, Y,IM_MHSU,N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VMULHU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, Y,IM_MHU, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VDIV ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_DIV, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VDIVU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_DIVU,N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VREM ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_REM, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VREMU ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW64,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_REMU,N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VADDW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_ADD, DW32,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_ADD, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSUBW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_SUB, DW32,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SUB, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSLLW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_SL, DW32,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SLL, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSRLW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_SR, DW32,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SRL, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VSRAW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_SRA, DW32,A1_RS1, A2_RS2, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_SRA, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VMULW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW32,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, Y,IM_M, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VDIVW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW32,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_DIV, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VDIVUW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW32,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_DIVU,N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VREMW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW32,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_REM, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VREMUW ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW32,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, Y,ID_REMU,N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VFMADD_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMADD_D), - VFMSUB_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MSUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMSUB_D), - VFNMADD_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMADD,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMADD_D), - VFNMSUB_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMSUB,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMSUB_D), - VFADD_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_ADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FADD_D), - VFSUB_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_SUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSUB_D), - VFMUL_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MUL, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMUL_D), + VFMADD_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMADD_D), + VFMSUB_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MSUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMSUB_D), + VFNMADD_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMADD,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMADD_D), + VFNMSUB_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMSUB,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMSUB_D), + VFADD_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_ADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FADD_D), + VFSUB_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_SUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSUB_D), + VFMUL_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MUL, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMUL_D), // FIXME START - VFDIV_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_DIV, N,FC_X, N,FV_X, N,N) ++ FDIV_D), - VFSQRT_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_SQRT,N,FC_X, N,FV_X, N,N) ++ FSQRT_D), + VFDIV_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_DIV, N,FC_X, N,FV_X, N,N) ++ FDIV_D), + VFSQRT_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_SQRT,N,FC_X, N,FV_X, N,N) ++ FSQRT_D), // FIXME END - VFSGNJ_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJ, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJ_D), - VFSGNJN_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJN,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJN_D), - VFSGNJX_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJX,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJX_D), - VFMIN_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MIN, N,FV_X, N,N) ++ FMIN_D), - VFMAX_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MAX, N,FV_X, N,N) ++ FMAX_D), - VFCVT_D_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CSTD, N,N) ++ FCVT_D_S), - VFCVT_D_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CHTD, N,N) ++ FCVT_D_S), - VFCLASS_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLASS,N,FV_X, N,N) ++ FCLASS_D), + VFSGNJ_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJ, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJ_D), + VFSGNJN_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJN,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJN_D), + VFSGNJX_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJX,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJX_D), + VFMIN_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MIN, N,FV_X, N,N) ++ FMIN_D), + VFMAX_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MAX, N,FV_X, N,N) ++ FMAX_D), + VFCVT_D_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CSTD, N,N) ++ FCVT_D_S), + VFCVT_D_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CHTD, N,N) ++ FCVT_D_S), + VFCLASS_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLASS,N,FV_X, N,N) ++ FCLASS_D), - // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? - // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn - // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - VFMADD_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMADD_S), - VFMSUB_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MSUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMSUB_S), - VFNMADD_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMADD,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMADD_S), - VFNMSUB_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMSUB,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMSUB_S), - VFADD_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_ADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FADD_S), - VFSUB_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_SUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSUB_S), - VFMUL_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MUL, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMUL_S), + // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? + // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn + // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + VFMADD_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMADD_S), + VFMSUB_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MSUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMSUB_S), + VFNMADD_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMADD,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMADD_S), + VFNMSUB_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMSUB,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMSUB_S), + VFADD_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_ADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FADD_S), + VFSUB_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_SUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSUB_S), + VFMUL_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MUL, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMUL_S), // FIXME START - VFDIV_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_DIV, N,FC_X, N,FV_X, N,N) ++ FDIV_S), - VFSQRT_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_SQRT,N,FC_X, N,FV_X, N,N) ++ FSQRT_S), + VFDIV_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_DIV, N,FC_X, N,FV_X, N,N) ++ FDIV_S), + VFSQRT_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_SQRT,N,FC_X, N,FV_X, N,N) ++ FSQRT_S), // FIXME END - VFSGNJ_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJ, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJ_S), - VFSGNJN_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJN,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJN_S), - VFSGNJX_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJX,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJX_S), - VFMIN_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MIN, N,FV_X, N,N) ++ FMIN_S), - VFMAX_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MAX, N,FV_X, N,N) ++ FMAX_S), - VFCVT_S_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CDTS, N,N) ++ FCVT_S_D), - VFCVT_S_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CHTS, N,N) ++ FCVT_S_S), - VFCLASS_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLASS,N,FV_X, N,N) ++ FCLASS_S), + VFSGNJ_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJ, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJ_S), + VFSGNJN_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJN,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJN_S), + VFSGNJX_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJX,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJX_S), + VFMIN_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MIN, N,FV_X, N,N) ++ FMIN_S), + VFMAX_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MAX, N,FV_X, N,N) ++ FMAX_S), + VFCVT_S_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CDTS, N,N) ++ FCVT_S_D), + VFCVT_S_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CHTS, N,N) ++ FCVT_S_S), + VFCLASS_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLASS,N,FV_X, N,N) ++ FCLASS_S), - VFMADD_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMADD_S), - VFMSUB_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MSUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMSUB_S), - VFNMADD_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMADD,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMADD_S), - VFNMSUB_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMSUB,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMSUB_S), - VFADD_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_ADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FADD_S), - VFSUB_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_SUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSUB_S), - VFMUL_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MUL, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMUL_S), + VFMADD_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMADD_S), + VFMSUB_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MSUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMSUB_S), + VFNMADD_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMADD,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMADD_S), + VFNMSUB_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,RX,Y,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_NMSUB,N,FD_X, N,FC_X, N,FV_X, N,N) ++ FNMSUB_S), + VFADD_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_ADD, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FADD_S), + VFSUB_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_SUB, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSUB_S), + VFMUL_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, Y,FM_MUL, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FMUL_S), // FIXME START - VFDIV_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_DIV, N,FC_X, N,FV_X, N,N) ++ FDIV_S), - VFSQRT_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_SQRT,N,FC_X, N,FV_X, N,N) ++ FSQRT_S), + VFDIV_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_DIV, N,FC_X, N,FV_X, N,N) ++ FDIV_S), + VFSQRT_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, Y,FD_SQRT,N,FC_X, N,FV_X, N,N) ++ FSQRT_S), // FIXME END - VFSGNJ_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJ, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJ_S), - VFSGNJN_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJN,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJN_S), - VFSGNJX_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJX,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJX_S), - VFMIN_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MIN, N,FV_X, N,N) ++ FMIN_S), - VFMAX_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MAX, N,FV_X, N,N) ++ FMAX_S), - VFCVT_H_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CDTH, N,N) ++ FCVT_S_D), - VFCVT_H_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CSTH, N,N) ++ FCVT_S_S), - VFCLASS_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLASS,N,FV_X, N,N) ++ FCLASS_S), + VFSGNJ_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJ, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJ_S), + VFSGNJN_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJN,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJN_S), + VFSGNJX_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, Y,I_FSJX,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FSGNJX_S), + VFMIN_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MIN, N,FV_X, N,N) ++ FMIN_S), + VFMAX_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_MAX, N,FV_X, N,N) ++ FMAX_S), + VFCVT_H_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CDTH, N,N) ++ FCVT_S_D), + VFCVT_H_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CSTH, N,N) ++ FCVT_S_S), + VFCLASS_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLASS,N,FV_X, N,N) ++ FCLASS_S), - // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? - // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn - // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - VFCVT_W_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTW, N,N) ++ FCVT_W_D), - VFCVT_WU_D->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTWU,N,N) ++ FCVT_WU_D), - VFCVT_L_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTL, N,N) ++ FCVT_L_D), - VFCVT_LU_D->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTLU,N,N) ++ FCVT_LU_D), - VFCVT_D_W ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWTF, N,N) ++ FCVT_D_W), - VFCVT_D_WU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWUTF,N,N) ++ FCVT_D_WU), - VFCVT_D_L ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLTF, N,N) ++ FCVT_D_L), - VFCVT_D_LU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLUTF,N,N) ++ FCVT_D_LU), - VFCVT_W_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTW, N,N) ++ FCVT_W_S), - VFCVT_WU_S->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTWU,N,N) ++ FCVT_WU_S), - VFCVT_L_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTL, N,N) ++ FCVT_L_S), - VFCVT_LU_S->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTLU,N,N) ++ FCVT_LU_S), - VFCVT_S_W ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWTF, N,N) ++ FCVT_S_W), - VFCVT_S_WU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWUTF,N,N) ++ FCVT_S_WU), - VFCVT_S_L ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLTF, N,N) ++ FCVT_S_L), - VFCVT_S_LU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLUTF,N,N) ++ FCVT_S_LU), - VFCVT_W_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTW, N,N) ++ FCVT_W_S), - VFCVT_WU_H->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTWU,N,N) ++ FCVT_WU_S), - VFCVT_L_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTL, N,N) ++ FCVT_L_S), - VFCVT_LU_H->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTLU,N,N) ++ FCVT_LU_S), - VFCVT_H_W ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWTF, N,N) ++ FCVT_S_W), - VFCVT_H_WU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWUTF,N,N) ++ FCVT_S_WU), - VFCVT_H_L ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLTF, N,N) ++ FCVT_S_L), - VFCVT_H_LU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLUTF,N,N) ++ FCVT_S_LU), + // fence? stop? fpu? vmu? smu? viu? vipu? vimu? vidu? vfmu? vfdu? vfcu? vfvu? vrfu? + // scalar? | | dv t d 1v t d 2v t d 3v t d p imm alufn dw sel1 sel2 | fp | mode cmd | cmd mt | fn | | fn | fn | fn | fn | fn | fn vrpu?| fpfn + // val? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + VFCVT_W_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTW, N,N) ++ FCVT_W_D), + VFCVT_WU_D->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTWU,N,N) ++ FCVT_WU_D), + VFCVT_L_D ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTL, N,N) ++ FCVT_L_D), + VFCVT_LU_D->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTLU,N,N) ++ FCVT_LU_D), + VFCVT_D_W ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWTF, N,N) ++ FCVT_D_W), + VFCVT_D_WU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWUTF,N,N) ++ FCVT_D_WU), + VFCVT_D_L ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLTF, N,N) ++ FCVT_D_L), + VFCVT_D_LU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLUTF,N,N) ++ FCVT_D_LU), + VFCVT_W_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTW, N,N) ++ FCVT_W_S), + VFCVT_WU_S->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTWU,N,N) ++ FCVT_WU_S), + VFCVT_L_S ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTL, N,N) ++ FCVT_L_S), + VFCVT_LU_S->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTLU,N,N) ++ FCVT_LU_S), + VFCVT_S_W ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWTF, N,N) ++ FCVT_S_W), + VFCVT_S_WU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWUTF,N,N) ++ FCVT_S_WU), + VFCVT_S_L ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLTF, N,N) ++ FCVT_S_L), + VFCVT_S_LU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLUTF,N,N) ++ FCVT_S_LU), + VFCVT_W_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTW, N,N) ++ FCVT_W_S), + VFCVT_WU_H->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTWU,N,N) ++ FCVT_WU_S), + VFCVT_L_H ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTL, N,N) ++ FCVT_L_S), + VFCVT_LU_H->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CFTLU,N,N) ++ FCVT_LU_S), + VFCVT_H_W ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWTF, N,N) ++ FCVT_S_W), + VFCVT_H_WU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CWUTF,N,N) ++ FCVT_S_WU), + VFCVT_H_L ->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLTF, N,N) ++ FCVT_S_L), + VFCVT_H_LU->(List[BitPat](Y,N,N,N,Y,RX,Y,Y,RX,Y,N,RX,N,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, Y,FV_CLUTF,N,N) ++ FCVT_S_LU), - VCMPEQ ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_CEQ, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VCMPLT ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_CLT, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VCMPLTU ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_CLTU,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), - VCMPFEQ_D ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CEQ, N,FV_X, N,N) ++ FEQ_D), - VCMPFLT_D ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLT, N,FV_X, N,N) ++ FLT_D), - VCMPFLE_D ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLE, N,FV_X, N,N) ++ FLE_D), - VCMPFEQ_S ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CEQ, N,FV_X, N,N) ++ FEQ_S), - VCMPFLT_S ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLT, N,FV_X, N,N) ++ FLT_S), - VCMPFLE_S ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLE, N,FV_X, N,N) ++ FLE_S), - VCMPFEQ_H ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CEQ, N,FV_X, N,N) ++ FEQ_S), - VCMPFLT_H ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLT, N,FV_X, N,N) ++ FLT_S), - VCMPFLE_H ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLE, N,FV_X, N,N) ++ FLE_S), + VCMPEQ ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_CEQ, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VCMPLT ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_CLT, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VCMPLTU ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, Y,I_CLTU,N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX), + VCMPFEQ_D ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CEQ, N,FV_X, N,N) ++ FEQ_D), + VCMPFLT_D ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLT, N,FV_X, N,N) ++ FLT_D), + VCMPFLE_D ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPD,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLE, N,FV_X, N,N) ++ FLE_D), + VCMPFEQ_S ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CEQ, N,FV_X, N,N) ++ FEQ_S), + VCMPFLT_S ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLT, N,FV_X, N,N) ++ FLT_S), + VCMPFLE_S ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPS,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLE, N,FV_X, N,N) ++ FLE_S), + VCMPFEQ_H ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CEQ, N,FV_X, N,N) ++ FEQ_S), + VCMPFLT_H ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLT, N,FV_X, N,N) ++ FLT_S), + VCMPFLE_H ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RX,Y,Y,RX,Y,N,RX,N,Y,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, Y,FPH,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, N, N,IM_X, N,ID_X, N,FM_X, N,FD_X, Y,FC_CLE, N,FV_X, N,N) ++ FLE_S), - VPOP ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RP,N,Y,RP,N,Y,RP,N,N,IMM_X,FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, Y, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX)) + VPOP ->(List[BitPat](Y,N,N,N,Y,RP,N,Y,RP,N,Y,RP,N,Y,RP,N,N,IMM_X,aluFn.FN_X, DW__,A1_X, A2_X, N,FP_,N,VM_X,M_X, N,SM_X,MT_X, N,I_X, Y, N,IM_X, N,ID_X, N,FM_X, N,FD_X, N,FC_X, N,FV_X, N,N) ++ FX)) } diff --git a/src/main/scala/scalar-fpu.scala b/src/main/scala/scalar-fpu.scala index c4d54c4..04deeba 100644 --- a/src/main/scala/scalar-fpu.scala +++ b/src/main/scala/scalar-fpu.scala @@ -1,26 +1,27 @@ package hwacha -import Chisel._ +import chisel3._ +import chisel3.util._ import freechips.rocketchip.config._ import freechips.rocketchip.tile.FPConstants._ import freechips.rocketchip.tile.{FPResult, FPUCtrlSigs, HasFPUParameters} import freechips.rocketchip.util._ class ScalarFPU(implicit p: Parameters) extends HwachaModule()(p) with HasFPUParameters { - val io = new Bundle { - val req = Decoupled(new freechips.rocketchip.tile.FPInput()).flip + val io = IO(new Bundle { + val req = Flipped(Decoupled(new freechips.rocketchip.tile.FPInput())) val resp = Decoupled(new FPResult()) - } + }) //buffer for simple back-pressure model - val resp_reg = Reg(Bits()) - val resp_reg_val = Reg(init=Bool(false)) + val resp_reg = Reg(UInt()) + val resp_reg_val = RegInit(false.B) io.req.ready := !resp_reg_val val ex_ctrl = Wire(new FPUCtrlSigs) ex_ctrl <> io.req.bits val wb_ctrl = RegEnable(ex_ctrl, io.req.valid) - val wb_reg_valid = Reg(next=io.req.valid, init=Bool(false)) + val wb_reg_valid = RegNext(io.req.valid, init=false.B) val req = new freechips.rocketchip.tile.FPInput req := io.req.bits @@ -68,18 +69,18 @@ class ScalarFPU(implicit p: Parameters) extends HwachaModule()(p) with HasFPUPar ) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) - pipes.map(p => Mux(p.cond(c), UInt(1 << p.lat-offset), UInt(0))).reduce(_|_) + pipes.map(p => Mux(p.cond(c), (1.U << (1 << p.lat-offset)), 0.U)).reduce(_|_) } - def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), UInt(p._2), UInt(0))).reduce(_|_) + def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) val maxLatency = pipes.map(_.lat).max val wbLatencyMask = latencyMask(wb_ctrl, 2) class WBInfo extends Bundle { val single = Bool() - val pipeid = UInt(width = log2Ceil(pipes.size)) + val pipeid = UInt(log2Ceil(pipes.size).W) } - val wen = Reg(init=Bits(0, maxLatency-1)) + val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val wb_wen = wb_reg_valid && (wb_ctrl.fma || wb_ctrl.fastpipe || wb_ctrl.fromint) val write_port_busy = RegEnable(wb_wen && (wbLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, io.req.valid) @@ -88,9 +89,9 @@ class ScalarFPU(implicit p: Parameters) extends HwachaModule()(p) with HasFPUPar for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } - wen := wen >> UInt(1) + wen := wen >> 1.U when (wb_wen) { - wen := wen >> UInt(1) | wbLatencyMask + wen := wen >> 1.U | wbLatencyMask for (i <- 0 until maxLatency-1) { when (!write_port_busy && wbLatencyMask(i)) { wbInfo(i).single := wb_ctrl.typeTagOut === S @@ -104,15 +105,15 @@ class ScalarFPU(implicit p: Parameters) extends HwachaModule()(p) with HasFPUPar val wexc = (pipes.map(_.res.exc): Seq[UInt])(wsrc) val resp_data = Mux(!fpiu.io.out.valid, wdata, fpiu.io.out.bits.toint) io.resp.bits.data := resp_data - when (wen(0) || fpiu.io.out.valid ) { + when (wen(0) || fpiu.io.out.valid ) { when(!io.resp.ready){ resp_reg := resp_data - resp_reg_val := Bool(true) + resp_reg_val := true.B } } when(io.resp.ready && resp_reg_val){ io.resp.bits.data := resp_reg - resp_reg_val := Bool(false) + resp_reg_val := false.B } io.resp.valid := wen(0) || fpiu.io.out.valid || resp_reg_val } diff --git a/src/main/scala/scalar-unit.scala b/src/main/scala/scalar-unit.scala index ff1b01c..fccfb51 100644 --- a/src/main/scala/scalar-unit.scala +++ b/src/main/scala/scalar-unit.scala @@ -3,7 +3,6 @@ package hwacha import Chisel._ import freechips.rocketchip.config._ import freechips.rocketchip.rocket._ -import freechips.rocketchip.rocket.ALU._ import ScalarFPUDecode._ import HardFloatHelper._ @@ -20,7 +19,7 @@ class ScalarUnit(resetSignal: Bool = null)(implicit p: Parameters) extends Hwach val cfg = new HwachaConfigIO().flip val cmdq = new CMDQIO().flip - val imem = new FrontendIO(p(HwachaIcacheKey)) + val imem = new hwacha.FrontendIO(p(HwachaIcacheKey)) val vxu = Decoupled(new IssueOpML) val vmu = Decoupled(new VMUOpML) val fpu = new Bundle { @@ -163,7 +162,7 @@ class ScalarUnit(resetSignal: Bool = null)(implicit p: Parameters) extends Hwach val pending_cbranch = Reg(init=Bool(false)) val ex_reg_valid = Reg(Bool()) - val ex_reg_ctrl = Reg(new IntCtrlSigs) + val ex_reg_ctrl = Reg(new hwacha.IntCtrlSigs) val ex_reg_pc = Reg(UInt()) val ex_reg_inst = Reg(Bits()) val ex_reg_bypass = Reg(Vec(3, Bool())) @@ -171,7 +170,7 @@ class ScalarUnit(resetSignal: Bool = null)(implicit p: Parameters) extends Hwach val ex_reg_ars = Reg(Vec(2, Bits())) val wb_reg_valid = Reg(Bool()) - val wb_reg_ctrl = Reg(new IntCtrlSigs) + val wb_reg_ctrl = Reg(new hwacha.IntCtrlSigs) val wb_reg_pc = Reg(UInt()) val wb_reg_inst = Reg(Bits()) val wb_reg_wdata = Reg(Bits()) @@ -201,7 +200,7 @@ class ScalarUnit(resetSignal: Bool = null)(implicit p: Parameters) extends Hwach val id_pc = io.imem.resp.bits.pc val id_inst = io.imem.resp.bits.data; require(io.imem.resp.bits.data.getWidth == HwachaElementInstBytes*8) val decode_table = ScalarDecode.table ++ VectorMemoryDecode.table ++ VectorArithmeticDecode.table - val id_ctrl = Wire(new IntCtrlSigs()).decode(id_inst, decode_table) + val id_ctrl = Wire(new hwacha.IntCtrlSigs()).decode(id_inst, decode_table) when (!killd && id_ctrl.decode_stop) { vf_active := Bool(false) } @@ -467,14 +466,14 @@ class ScalarUnit(resetSignal: Bool = null)(implicit p: Parameters) extends Hwach Mux(id_ctrl.alu_dw === DW32, RocketConstants.DW_32, RocketConstants.DW_64) muldiv.io.req.bits.fn := Mux(id_mul_inst, - Mux(id_ctrl.vimu_fn === IM_M, FN_MUL, - Mux(id_ctrl.vimu_fn === IM_MH, FN_MULH, - Mux(id_ctrl.vimu_fn === IM_MHU, FN_MULHU, - FN_MULHSU))), - Mux(id_ctrl.vidu_fn === ID_DIV, FN_DIV, - Mux(id_ctrl.vidu_fn === ID_DIVU, FN_DIVU, - Mux(id_ctrl.vidu_fn === ID_REM, FN_REM, - FN_REMU)))) + Mux(id_ctrl.vimu_fn === IM_M, aluFn.FN_MUL, + Mux(id_ctrl.vimu_fn === IM_MH, aluFn.FN_MULH, + Mux(id_ctrl.vimu_fn === IM_MHU, aluFn.FN_MULHU, + aluFn.FN_MULHSU))), + Mux(id_ctrl.vidu_fn === ID_DIV, aluFn.FN_DIV, + Mux(id_ctrl.vidu_fn === ID_DIVU, aluFn.FN_DIVU, + Mux(id_ctrl.vidu_fn === ID_REM, aluFn.FN_REM, + aluFn.FN_REMU)))) muldiv.io.req.bits.in1 := id_sreads(0) muldiv.io.req.bits.in2 := id_sreads(1) muldiv.io.req.bits.tag := id_ctrl.vd diff --git a/src/main/scala/sequencer-lane.scala b/src/main/scala/sequencer-lane.scala index 4a01b6c..5f3bf24 100644 --- a/src/main/scala/sequencer-lane.scala +++ b/src/main/scala/sequencer-lane.scala @@ -146,7 +146,7 @@ class LaneSequencer(implicit p: Parameters) extends VXUModule()(p) val wpred_mat_vd = wpred_mat(reg_vd, pregid_vd) def wport_lookup(row: Vec[Bool], level: UInt) = - Vec((row zipWithIndex) map { case (r, i) => r && UInt(i) > level }) + Vec((row.zipWithIndex) map { case (r, i) => r && UInt(i) > level }) val raw = (0 until nSeq).map { r => @@ -210,7 +210,7 @@ class LaneSequencer(implicit p: Parameters) extends VXUModule()(p) val shazard = new { def use_mask_lop[T <: LaneOp](lops: Vec[ValidIO[T]], fn: ValidIO[T]=>Bool) = { val mask = - (lops zipWithIndex) map { case (lop, i) => + (lops.zipWithIndex) map { case (lop, i) => dgate(fn(lop), Wire(UInt(width = lops.size+nBanks-1), init = strip_to_bmask(lop.bits.strip) << UInt(i))) } reduce(_|_) mask >> UInt(1) // shift right by one because we are looking one cycle in the future @@ -382,7 +382,7 @@ class LaneSequencer(implicit p: Parameters) extends VXUModule()(p) val first = ff((i: Int) => afn(me(i).active)) val strip = stripfn(first) - val valids = Vec((first zipWithIndex) map { case (f, i) => f && nohazards(i) }) + val valids = Vec((first.zipWithIndex) map { case (f, i) => f && nohazards(i) }) val ready = la.available def fires(n: Int) = valids(n) && ready val fire = valids.reduce(_ || _) && ready @@ -402,7 +402,7 @@ class LaneSequencer(implicit p: Parameters) extends VXUModule()(p) val fn = mread(first, (me: MasterSeqEntry) => me.fn) val mcmd = DecodedMemCommand(fn.vmu().cmd) - val valids = Vec((first zipWithIndex) map { case (f, i) => f && nohazards(i) }) + val valids = Vec((first.zipWithIndex) map { case (f, i) => f && nohazards(i) }) val readys = Vec((0 until nSeq) map { case i => io.vmu.pala.available && (!mcmd.read || io.mocheck(i).load && io.lreq.available) && @@ -429,7 +429,7 @@ class LaneSequencer(implicit p: Parameters) extends VXUModule()(p) val first = ff((i: Int) => me(i).active.vlu) val strip = stripfn(first) - val valids = Vec((first zipWithIndex) map { case (f, i) => f && nohazards(i) }) + val valids = Vec((first.zipWithIndex) map { case (f, i) => f && nohazards(i) }) val ready = io.lla.available def fires(n: Int) = valids(n) && ready val fire = valids.reduce(_ || _) && ready @@ -489,7 +489,7 @@ class LaneSequencer(implicit p: Parameters) extends VXUModule()(p) } def debug = { - (io.debug.consider zipWithIndex) foreach { case (io, i) => io := consider(i) } + (io.debug.consider.zipWithIndex) foreach { case (io, i) => io := consider(i) } (io.debug.first_sched zip first_sched) foreach { case (io, c) => io := c } (io.debug.second_sched zip second_sched) foreach { case (io, c) => io := c } } @@ -533,7 +533,7 @@ class LaneSequencer(implicit p: Parameters) extends VXUModule()(p) out } - val valids = Vec((first zipWithIndex) map { case (f, i) => f && nohazards(i) }) + val valids = Vec((first.zipWithIndex) map { case (f, i) => f && nohazards(i) }) val ready = io.pla.available && (!sel || exp.fire_vgu) def fires(n: Int) = valids(n) && ready val fire = valids.reduce(_ || _) && ready @@ -594,7 +594,7 @@ class LaneSequencer(implicit p: Parameters) extends VXUModule()(p) def logic = { io.dpla.cnt := cnt io.dpla.reserve := exp.fire_vqu - (io.dqla zipWithIndex) map { case (la, i) => + (io.dqla.zipWithIndex) map { case (la, i) => la.cnt := cnt la.reserve := exp.fire_vqu_latch(i) } diff --git a/src/main/scala/vfu-idiv.scala b/src/main/scala/vfu-idiv.scala index f8fc2bc..6d972a8 100644 --- a/src/main/scala/vfu-idiv.scala +++ b/src/main/scala/vfu-idiv.scala @@ -46,10 +46,10 @@ class IDivSlice(implicit p: Parameters) extends VXUModule()(p) { Mux(io.req.bits.fn.dw_is(DW32), RocketConstants.DW_32, RocketConstants.DW_64) div.io.req.bits.fn := - Mux(io.req.bits.fn.op_is(ID_DIV), ALU.FN_DIV, - Mux(io.req.bits.fn.op_is(ID_DIVU), ALU.FN_DIVU, - Mux(io.req.bits.fn.op_is(ID_REM), ALU.FN_REM, - ALU.FN_REMU))) + Mux(io.req.bits.fn.op_is(ID_DIV), aluFn.FN_DIV, + Mux(io.req.bits.fn.op_is(ID_DIVU), aluFn.FN_DIVU, + Mux(io.req.bits.fn.op_is(ID_REM), aluFn.FN_REM, + aluFn.FN_REMU))) div.io.req.bits.in1 := io.req.bits.in0 div.io.req.bits.in2 := io.req.bits.in1 div.io.kill := Bool(false) diff --git a/src/main/scala/vfu-rfirst.scala b/src/main/scala/vfu-rfirst.scala index 83230cf..ea0721d 100644 --- a/src/main/scala/vfu-rfirst.scala +++ b/src/main/scala/vfu-rfirst.scala @@ -70,7 +70,7 @@ class RFirstMaster(implicit p: Parameters) extends VXUModule()(p) { } io.result.valid := fire(io.result.ready) - (io.lane zipWithIndex) map { case (lane, i) => + (io.lane.zipWithIndex) map { case (lane, i) => lane.ready := fire(mask_lane_valid(i), deq_lane(i)) } opq.io.deq.ready := Bool(false) diff --git a/src/main/scala/vfu-rpred.scala b/src/main/scala/vfu-rpred.scala index 593e12c..9e5882d 100644 --- a/src/main/scala/vfu-rpred.scala +++ b/src/main/scala/vfu-rpred.scala @@ -63,7 +63,7 @@ class RPredMaster(implicit p: Parameters) extends VXUModule()(p) { } io.result.valid := fire(io.result.ready) - (io.lane zipWithIndex) map { case (lane, i) => + (io.lane.zipWithIndex) map { case (lane, i) => lane.ready := fire(mask_lane_valid(i), deq_lane(i)) } opq.io.deq.ready := Bool(false)