From 49e5940bbcba24d0bca03c957077bfe56337ae09 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Sat, 22 Apr 2023 14:22:24 -0700 Subject: [PATCH 1/4] FIX: change bootrom --- .../resources/testchipip/bootrom/bootrom.S | 2 +- .../testchipip/bootrom/bootrom.rv32.dump | 63 ++++++++++++++++++ .../testchipip/bootrom/bootrom.rv32.img | Bin 192 -> 192 bytes .../testchipip/bootrom/bootrom.rv64.dump | 63 ++++++++++++++++++ .../testchipip/bootrom/bootrom.rv64.img | Bin 192 -> 192 bytes .../resources/testchipip/bootrom/linker.ld | 4 +- 6 files changed, 129 insertions(+), 3 deletions(-) create mode 100644 src/main/resources/testchipip/bootrom/bootrom.rv32.dump create mode 100644 src/main/resources/testchipip/bootrom/bootrom.rv64.dump diff --git a/src/main/resources/testchipip/bootrom/bootrom.S b/src/main/resources/testchipip/bootrom/bootrom.S index 79f41d7f..6ef463ec 100644 --- a/src/main/resources/testchipip/bootrom/bootrom.S +++ b/src/main/resources/testchipip/bootrom/bootrom.S @@ -1,4 +1,4 @@ -#define BOOTADDR_REG 0x4000 +#define BOOTADDR_REG 0x1000 // boot all cores (only hart 0) and jump to main program execution .section .text.start, "ax", @progbits diff --git a/src/main/resources/testchipip/bootrom/bootrom.rv32.dump b/src/main/resources/testchipip/bootrom/bootrom.rv32.dump new file mode 100644 index 00000000..0eed869c --- /dev/null +++ b/src/main/resources/testchipip/bootrom/bootrom.rv32.dump @@ -0,0 +1,63 @@ + +bootrom.rv32.elf: file format elf32-littleriscv + + +Disassembly of section .text.hang: + +00010000 <_hang>: + 10000: 00000517 auipc a0,0x0 + 10004: 04050513 addi a0,a0,64 # 10040 <_start> + 10008: 30551073 csrw mtvec,a0 + 1000c: 301022f3 csrr t0,misa + 10010: 4122d293 srai t0,t0,0x12 + 10014: 0012f293 andi t0,t0,1 + 10018: 00028463 beqz t0,10020 <_hang+0x20> + 1001c: 30301073 csrw mideleg,zero + 10020: 00800513 li a0,8 + 10024: 30451073 csrw mie,a0 + 10028: 30052073 csrs mstatus,a0 + +0001002c : + 1002c: 10500073 wfi + 10030: ffdff06f j 1002c + +Disassembly of section .text.start: + +00010040 <_start>: + 10040: 020005b7 lui a1,0x2000 + 10044: f1402573 csrr a0,mhartid + 10048: 00050463 beqz a0,10050 <_start+0x10> + 1004c: 0380006f j 10084 + 10050: 00458613 addi a2,a1,4 # 2000004 <_dtb+0x1feff44> + 10054: 00100693 li a3,1 + +00010058 : + 10058: 00d62023 sw a3,0(a2) + 1005c: 00460613 addi a2,a2,4 + 10060: ffc62683 lw a3,-4(a2) + 10064: fe069ae3 bnez a3,10058 + 10068: 02c0006f j 10094 + +Disassembly of section .text.hang80: + +00010080 <_hang80>: + 10080: f81ff06f j 10000 + +00010084 : + 10084: 0005a283 lw t0,0(a1) + 10088: fe029ee3 bnez t0,10084 + 1008c: 00251513 slli a0,a0,0x2 + 10090: 00b505b3 add a1,a0,a1 + +00010094 : + 10094: 0005a023 sw zero,0(a1) + 10098: 00001537 lui a0,0x1 + 1009c: 00052503 lw a0,0(a0) # 1000 + 100a0: 34151073 csrw mepc,a0 + 100a4: f1402573 csrr a0,mhartid + 100a8: 00000597 auipc a1,0x0 + 100ac: 01858593 addi a1,a1,24 # 100c0 <_dtb> + 100b0: 08000613 li a2,128 + 100b4: 30063073 csrc mstatus,a2 + 100b8: 30200073 mret + 100bc: 00000013 nop diff --git a/src/main/resources/testchipip/bootrom/bootrom.rv32.img b/src/main/resources/testchipip/bootrom/bootrom.rv32.img index fbab5033ab69b24d54a0175d735a0f2cf21f5364..2a38b04f6adf6a78b0b90c224c23f30028fd2f53 100755 GIT binary patch delta 87 zcmX@Wcz}^ZoRxt=n3a`fqKAdRc2)+aVpWHa$t5GYz$a{I4c8#Fe~eyi5wPE`5)x}G%sRh bcs!5kpRlMZ!)Dg449W{w8O&WL&Qb#a@Lv-z diff --git a/src/main/resources/testchipip/bootrom/bootrom.rv64.dump b/src/main/resources/testchipip/bootrom/bootrom.rv64.dump new file mode 100644 index 00000000..8110fc41 --- /dev/null +++ b/src/main/resources/testchipip/bootrom/bootrom.rv64.dump @@ -0,0 +1,63 @@ + +bootrom.rv64.elf: file format elf64-littleriscv + + +Disassembly of section .text.hang: + +0000000000010000 <_hang>: + 10000: 00000517 auipc a0,0x0 + 10004: 04050513 addi a0,a0,64 # 10040 <_start> + 10008: 30551073 csrw mtvec,a0 + 1000c: 301022f3 csrr t0,misa + 10010: 4122d293 srai t0,t0,0x12 + 10014: 0012f293 andi t0,t0,1 + 10018: 00028463 beqz t0,10020 <_hang+0x20> + 1001c: 30301073 csrw mideleg,zero + 10020: 00800513 li a0,8 + 10024: 30451073 csrw mie,a0 + 10028: 30052073 csrs mstatus,a0 + +000000000001002c : + 1002c: 10500073 wfi + 10030: ffdff06f j 1002c + +Disassembly of section .text.start: + +0000000000010040 <_start>: + 10040: 020005b7 lui a1,0x2000 + 10044: f1402573 csrr a0,mhartid + 10048: 00050463 beqz a0,10050 <_start+0x10> + 1004c: 0380006f j 10084 + 10050: 00458613 addi a2,a1,4 # 2000004 <_dtb+0x1feff44> + 10054: 00100693 li a3,1 + +0000000000010058 : + 10058: 00d62023 sw a3,0(a2) + 1005c: 00460613 addi a2,a2,4 + 10060: ffc62683 lw a3,-4(a2) + 10064: fe069ae3 bnez a3,10058 + 10068: 02c0006f j 10094 + +Disassembly of section .text.hang80: + +0000000000010080 <_hang80>: + 10080: f81ff06f j 10000 + +0000000000010084 : + 10084: 0005a283 lw t0,0(a1) + 10088: fe029ee3 bnez t0,10084 + 1008c: 00251513 slli a0,a0,0x2 + 10090: 00b505b3 add a1,a0,a1 + +0000000000010094 : + 10094: 0005a023 sw zero,0(a1) + 10098: 00001537 lui a0,0x1 + 1009c: 00053503 ld a0,0(a0) # 1000 + 100a0: 34151073 csrw mepc,a0 + 100a4: f1402573 csrr a0,mhartid + 100a8: 00000597 auipc a1,0x0 + 100ac: 01858593 addi a1,a1,24 # 100c0 <_dtb> + 100b0: 08000613 li a2,128 + 100b4: 30063073 csrc mstatus,a2 + 100b8: 30200073 mret + 100bc: 00000013 nop diff --git a/src/main/resources/testchipip/bootrom/bootrom.rv64.img b/src/main/resources/testchipip/bootrom/bootrom.rv64.img index 8d4fea0554d5c5f953b25cfe015ae3c9bd3b1189..326a7c6dc8ef967128b01587f3ab15e379456a7d 100755 GIT binary patch delta 87 zcmX@Wcz}^ZoRxt=n3a`fqKAdRc2)+aVpWHa$t5GYz$a{I4c8#Fe~eyi5wPE`5)x}G%sRh bcs!5kpRlMZ!)Dg449W{w8O&WL&Qb#a@Lv-z diff --git a/src/main/resources/testchipip/bootrom/linker.ld b/src/main/resources/testchipip/bootrom/linker.ld index 83d3b3fc..dec6a5b2 100644 --- a/src/main/resources/testchipip/bootrom/linker.ld +++ b/src/main/resources/testchipip/bootrom/linker.ld @@ -3,9 +3,9 @@ SECTIONS ROM_BASE = 0x10000; /* ... but actually position independent */ . = ROM_BASE; - .text.start : { *(.text.start) } - . = ROM_BASE + 0x40; .text.hang : { *(.text.hang) } + . = ROM_BASE + 0x40; + .text.start : { *(.text.start) } . = ROM_BASE + 0x80; .text.hang80 : { *(.text.hang80) } } From 476fd8e732457c0ac19e75c04e93ed5ed275824a Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 16 Jun 2023 23:26:09 -0700 Subject: [PATCH 2/4] FIX: fix bootaddrreg location --- src/main/scala/BootAddrReg.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/BootAddrReg.scala b/src/main/scala/BootAddrReg.scala index 20e9a02d..8e16338e 100644 --- a/src/main/scala/BootAddrReg.scala +++ b/src/main/scala/BootAddrReg.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.prci._ case class BootAddrRegParams( defaultBootAddress: BigInt = 0x80000000L, // This should be DRAM_BASE - bootRegAddress: BigInt = 0x4000, + bootRegAddress: BigInt = 0x1000, slaveWhere: TLBusWrapperLocation = PBUS ) case object BootAddrRegKey extends Field[Option[BootAddrRegParams]](None) From 307fca3c3ec4484d071744df6752bbbb77be7ddb Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 26 Sep 2023 10:50:26 -0700 Subject: [PATCH 3/4] FIX: change PC reset vector in cosim --- src/main/resources/testchipip/csrc/cospike_impl.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/main/resources/testchipip/csrc/cospike_impl.cc b/src/main/resources/testchipip/csrc/cospike_impl.cc index 21247471..9de26e1f 100644 --- a/src/main/resources/testchipip/csrc/cospike_impl.cc +++ b/src/main/resources/testchipip/csrc/cospike_impl.cc @@ -37,6 +37,9 @@ extern std::map backing_mem_data; #define PLIC_BASE (0xc000000) #define PLIC_SIZE (0x4000000) +// address of the PC register after reset +#define RESET_VECTOR (0x10000) + #define COSPIKE_PRINTF(...) { \ printf(__VA_ARGS__); \ fprintf(stderr, __VA_ARGS__); \ @@ -251,7 +254,7 @@ int cospike_cosim(long long int cycle, sim->configure_log(true, true); for (int i = 0; i < info->nharts; i++) { // Use our own reset vector - sim->get_core(hartid)->get_state()->pc = 0x10040; + sim->get_core(hartid)->get_state()->pc = RESET_VECTOR; // Set MMU to support up to sv39, as our normal hw configs do sim->get_core(hartid)->set_impl(IMPL_MMU_SV48, false); sim->get_core(hartid)->set_impl(IMPL_MMU_SV57, false); From e3fa307268e0ed97d0389edd2c45ac0dd4993e72 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 1 Nov 2023 11:44:42 -0700 Subject: [PATCH 4/4] FIX: make BOOT_ADDR_BASE a macro definition --- src/main/resources/testchipip/csrc/cospike_impl.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/resources/testchipip/csrc/cospike_impl.cc b/src/main/resources/testchipip/csrc/cospike_impl.cc index 9de26e1f..95fe4a3b 100644 --- a/src/main/resources/testchipip/csrc/cospike_impl.cc +++ b/src/main/resources/testchipip/csrc/cospike_impl.cc @@ -30,6 +30,7 @@ extern std::map backing_mem_data; #endif #endif +#define BOOT_ADDR_BASE (0x1000) #define CLINT_BASE (0x2000000) #define CLINT_SIZE (0x10000) #define UART_BASE (0x54000000) @@ -182,7 +183,7 @@ int cospike_cosim(long long int cycle, info->bootrom.resize(default_boot_rom_size); std::shared_ptr boot_rom = std::make_shared(info->bootrom); - std::shared_ptr boot_addr_reg = std::make_shared(0x1000); + std::shared_ptr boot_addr_reg = std::make_shared(BOOT_ADDR_BASE); uint64_t default_boot_addr = 0x80000000; boot_addr_reg.get()->store(0, 8, (const uint8_t*)(&default_boot_addr)); @@ -195,7 +196,7 @@ int cospike_cosim(long long int cycle, read_override_devices.push_back(plic); // The device map is hardcoded here for now - devices.push_back(std::pair(0x4000, boot_addr_reg)); + devices.push_back(std::pair(BOOT_ADDR_BASE, boot_addr_reg)); devices.push_back(std::pair(default_boot_rom_addr, boot_rom)); devices.push_back(std::pair(CLINT_BASE, clint)); devices.push_back(std::pair(UART_BASE, uart));