diff --git a/src/main/scala/soc/ChipIdPin.scala b/src/main/scala/soc/ChipIdPin.scala
new file mode 100644
index 00000000..6a2dfe64
--- /dev/null
+++ b/src/main/scala/soc/ChipIdPin.scala
@@ -0,0 +1,43 @@
+package testchipip.soc
+
+import chisel3._
+import chisel3.util._
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.subsystem._
+
+case class ChipIdPinParams (
+  width: Int = 1, 
+  chipIdAddr: BigInt = 0x2000,
+  slaveWhere: TLBusWrapperLocation = CBUS
+)
+
+case object ChipIdPinKey extends Field[Option[ChipIdPinParams]](None)
+
+trait CanHavePeripheryChipIdPin { this: BaseSubsystem =>
+  val chip_id_pin = p(ChipIdPinKey).map { params => 
+    val tlbus = locateTLBusWrapper(params.slaveWhere)
+    val device = new SimpleDevice("chip-id-reg", Nil)
+
+    val inner_io = tlbus {
+      val node = TLRegisterNode(
+        address = Seq(AddressSet(params.chipIdAddr, 4096 - 1)),
+        device = device, 
+        beatBytes=tlbus.beatBytes)
+      tlbus.coupleTo(s"chip-id-reg"){ node := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := _ }
+      InModuleBody {
+        val chip_id = IO(Input(UInt(params.width.W))).suggestName("chip_id") 
+        node.regmap(0 -> Seq(RegField.r(64, chip_id)))
+        chip_id
+      }
+    }
+    val outer_io = InModuleBody {
+      val chip_id = IO(Input(UInt(params.width.W))).suggestName("chip_id")
+      inner_io := chip_id
+      chip_id
+    }
+    outer_io
+  }
+}
\ No newline at end of file
diff --git a/src/main/scala/soc/Configs.scala b/src/main/scala/soc/Configs.scala
index 57dc1e01..26f15556 100644
--- a/src/main/scala/soc/Configs.scala
+++ b/src/main/scala/soc/Configs.scala
@@ -67,6 +67,19 @@ class WithOffchipBusClient(
       OffchipBusTopologyConnectionParams(location, blockRange, replicationBase)
 })
 
+//-------------------------
+// ChipIdPin Configs
+//-------------------------
+
+class WithChipIdPin(params: ChipIdPinParams = ChipIdPinParams()) extends Config((site, here, up) => {
+  case ChipIdPinKey => Some(params)
+})
+
+// Used for setting pin width
+class WithChipIdPinWidth(width: Int) extends Config((site, here, up) => {
+  case ChipIdPinKey => up(ChipIdPinKey, site).map(p => p.copy(width = width))
+})
+
 // Deprecated: use Constellation's network-on-chip generators instead of this
 class WithRingSystemBus(
     buffer: TLNetworkBufferParams = TLNetworkBufferParams.default)