Skip to content

Commit 00caf1c

Browse files
committed
Fix(cpu): Add riscv64 to chunked_prefill exclusion list
Signed-off-by: lyd1992 <liuyudong@iscas.ac.cn> Signed-off-by: ihb2032 <1355790728@qq.com>
1 parent e23cacd commit 00caf1c

File tree

1 file changed

+4
-3
lines changed

1 file changed

+4
-3
lines changed

vllm/engine/arg_utils.py

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1162,9 +1162,10 @@ def create_engine_config(
11621162
self._set_default_args(usage_context, model_config)
11631163
# Disable chunked prefill for POWER (ppc64le)/ARM/s390x CPUs in V1
11641164
if current_platform.is_cpu() and current_platform.get_cpu_architecture(
1165-
) in (CpuArchEnum.POWERPC, CpuArchEnum.S390X, CpuArchEnum.ARM):
1166-
logger.info("Chunked prefill is not supported for ARM and POWER "
1167-
"and S390X CPUs; "
1165+
) in (CpuArchEnum.POWERPC, CpuArchEnum.S390X, CpuArchEnum.ARM,
1166+
CpuArchEnum.RISCV):
1167+
logger.info("Chunked prefill is not supported for ARM and POWER, "
1168+
"S390X and RISC-V CPUs; "
11681169
"disabling it for V1 backend.")
11691170
self.enable_chunked_prefill = False
11701171
assert self.enable_chunked_prefill is not None

0 commit comments

Comments
 (0)