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@bigPYJ1151 bigPYJ1151 commented Aug 3, 2025

Essential Elements of an Effective PR Description Checklist

  • The purpose of the PR, such as "Fix some issue (link existing issues this PR will resolve)".
  • The test plan, such as providing test command.
  • The test results, such as pasting the results comparison before and after, or e2e results
  • (Optional) The necessary documentation update, such as updating supported_models.md and examples for a new model.

Purpose

  • Some hidden states dimension of Qwen2.5 is uneven for CPU custom silu_and_mul, fallback it to torch native implementation. For torch.compile, there will be no difference. For eager mode, the performance drop will be very slight.

Test Plan

Test Result

(Optional) Documentation Update

Signed-off-by: jiang1.li <jiang1.li@intel.com>
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@mergify mergify bot added the qwen Related to Qwen models label Aug 3, 2025
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Code Review

This pull request addresses a crash in the SiluAndMul activation on CPU when used with hidden dimensions that are not a multiple of the CPU vector size. The fix involves falling back to the native PyTorch implementation for the CPU platform, which correctly handles arbitrary dimensions. The change is correct and effectively resolves the reported issue for SiluAndMul. I've identified that several other activation functions in the same file suffer from the identical problem on CPU and have left a comment with a recommendation to apply a similar fix to those as well for consistency and to prevent future crashes.

Comment on lines +68 to +74
if current_platform.is_cuda_alike():
self.op = torch.ops._C.silu_and_mul
elif current_platform.is_xpu():
from vllm._ipex_ops import ipex_ops
self.op = ipex_ops.silu_and_mul
elif current_platform.is_cpu():
self._forward_method = self.forward_native
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high

While this change correctly fixes the crash for SiluAndMul on CPU with uneven dimensions, it is an incomplete fix for the file. Other activation functions in this file, such as GeluAndMul, NewGELU, FastGELU, and QuickGELU, still use custom CPU kernels with the same dimension constraints and will crash under similar conditions.

For example, GeluAndMul at line 207 has if current_platform.is_cuda_alike() or current_platform.is_cpu(): which will lead to the same crash.

To ensure consistent behavior and prevent future bugs, it's highly recommended to apply the same fix to these other activations within this PR. This will improve code quality and maintainability.

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CPU tests pass

@vllm-bot vllm-bot merged commit b5dfb94 into vllm-project:main Aug 3, 2025
15 of 17 checks passed
npanpaliya pushed a commit to odh-on-pz/vllm-upstream that referenced this pull request Aug 6, 2025
…mul to torch native implementation (vllm-project#22145)

Signed-off-by: jiang1.li <jiang1.li@intel.com>
jinzhen-lin pushed a commit to jinzhen-lin/vllm that referenced this pull request Aug 9, 2025
…mul to torch native implementation (vllm-project#22145)

Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Jinzhen Lin <linjinzhen@hotmail.com>
noamgat pushed a commit to noamgat/vllm that referenced this pull request Aug 9, 2025
…mul to torch native implementation (vllm-project#22145)

Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Noam Gat <noamgat@gmail.com>
paulpak58 pushed a commit to paulpak58/vllm that referenced this pull request Aug 13, 2025
…mul to torch native implementation (vllm-project#22145)

Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Paul Pak <paulpak58@gmail.com>
diegocastanibm pushed a commit to diegocastanibm/vllm that referenced this pull request Aug 15, 2025
…mul to torch native implementation (vllm-project#22145)

Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Diego-Castan <diego.castan@ibm.com>
epwalsh pushed a commit to epwalsh/vllm that referenced this pull request Aug 28, 2025
…mul to torch native implementation (vllm-project#22145)

Signed-off-by: jiang1.li <jiang1.li@intel.com>
zhewenl pushed a commit to zhewenl/vllm that referenced this pull request Aug 28, 2025
…mul to torch native implementation (vllm-project#22145)

Signed-off-by: jiang1.li <jiang1.li@intel.com>
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3 participants