From b9b41a666c3538f0844cdf399648b3d121a29c9c Mon Sep 17 00:00:00 2001 From: Sasha Lopoukhine Date: Tue, 6 Feb 2024 10:03:43 +0000 Subject: [PATCH 1/6] dialects: (builtin) --- tests/test_attribute_definition.py | 6 +-- tests/test_op_builder.py | 10 ++-- xdsl/dialects/builtin.py | 86 +++++++++++++++++------------- xdsl/utils/comparisons.py | 11 ++-- 4 files changed, 65 insertions(+), 48 deletions(-) diff --git a/tests/test_attribute_definition.py b/tests/test_attribute_definition.py index 4119d4721a..76dfcceaa9 100644 --- a/tests/test_attribute_definition.py +++ b/tests/test_attribute_definition.py @@ -226,13 +226,13 @@ def test_unsigned_integer_attr(): def test_signless_integer_attr(): """Test the verification of a signless integer attribute.""" with pytest.raises(VerifyException): - IntegerAttr((1 << 32) + 1, IntegerType(32, Signedness.SIGNLESS)) + IntegerAttr((1 << 32), IntegerType(32, Signedness.SIGNLESS)) with pytest.raises(VerifyException): IntegerAttr(-(1 << 32) - 1, IntegerType(32, Signedness.SIGNLESS)) - IntegerAttr(1 << 32, IntegerType(32, Signedness.SIGNLESS)) - IntegerAttr(-(1 << 32), IntegerType(32, Signedness.SIGNLESS)) + IntegerAttr(1 << 32 - 1, IntegerType(32, Signedness.SIGNLESS)) + IntegerAttr(-(1 << 31), IntegerType(32, Signedness.SIGNLESS)) ################################################################################ diff --git a/tests/test_op_builder.py b/tests/test_op_builder.py index 796b9c77e3..f4788671bc 100644 --- a/tests/test_op_builder.py +++ b/tests/test_op_builder.py @@ -10,8 +10,8 @@ def test_insertion_point_constructors(): target = Block( [ - (op1 := Constant.from_int_and_width(1, 1)), - (op2 := Constant.from_int_and_width(2, 1)), + (op1 := Constant.from_int_and_width(0, 1)), + (op2 := Constant.from_int_and_width(1, 1)), ] ) @@ -37,16 +37,16 @@ def test_insertion_point_constructors(): def test_builder(): target = Block( [ + Constant.from_int_and_width(0, 1), Constant.from_int_and_width(1, 1), - Constant.from_int_and_width(2, 1), ] ) block = Block() b = Builder.at_end(block) - x = Constant.from_int_and_width(1, 1) - y = Constant.from_int_and_width(2, 1) + x = Constant.from_int_and_width(0, 1) + y = Constant.from_int_and_width(1, 1) b.insert(x) b.insert(y) diff --git a/xdsl/dialects/builtin.py b/xdsl/dialects/builtin.py index ab501e8700..11a8c1d74a 100644 --- a/xdsl/dialects/builtin.py +++ b/xdsl/dialects/builtin.py @@ -16,7 +16,7 @@ overload, ) -from typing_extensions import Self, assert_never +from typing_extensions import Self from xdsl.ir import ( Attribute, @@ -304,6 +304,27 @@ class Signedness(Enum): SIGNED = 1 UNSIGNED = 2 + def value_range(self, bitwidth: int) -> tuple[int, int]: + """ + For a given bitwidth, returns (min, max+1), where min and max are the smallest and + largest representable values. + + Signless integers are bit patterns, so the representable range is the union of the + signed and unsigned representable ranges. + """ + match self: + case Signedness.SIGNLESS: + min_value = -(1 << (bitwidth - 1)) + max_value = 1 << bitwidth + case Signedness.SIGNED: + min_value = -(1 << (bitwidth - 1)) + max_value = 1 << (bitwidth - 1) + case Signedness.UNSIGNED: + min_value = 0 + max_value = 1 << bitwidth + + return min_value, max_value + @irdl_attr_definition class SignednessAttr(Data[Signedness]): @@ -350,6 +371,9 @@ def __init__( signedness = SignednessAttr(signedness) super().__init__([data, signedness]) + def value_range(self) -> tuple[int, int]: + return self.signedness.data.value_range(self.width.data) + i64 = IntegerType(64) i32 = IntegerType(32) @@ -432,36 +456,17 @@ def from_int_and_width(value: int, width: int) -> IntegerAttr[IntegerType]: def from_index_int_value(value: int) -> IntegerAttr[IndexType]: return IntegerAttr(value, IndexType()) - @staticmethod - def _get_value_range(int_type: IntegerType) -> tuple[int, int]: - signedness = int_type.signedness.data - width = int_type.width.data - - if signedness == Signedness.SIGNLESS: - min_value = -(1 << width) - max_value = 1 << width - elif signedness == Signedness.SIGNED: - min_value = -(1 << (width - 1)) - max_value = (1 << (width - 1)) - 1 - elif signedness == Signedness.UNSIGNED: - min_value = 0 - max_value = (1 << width) - 1 - else: - assert_never(signedness) - - return min_value, max_value - def verify(self) -> None: if isinstance(int_type := self.type, IndexType): return - min_value, max_value = self._get_value_range(int_type) + min_value, max_value = int_type.value_range() - if not (min_value <= self.value.data <= max_value): + if not (min_value <= self.value.data < max_value): raise VerifyException( f"Integer value {self.value.data} is out of range for " f"type {self.type} which supports values in the " - f"range [{min_value}, {max_value}]" + f"range [{min_value}, {max_value})" ) @@ -967,9 +972,11 @@ def create_dense_float( @staticmethod def from_list( type: RankedVectorOrTensorOf[AnyFloat | IntegerType | IndexType], - data: Sequence[int] - | Sequence[IntegerAttr[IndexType]] - | Sequence[IntegerAttr[IntegerType]], + data: ( + Sequence[int] + | Sequence[IntegerAttr[IndexType]] + | Sequence[IntegerAttr[IntegerType]] + ), ) -> DenseIntOrFPElementsAttr: ... @@ -1013,11 +1020,13 @@ def vector_from_list( @staticmethod def tensor_from_list( - data: Sequence[int] - | Sequence[float] - | Sequence[IntegerAttr[IndexType]] - | Sequence[IntegerAttr[IntegerType]] - | Sequence[AnyFloatAttr], + data: ( + Sequence[int] + | Sequence[float] + | Sequence[IntegerAttr[IndexType]] + | Sequence[IntegerAttr[IntegerType]] + | Sequence[AnyFloatAttr] + ), data_type: IntegerType | IndexType | AnyFloat, shape: Sequence[int], ) -> DenseIntOrFPElementsAttr: @@ -1103,10 +1112,12 @@ def from_list( @staticmethod def from_list( data_type: Attribute, - data: Sequence[int] - | Sequence[int | float] - | Sequence[IntAttr] - | Sequence[FloatData], + data: ( + Sequence[int] + | Sequence[int | float] + | Sequence[IntAttr] + | Sequence[FloatData] + ), ) -> DenseArrayBase: if isinstance(data_type, IndexType | IntegerType): _data = cast(Sequence[int] | Sequence[IntAttr], data) @@ -1180,8 +1191,9 @@ class StridedLayoutAttr(ParametrizedAttribute): def __init__( self, - strides: ArrayAttr[IntAttr | NoneAttr] - | Sequence[int | None | IntAttr | NoneAttr], + strides: ( + ArrayAttr[IntAttr | NoneAttr] | Sequence[int | None | IntAttr | NoneAttr] + ), offset: int | None | IntAttr | NoneAttr = 0, ) -> None: if not isinstance(strides, ArrayAttr): diff --git a/xdsl/utils/comparisons.py b/xdsl/utils/comparisons.py index a1ebf7ba6b..45d99b8000 100644 --- a/xdsl/utils/comparisons.py +++ b/xdsl/utils/comparisons.py @@ -32,26 +32,31 @@ their bit representations are the same. """ +from xdsl.dialects.builtin import Signedness + def unsigned_upper_bound(bitwidth: int) -> int: """ The maximum representable value + 1. """ - return 1 << bitwidth + _, ub = Signedness.UNSIGNED.value_range(bitwidth) + return ub def signed_lower_bound(bitwidth: int) -> int: """ The minimum representable value. """ - return -(1 << (bitwidth - 1)) + lb, _ = Signedness.SIGNED.value_range(bitwidth) + return lb def signed_upper_bound(bitwidth: int) -> int: """ The maximum representable value + 1. """ - return 1 << (bitwidth - 1) + _, ub = Signedness.SIGNED.value_range(bitwidth) + return ub def to_unsigned(signless: int, bitwidth: int) -> int: From 405043f7dcee5b8f3aaafd138beb353326f78655 Mon Sep 17 00:00:00 2001 From: Sasha Lopoukhine Date: Tue, 6 Feb 2024 08:55:53 +0000 Subject: [PATCH 2/6] dialects: (riscv) Li value has 20 bits --- xdsl/dialects/riscv.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/xdsl/dialects/riscv.py b/xdsl/dialects/riscv.py index e8b031fd2a..b54e6db0e5 100644 --- a/xdsl/dialects/riscv.py +++ b/xdsl/dialects/riscv.py @@ -648,7 +648,7 @@ class RdImmIntegerOperation(IRDLOperation, RISCVInstruction, ABC): """ rd: OpResult = result_def(IntRegisterType) - immediate: AnyIntegerAttr | LabelAttr = attr_def(AnyIntegerAttr | LabelAttr) + immediate: SImm20Attr | LabelAttr = attr_def(SImm20Attr | LabelAttr) def __init__( self, @@ -658,7 +658,7 @@ def __init__( comment: str | StringAttr | None = None, ): if isinstance(immediate, int): - immediate = IntegerAttr(immediate, IntegerType(20, Signedness.UNSIGNED)) + immediate = IntegerAttr(immediate, si20) elif isinstance(immediate, str): immediate = LabelAttr(immediate) if rd is None: @@ -682,9 +682,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]: @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["immediate"] = _parse_immediate_value( - parser, IntegerType(20, Signedness.UNSIGNED) - ) + attributes["immediate"] = _parse_immediate_value(parser, si20) return attributes def custom_print_attributes(self, printer: Printer) -> Set[str]: From e362b917ee03858968f2a17f22d12baa224789d2 Mon Sep 17 00:00:00 2001 From: Sasha Lopoukhine Date: Tue, 6 Feb 2024 09:45:22 +0000 Subject: [PATCH 3/6] fix bitwidth in riscv --- tests/dialects/test_riscv.py | 29 ++++++++--- tests/filecheck/dialects/riscv/riscv_ops.mlir | 10 ++-- .../filecheck/dialects/snitch_stream/ops.mlir | 2 +- xdsl/dialects/riscv.py | 49 ++++++++++++++----- .../canonicalization_patterns/riscv.py | 5 +- 5 files changed, 71 insertions(+), 24 deletions(-) diff --git a/tests/dialects/test_riscv.py b/tests/dialects/test_riscv.py index 7628eca482..8642f8b200 100644 --- a/tests/dialects/test_riscv.py +++ b/tests/dialects/test_riscv.py @@ -4,6 +4,11 @@ from xdsl.dialects.builtin import IntegerAttr, ModuleOp, i32 from xdsl.ir import MLContext from xdsl.parser import Parser +from xdsl.utils.comparisons import ( + signed_lower_bound, + signed_upper_bound, + unsigned_upper_bound, +) from xdsl.utils.exceptions import ParseError, VerifyException from xdsl.utils.test_value import TestSSAValue @@ -150,13 +155,19 @@ def test_immediate_s_inst(): def test_immediate_u_j_inst(): # U-Type and J-Type - 20-bits immediate + ub = signed_upper_bound(20) + lb = signed_lower_bound(20) + assert ub == 524288 + assert lb == -524288 + with pytest.raises(VerifyException): - riscv.LuiOp(1 << 20) + riscv.LuiOp(ub) with pytest.raises(VerifyException): - riscv.LuiOp(-(1 << 20) - 2) + riscv.LuiOp(lb - 1) - riscv.LuiOp((1 << 20) - 1) + riscv.LuiOp(ub - 1) + riscv.LuiOp(lb) def test_immediate_jalr_inst(): @@ -173,14 +184,20 @@ def test_immediate_jalr_inst(): def test_immediate_pseudo_inst(): + ub = unsigned_upper_bound(32) + lb = signed_lower_bound(32) + assert ub == 4294967296 + assert lb == -2147483648 + # Pseudo-Instruction with custom handling with pytest.raises(VerifyException): - riscv.LiOp(-(1 << 31) - 1, rd=riscv.Registers.A0) + riscv.LiOp(ub, rd=riscv.Registers.A0) with pytest.raises(VerifyException): - riscv.LiOp(1 << 32, rd=riscv.Registers.A0) + riscv.LiOp(lb - 1, rd=riscv.Registers.A0) - riscv.LiOp((1 << 31) - 1, rd=riscv.Registers.A0) + riscv.LiOp(ub - 1, rd=riscv.Registers.A0) + riscv.LiOp(lb, rd=riscv.Registers.A0) def test_immediate_shift_inst(): diff --git a/tests/filecheck/dialects/riscv/riscv_ops.mlir b/tests/filecheck/dialects/riscv/riscv_ops.mlir index c5febadd49..193a4a93b3 100644 --- a/tests/filecheck/dialects/riscv/riscv_ops.mlir +++ b/tests/filecheck/dialects/riscv/riscv_ops.mlir @@ -359,8 +359,8 @@ // CHECK-GENERIC-NEXT: %slli = "riscv.slli"(%0) {"immediate" = 1 : ui5} : (!riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %srli = "riscv.srli"(%0) {"immediate" = 1 : ui5} : (!riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %srai = "riscv.srai"(%0) {"immediate" = 1 : ui5} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %lui = "riscv.lui"() {"immediate" = 1 : ui20} : () -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %auipc = "riscv.auipc"() {"immediate" = 1 : ui20} : () -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %lui = "riscv.lui"() {"immediate" = 1 : i20} : () -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %auipc = "riscv.auipc"() {"immediate" = 1 : i20} : () -> !riscv.reg<> // CHECK-GENERIC-NEXT: %mv = "riscv.mv"(%0) : (!riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %add = "riscv.add"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %slt = "riscv.slt"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<> @@ -418,16 +418,16 @@ // CHECK-GENERIC-NEXT: %divu = "riscv.divu"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %rem = "riscv.rem"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %remu = "riscv.remu"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %li = "riscv.li"() {"immediate" = 1 : si32} : () -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %li = "riscv.li"() {"immediate" = 1 : i32} : () -> !riscv.reg<> // CHECK-GENERIC-NEXT: "riscv.ecall"() : () -> () // CHECK-GENERIC-NEXT: "riscv.ebreak"() : () -> () // CHECK-GENERIC-NEXT: "riscv.directive"() {"directive" = ".bss"} : () -> () // CHECK-GENERIC-NEXT: "riscv.directive"() {"directive" = ".align", "value" = "2"} : () -> () // CHECK-GENERIC-NEXT: "riscv.assembly_section"() ({ -// CHECK-GENERIC-NEXT: %nested_li = "riscv.li"() {"immediate" = 1 : si32} : () -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %nested_li = "riscv.li"() {"immediate" = 1 : i32} : () -> !riscv.reg<> // CHECK-GENERIC-NEXT: }) {"directive" = ".text", "foo" = i32} : () -> () // CHECK-GENERIC-NEXT: "riscv.assembly_section"() ({ -// CHECK-GENERIC-NEXT: %nested_li_1 = "riscv.li"() {"immediate" = 1 : si32} : () -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %nested_li_1 = "riscv.li"() {"immediate" = 1 : i32} : () -> !riscv.reg<> // CHECK-GENERIC-NEXT: }) {"directive" = ".text"} : () -> () // CHECK-GENERIC-NEXT: %custom0, %custom1 = "riscv.custom_assembly_instruction"(%0, %1) {"instruction_name" = "hello"} : (!riscv.reg<>, !riscv.reg<>) -> (!riscv.reg<>, !riscv.reg<>) // CHECK-GENERIC-NEXT: %f0 = "riscv.get_float_register"() : () -> !riscv.freg<> diff --git a/tests/filecheck/dialects/snitch_stream/ops.mlir b/tests/filecheck/dialects/snitch_stream/ops.mlir index 0083959e0a..fb10d55607 100644 --- a/tests/filecheck/dialects/snitch_stream/ops.mlir +++ b/tests/filecheck/dialects/snitch_stream/ops.mlir @@ -44,7 +44,7 @@ // CHECK-GENERIC-NEXT: %Z_str = "snitch_stream.strided_write"(%Z, %pattern) {"dm" = #builtin.int<2>, "rank" = #builtin.int<2>} : (!riscv.reg<>, !snitch_stream.stride_pattern_type<2>) -> !stream.writable> // CHECK-GENERIC-NEXT: "snitch_stream.streaming_region"(%X, %Y, %Z, %pattern) <{"operandSegmentSizes" = array}> ({ // CHECK-GENERIC-NEXT: ^0(%a_stream : !stream.readable>, %b_stream : !stream.readable>, %c_stream : !stream.writable>): -// CHECK-GENERIC-NEXT: %c5 = "riscv.li"() {"immediate" = 5 : si32} : () -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %c5 = "riscv.li"() {"immediate" = 5 : i32} : () -> !riscv.reg<> // CHECK-GENERIC-NEXT: "riscv_snitch.frep_outer"(%c5) ({ // CHECK-GENERIC-NEXT: %a = "riscv_snitch.read"(%a_stream) : (!stream.readable>) -> !riscv.freg // CHECK-GENERIC-NEXT: %b = "riscv_snitch.read"(%b_stream) : (!stream.readable>) -> !riscv.freg diff --git a/xdsl/dialects/riscv.py b/xdsl/dialects/riscv.py index b54e6db0e5..0b6015990c 100644 --- a/xdsl/dialects/riscv.py +++ b/xdsl/dialects/riscv.py @@ -16,6 +16,7 @@ Signedness, StringAttr, UnitAttr, + i32, ) from xdsl.dialects.llvm import FastMathAttr as LLVMFastMathAttr from xdsl.ir import ( @@ -332,9 +333,12 @@ class Registers(ABC): ui5 = IntegerType(5, Signedness.UNSIGNED) si12 = IntegerType(12, Signedness.SIGNED) si20 = IntegerType(20, Signedness.SIGNED) +i20 = IntegerType(20, Signedness.SIGNLESS) UImm5Attr = IntegerAttr[Annotated[IntegerType, ui5]] SImm12Attr = IntegerAttr[Annotated[IntegerType, si12]] SImm20Attr = IntegerAttr[Annotated[IntegerType, si20]] +Imm20Attr = IntegerAttr[Annotated[IntegerType, i20]] +Imm32Attr = IntegerAttr[Annotated[IntegerType, i32]] @irdl_attr_definition @@ -648,7 +652,7 @@ class RdImmIntegerOperation(IRDLOperation, RISCVInstruction, ABC): """ rd: OpResult = result_def(IntRegisterType) - immediate: SImm20Attr | LabelAttr = attr_def(SImm20Attr | LabelAttr) + immediate: Imm20Attr | LabelAttr = attr_def(Imm20Attr | LabelAttr) def __init__( self, @@ -658,7 +662,7 @@ def __init__( comment: str | StringAttr | None = None, ): if isinstance(immediate, int): - immediate = IntegerAttr(immediate, si20) + immediate = IntegerAttr(immediate, i20) elif isinstance(immediate, str): immediate = LabelAttr(immediate) if rd is None: @@ -682,7 +686,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]: @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["immediate"] = _parse_immediate_value(parser, si20) + attributes["immediate"] = _parse_immediate_value(parser, i20) return attributes def custom_print_attributes(self, printer: Printer) -> Set[str]: @@ -2432,9 +2436,9 @@ def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]: @irdl_op_definition -class LiOp(RdImmIntegerOperation): +class LiOp(IRDLOperation, RISCVInstruction, ABC): """ - Loads an immediate into rd. + Loads a 32-bit immediate into rd. This is an assembler pseudo-instruction. @@ -2443,28 +2447,51 @@ class LiOp(RdImmIntegerOperation): name = "riscv.li" + rd: OpResult = result_def(IntRegisterType) + immediate: Imm32Attr | LabelAttr = attr_def(Imm32Attr | LabelAttr) + traits = frozenset((Pure(), ConstantLike(), LiOpHasCanonicalizationPatternTrait())) def __init__( self, - immediate: int | AnyIntegerAttr | str | LabelAttr, + immediate: int | Imm32Attr | str | LabelAttr, *, rd: IntRegisterType | str | None = None, comment: str | StringAttr | None = None, ): if isinstance(immediate, int): - immediate = IntegerAttr(immediate, IntegerType(32, Signedness.SIGNED)) + immediate = IntegerAttr(immediate, i32) + elif isinstance(immediate, str): + immediate = LabelAttr(immediate) + if rd is None: + rd = IntRegisterType.unallocated() + elif isinstance(rd, str): + rd = IntRegisterType(rd) + if isinstance(comment, str): + comment = StringAttr(comment) - super().__init__(immediate, rd=rd, comment=comment) + super().__init__( + result_types=[rd], + attributes={ + "immediate": immediate, + "comment": comment, + }, + ) + + def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]: + return self.rd, self.immediate @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["immediate"] = _parse_immediate_value( - parser, IntegerType(32, Signedness.SIGNED) - ) + attributes["immediate"] = _parse_immediate_value(parser, i32) return attributes + def custom_print_attributes(self, printer: Printer) -> Set[str]: + printer.print(" ") + _print_immediate_value(printer, self.immediate) + return {"immediate"} + @irdl_op_definition class EcallOp(NullaryOperation): diff --git a/xdsl/transforms/canonicalization_patterns/riscv.py b/xdsl/transforms/canonicalization_patterns/riscv.py index 82d267c1b4..56bfee5f95 100644 --- a/xdsl/transforms/canonicalization_patterns/riscv.py +++ b/xdsl/transforms/canonicalization_patterns/riscv.py @@ -221,10 +221,13 @@ def match_and_rewrite(self, op: riscv.SubOp, rewriter: PatternRewriter) -> None: if ( isinstance(op.rs1, OpResult) and isinstance(op.rs1.op, riscv.AddiOp) + and isinstance(op.rs1.op.immediate, IntegerAttr) and op.rs2 == op.rs1.op.rs1 ): rd = cast(riscv.IntRegisterType, op.rd.type) - rewriter.replace_matched_op(riscv.LiOp(op.rs1.op.immediate, rd=rd)) + rewriter.replace_matched_op( + riscv.LiOp(op.rs1.op.immediate.value.data, rd=rd) + ) class ShiftLeftImmediate(RewritePattern): From 6cbf8ac456a42853fbdd23d75ccc335e05ef645f Mon Sep 17 00:00:00 2001 From: Sasha Lopoukhine Date: Tue, 6 Feb 2024 10:10:43 +0000 Subject: [PATCH 4/6] dialects: (riscv) fix signedness in riscv --- tests/dialects/test_riscv.py | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/tests/dialects/test_riscv.py b/tests/dialects/test_riscv.py index 8642f8b200..1afbf51292 100644 --- a/tests/dialects/test_riscv.py +++ b/tests/dialects/test_riscv.py @@ -1,14 +1,9 @@ import pytest from xdsl.dialects import riscv -from xdsl.dialects.builtin import IntegerAttr, ModuleOp, i32 +from xdsl.dialects.builtin import IntegerAttr, ModuleOp, Signedness, i32 from xdsl.ir import MLContext from xdsl.parser import Parser -from xdsl.utils.comparisons import ( - signed_lower_bound, - signed_upper_bound, - unsigned_upper_bound, -) from xdsl.utils.exceptions import ParseError, VerifyException from xdsl.utils.test_value import TestSSAValue @@ -155,9 +150,8 @@ def test_immediate_s_inst(): def test_immediate_u_j_inst(): # U-Type and J-Type - 20-bits immediate - ub = signed_upper_bound(20) - lb = signed_lower_bound(20) - assert ub == 524288 + lb, ub = Signedness.SIGNLESS.value_range(20) + assert ub == 1048576 assert lb == -524288 with pytest.raises(VerifyException): @@ -184,8 +178,7 @@ def test_immediate_jalr_inst(): def test_immediate_pseudo_inst(): - ub = unsigned_upper_bound(32) - lb = signed_lower_bound(32) + lb, ub = Signedness.SIGNLESS.value_range(32) assert ub == 4294967296 assert lb == -2147483648 From b627a0cd91e9cf38296b303ed30dc515c92fbcfc Mon Sep 17 00:00:00 2001 From: Sasha Lopoukhine Date: Tue, 6 Feb 2024 10:26:12 +0000 Subject: [PATCH 5/6] i12 --- xdsl/dialects/riscv.py | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/xdsl/dialects/riscv.py b/xdsl/dialects/riscv.py index 0b6015990c..3ecb6bfd7c 100644 --- a/xdsl/dialects/riscv.py +++ b/xdsl/dialects/riscv.py @@ -331,12 +331,12 @@ class Registers(ABC): ui5 = IntegerType(5, Signedness.UNSIGNED) -si12 = IntegerType(12, Signedness.SIGNED) si20 = IntegerType(20, Signedness.SIGNED) +i12 = IntegerType(12, Signedness.SIGNLESS) i20 = IntegerType(20, Signedness.SIGNLESS) UImm5Attr = IntegerAttr[Annotated[IntegerType, ui5]] -SImm12Attr = IntegerAttr[Annotated[IntegerType, si12]] SImm20Attr = IntegerAttr[Annotated[IntegerType, si20]] +Imm12Attr = IntegerAttr[Annotated[IntegerType, i12]] Imm20Attr = IntegerAttr[Annotated[IntegerType, i20]] Imm32Attr = IntegerAttr[Annotated[IntegerType, i32]] @@ -780,13 +780,13 @@ class RdRsImmIntegerOperation(IRDLOperation, RISCVInstruction, ABC): def __init__( self, rs1: Operation | SSAValue, - immediate: int | SImm12Attr | str | LabelAttr, + immediate: int | Imm12Attr | str | LabelAttr, *, rd: IntRegisterType | str | None = None, comment: str | StringAttr | None = None, ): if isinstance(immediate, int): - immediate = IntegerAttr(immediate, si12) + immediate = IntegerAttr(immediate, i12) elif isinstance(immediate, str): immediate = LabelAttr(immediate) @@ -877,18 +877,18 @@ class RdRsImmJumpOperation(IRDLOperation, RISCVInstruction, ABC): The rd register here is not a register storing the result, rather the register where the program counter is stored before jumping. """ - immediate = attr_def(SImm12Attr | LabelAttr) + immediate = attr_def(Imm12Attr | LabelAttr) def __init__( self, rs1: Operation | SSAValue, - immediate: int | SImm12Attr | str | LabelAttr, + immediate: int | Imm12Attr | str | LabelAttr, *, rd: IntRegisterType | str | None = None, comment: str | StringAttr | None = None, ): if isinstance(immediate, int): - immediate = IntegerAttr(immediate, si12) + immediate = IntegerAttr(immediate, i12) elif isinstance(immediate, str): immediate = LabelAttr(immediate) @@ -967,18 +967,18 @@ class RsRsOffIntegerOperation(IRDLOperation, RISCVInstruction, ABC): rs1: Operand = operand_def(IntRegisterType) rs2: Operand = operand_def(IntRegisterType) - offset = attr_def(SImm12Attr | LabelAttr) + offset = attr_def(Imm12Attr | LabelAttr) def __init__( self, rs1: Operation | SSAValue, rs2: Operation | SSAValue, - offset: int | SImm12Attr | LabelAttr, + offset: int | Imm12Attr | LabelAttr, *, comment: str | StringAttr | None = None, ): if isinstance(offset, int): - offset = IntegerAttr(offset, si12) + offset = IntegerAttr(offset, i12) if isinstance(offset, str): offset = LabelAttr(offset) if isinstance(comment, str): @@ -998,7 +998,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]: @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["offset"] = _parse_immediate_value(parser, si12) + attributes["offset"] = _parse_immediate_value(parser, i12) return attributes def custom_print_attributes(self, printer: Printer) -> Set[str]: @@ -1017,18 +1017,18 @@ class RsRsImmIntegerOperation(IRDLOperation, RISCVInstruction, ABC): rs1 = operand_def(IntRegisterType) rs2 = operand_def(IntRegisterType) - immediate = attr_def(SImm12Attr) + immediate = attr_def(Imm12Attr) def __init__( self, rs1: Operation | SSAValue, rs2: Operation | SSAValue, - immediate: int | SImm12Attr | str | LabelAttr, + immediate: int | Imm12Attr | str | LabelAttr, *, comment: str | StringAttr | None = None, ): if isinstance(immediate, int): - immediate = IntegerAttr(immediate, si12) + immediate = IntegerAttr(immediate, i12) elif isinstance(immediate, str): immediate = LabelAttr(immediate) if isinstance(comment, str): @@ -2944,18 +2944,18 @@ class RsRsImmFloatOperation(IRDLOperation, RISCVInstruction, ABC): rs1 = operand_def(IntRegisterType) rs2 = operand_def(FloatRegisterType) - immediate = attr_def(SImm12Attr) + immediate = attr_def(Imm12Attr) def __init__( self, rs1: Operation | SSAValue, rs2: Operation | SSAValue, - immediate: int | SImm12Attr | str | LabelAttr, + immediate: int | Imm12Attr | str | LabelAttr, *, comment: str | StringAttr | None = None, ): if isinstance(immediate, int): - immediate = IntegerAttr(immediate, si12) + immediate = IntegerAttr(immediate, i12) elif isinstance(immediate, str): immediate = LabelAttr(immediate) if isinstance(comment, str): @@ -2995,18 +2995,18 @@ class RdRsImmFloatOperation(IRDLOperation, RISCVInstruction, ABC): rd = result_def(FloatRegisterType) rs1 = operand_def(IntRegisterType) - immediate = attr_def(SImm12Attr | LabelAttr) + immediate = attr_def(Imm12Attr | LabelAttr) def __init__( self, rs1: Operation | SSAValue, - immediate: int | SImm12Attr | str | LabelAttr, + immediate: int | Imm12Attr | str | LabelAttr, *, rd: FloatRegisterType | str | None = None, comment: str | StringAttr | None = None, ): if isinstance(immediate, int): - immediate = IntegerAttr(immediate, si12) + immediate = IntegerAttr(immediate, i12) elif isinstance(immediate, str): immediate = LabelAttr(immediate) From 5942103c2ba75b87789f7653e52448027df242d1 Mon Sep 17 00:00:00 2001 From: Sasha Lopoukhine Date: Tue, 6 Feb 2024 10:59:23 +0000 Subject: [PATCH 6/6] fix tests --- tests/dialects/test_riscv.py | 18 ++++---- tests/filecheck/dialects/riscv/riscv_ops.mlir | 36 +++++++-------- .../filecheck/dialects/riscv_snitch/ops.mlir | 2 +- xdsl/dialects/riscv.py | 46 +++++++------------ 4 files changed, 46 insertions(+), 56 deletions(-) diff --git a/tests/dialects/test_riscv.py b/tests/dialects/test_riscv.py index 1afbf51292..01066456cc 100644 --- a/tests/dialects/test_riscv.py +++ b/tests/dialects/test_riscv.py @@ -121,31 +121,33 @@ def test_return_op(): def test_immediate_i_inst(): # I-Type - 12-bits immediate + lb, ub = Signedness.SIGNLESS.value_range(12) a1 = TestSSAValue(riscv.Registers.A1) with pytest.raises(VerifyException): - riscv.AddiOp(a1, 1 << 11, rd=riscv.Registers.A0) + riscv.AddiOp(a1, ub, rd=riscv.Registers.A0) with pytest.raises(VerifyException): - riscv.AddiOp(a1, -(1 << 11) - 2, rd=riscv.Registers.A0) + riscv.AddiOp(a1, lb - 1, rd=riscv.Registers.A0) - riscv.AddiOp(a1, -(1 << 11), rd=riscv.Registers.A0) - riscv.AddiOp(a1, (1 << 11) - 1, rd=riscv.Registers.A0) + riscv.AddiOp(a1, ub - 1, rd=riscv.Registers.A0) + riscv.AddiOp(a1, lb, rd=riscv.Registers.A0) def test_immediate_s_inst(): # S-Type - 12-bits immediate + lb, ub = Signedness.SIGNLESS.value_range(12) a1 = TestSSAValue(riscv.Registers.A1) a2 = TestSSAValue(riscv.Registers.A2) with pytest.raises(VerifyException): - riscv.SwOp(a1, a2, 1 << 11) + riscv.SwOp(a1, a2, ub) with pytest.raises(VerifyException): - riscv.SwOp(a1, a2, -(1 << 11) - 2) + riscv.SwOp(a1, a2, lb - 1) - riscv.SwOp(a1, a2, -(1 << 11)) - riscv.SwOp(a1, a2, (1 << 11) - 1) + riscv.SwOp(a1, a2, ub - 1) + riscv.SwOp(a1, a2, lb) def test_immediate_u_j_inst(): diff --git a/tests/filecheck/dialects/riscv/riscv_ops.mlir b/tests/filecheck/dialects/riscv/riscv_ops.mlir index 193a4a93b3..5626bc1b7d 100644 --- a/tests/filecheck/dialects/riscv/riscv_ops.mlir +++ b/tests/filecheck/dialects/riscv/riscv_ops.mlir @@ -350,12 +350,12 @@ // CHECK-GENERIC-NEXT: "riscv_func.func"() ({ // CHECK-GENERIC-NEXT: %0 = "riscv.get_register"() : () -> !riscv.reg<> // CHECK-GENERIC-NEXT: %1 = "riscv.get_register"() : () -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %addi = "riscv.addi"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %slti = "riscv.slti"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %sltiu = "riscv.sltiu"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %andi = "riscv.andi"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %ori = "riscv.ori"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %xori = "riscv.xori"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %addi = "riscv.addi"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %slti = "riscv.slti"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %sltiu = "riscv.sltiu"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %andi = "riscv.andi"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %ori = "riscv.ori"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %xori = "riscv.xori"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %slli = "riscv.slli"(%0) {"immediate" = 1 : ui5} : (!riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %srli = "riscv.srli"(%0) {"immediate" = 1 : ui5} : (!riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %srai = "riscv.srai"(%0) {"immediate" = 1 : ui5} : (!riscv.reg<>) -> !riscv.reg<> @@ -389,14 +389,14 @@ // CHECK-GENERIC-NEXT: "riscv.bge"(%0, %1) {"offset" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> () // CHECK-GENERIC-NEXT: "riscv.bltu"(%0, %1) {"offset" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> () // CHECK-GENERIC-NEXT: "riscv.bgeu"(%0, %1) {"offset" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> () -// CHECK-GENERIC-NEXT: %lb = "riscv.lb"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %lbu = "riscv.lbu"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %lh = "riscv.lh"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %lhu = "riscv.lhu"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: %lw = "riscv.lw"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<> -// CHECK-GENERIC-NEXT: "riscv.sb"(%0, %1) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> () -// CHECK-GENERIC-NEXT: "riscv.sh"(%0, %1) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> () -// CHECK-GENERIC-NEXT: "riscv.sw"(%0, %1) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> () +// CHECK-GENERIC-NEXT: %lb = "riscv.lb"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %lbu = "riscv.lbu"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %lh = "riscv.lh"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %lhu = "riscv.lhu"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: %lw = "riscv.lw"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<> +// CHECK-GENERIC-NEXT: "riscv.sb"(%0, %1) {"immediate" = 1 : i12} : (!riscv.reg<>, !riscv.reg<>) -> () +// CHECK-GENERIC-NEXT: "riscv.sh"(%0, %1) {"immediate" = 1 : i12} : (!riscv.reg<>, !riscv.reg<>) -> () +// CHECK-GENERIC-NEXT: "riscv.sw"(%0, %1) {"immediate" = 1 : i12} : (!riscv.reg<>, !riscv.reg<>) -> () // CHECK-GENERIC-NEXT: %csrrw_rw = "riscv.csrrw"(%0) {"csr" = 1024 : i32} : (!riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %csrrw_w = "riscv.csrrw"(%0) {"csr" = 1024 : i32, "writeonly"} : (!riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: %csrrs_rw = "riscv.csrrs"(%0) {"csr" = 1024 : i32} : (!riscv.reg<>) -> !riscv.reg<> @@ -464,10 +464,10 @@ // CHECK-GENERIC-NEXT: %fcvt_s_w = "riscv.fcvt.s.w"(%0) : (!riscv.reg<>) -> !riscv.freg<> // CHECK-GENERIC-NEXT: %fcvt_s_wu = "riscv.fcvt.s.wu"(%0) : (!riscv.reg<>) -> !riscv.freg<> // CHECK-GENERIC-NEXT: %fmv_w_x = "riscv.fmv.w.x"(%0) : (!riscv.reg<>) -> !riscv.freg<> -// CHECK-GENERIC-NEXT: %flw = "riscv.flw"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.freg<> -// CHECK-GENERIC-NEXT: "riscv.fsw"(%0, %f0) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.freg<>) -> () -// CHECK-GENERIC-NEXT: %fld = "riscv.fld"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.freg<> -// CHECK-GENERIC-NEXT: "riscv.fsd"(%0, %f0) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.freg<>) -> () +// CHECK-GENERIC-NEXT: %flw = "riscv.flw"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.freg<> +// CHECK-GENERIC-NEXT: "riscv.fsw"(%0, %f0) {"immediate" = 1 : i12} : (!riscv.reg<>, !riscv.freg<>) -> () +// CHECK-GENERIC-NEXT: %fld = "riscv.fld"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.freg<> +// CHECK-GENERIC-NEXT: "riscv.fsd"(%0, %f0) {"immediate" = 1 : i12} : (!riscv.reg<>, !riscv.freg<>) -> () // CHECK-GENERIC-NEXT: %fmv_d = "riscv.fmv.d"(%f0) : (!riscv.freg<>) -> !riscv.freg<> // CHECK-GENERIC-NEXT: %vfadd_s = "riscv.vfadd.s"(%f0, %f1) : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<> // CHECK-GENERIC-NEXT: %vfmul_s = "riscv.vfmul.s"(%f0, %f1) : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<> diff --git a/tests/filecheck/dialects/riscv_snitch/ops.mlir b/tests/filecheck/dialects/riscv_snitch/ops.mlir index e069adbaa0..7dccf16de5 100644 --- a/tests/filecheck/dialects/riscv_snitch/ops.mlir +++ b/tests/filecheck/dialects/riscv_snitch/ops.mlir @@ -61,7 +61,7 @@ riscv_func.func @main() { // CHECK-GENERIC-NEXT: %0 = "riscv.get_register"() : () -> !riscv.reg<> // CHECK-GENERIC-NEXT: %1 = "riscv.get_register"() : () -> !riscv.reg<> // CHECK-GENERIC-NEXT: %scfgw = "riscv_snitch.scfgw"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg -// CHECK-GENERIC-NEXT: %scfgwi_zero = "riscv_snitch.scfgwi"(%0) {"immediate" = 42 : si12} : (!riscv.reg<>) -> !riscv.reg +// CHECK-GENERIC-NEXT: %scfgwi_zero = "riscv_snitch.scfgwi"(%0) {"immediate" = 42 : i12} : (!riscv.reg<>) -> !riscv.reg // CHECK-GENERIC-NEXT: "riscv_snitch.frep_outer"(%{{.*}}) ({ // CHECK-GENERIC-NEXT: %{{.*}} = "riscv.add"(%{{.*}}, %{{.*}}) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<> // CHECK-GENERIC-NEXT: "riscv_snitch.frep_yield"() : () -> () diff --git a/xdsl/dialects/riscv.py b/xdsl/dialects/riscv.py index 3ecb6bfd7c..2e4f942645 100644 --- a/xdsl/dialects/riscv.py +++ b/xdsl/dialects/riscv.py @@ -332,9 +332,11 @@ class Registers(ABC): ui5 = IntegerType(5, Signedness.UNSIGNED) si20 = IntegerType(20, Signedness.SIGNED) +si12 = IntegerType(12, Signedness.SIGNED) i12 = IntegerType(12, Signedness.SIGNLESS) i20 = IntegerType(20, Signedness.SIGNLESS) UImm5Attr = IntegerAttr[Annotated[IntegerType, ui5]] +SImm12Attr = IntegerAttr[Annotated[IntegerType, si12]] SImm20Attr = IntegerAttr[Annotated[IntegerType, si20]] Imm12Attr = IntegerAttr[Annotated[IntegerType, i12]] Imm20Attr = IntegerAttr[Annotated[IntegerType, i20]] @@ -739,9 +741,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]: @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["immediate"] = _parse_immediate_value( - parser, IntegerType(20, Signedness.SIGNED) - ) + attributes["immediate"] = _parse_immediate_value(parser, si20) if parser.parse_optional_punctuation(","): attributes["rd"] = parser.parse_attribute() return attributes @@ -780,7 +780,7 @@ class RdRsImmIntegerOperation(IRDLOperation, RISCVInstruction, ABC): def __init__( self, rs1: Operation | SSAValue, - immediate: int | Imm12Attr | str | LabelAttr, + immediate: int | SImm12Attr | str | LabelAttr, *, rd: IntRegisterType | str | None = None, comment: str | StringAttr | None = None, @@ -811,9 +811,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]: @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["immediate"] = _parse_immediate_value( - parser, IntegerType(12, Signedness.SIGNED) - ) + attributes["immediate"] = _parse_immediate_value(parser, i12) return attributes def custom_print_attributes(self, printer: Printer) -> Set[str]: @@ -852,9 +850,7 @@ def __init__( @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["immediate"] = _parse_immediate_value( - parser, IntegerType(5, Signedness.UNSIGNED) - ) + attributes["immediate"] = _parse_immediate_value(parser, ui5) return attributes @@ -877,18 +873,18 @@ class RdRsImmJumpOperation(IRDLOperation, RISCVInstruction, ABC): The rd register here is not a register storing the result, rather the register where the program counter is stored before jumping. """ - immediate = attr_def(Imm12Attr | LabelAttr) + immediate = attr_def(SImm12Attr | LabelAttr) def __init__( self, rs1: Operation | SSAValue, - immediate: int | Imm12Attr | str | LabelAttr, + immediate: int | SImm12Attr | str | LabelAttr, *, rd: IntRegisterType | str | None = None, comment: str | StringAttr | None = None, ): if isinstance(immediate, int): - immediate = IntegerAttr(immediate, i12) + immediate = IntegerAttr(immediate, si12) elif isinstance(immediate, str): immediate = LabelAttr(immediate) @@ -913,9 +909,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]: @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["immediate"] = _parse_immediate_value( - parser, IntegerType(12, Signedness.SIGNED) - ) + attributes["immediate"] = _parse_immediate_value(parser, si12) if parser.parse_optional_punctuation(","): attributes["rd"] = parser.parse_attribute() return attributes @@ -967,18 +961,18 @@ class RsRsOffIntegerOperation(IRDLOperation, RISCVInstruction, ABC): rs1: Operand = operand_def(IntRegisterType) rs2: Operand = operand_def(IntRegisterType) - offset = attr_def(Imm12Attr | LabelAttr) + offset = attr_def(SImm12Attr | LabelAttr) def __init__( self, rs1: Operation | SSAValue, rs2: Operation | SSAValue, - offset: int | Imm12Attr | LabelAttr, + offset: int | SImm12Attr | LabelAttr, *, comment: str | StringAttr | None = None, ): if isinstance(offset, int): - offset = IntegerAttr(offset, i12) + offset = IntegerAttr(offset, si12) if isinstance(offset, str): offset = LabelAttr(offset) if isinstance(comment, str): @@ -998,7 +992,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]: @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["offset"] = _parse_immediate_value(parser, i12) + attributes["offset"] = _parse_immediate_value(parser, si12) return attributes def custom_print_attributes(self, printer: Printer) -> Set[str]: @@ -1048,9 +1042,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]: @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["immediate"] = _parse_immediate_value( - parser, IntegerType(12, Signedness.SIGNED) - ) + attributes["immediate"] = _parse_immediate_value(parser, i12) return attributes def custom_print_attributes(self, printer: Printer) -> Set[str]: @@ -2975,9 +2967,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]: @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["immediate"] = _parse_immediate_value( - parser, IntegerType(12, Signedness.SIGNED) - ) + attributes["immediate"] = _parse_immediate_value(parser, i12) return attributes def custom_print_attributes(self, printer: Printer) -> Set[str]: @@ -3031,9 +3021,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]: @classmethod def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]: attributes = dict[str, Attribute]() - attributes["immediate"] = _parse_immediate_value( - parser, IntegerType(12, Signedness.SIGNED) - ) + attributes["immediate"] = _parse_immediate_value(parser, i12) return attributes def custom_print_attributes(self, printer: Printer) -> Set[str]: