diff --git a/tests/backend/riscv/test_register_allocation.py b/tests/backend/riscv/test_register_allocation.py
index 262e06dd1a..f28ddbd49c 100644
--- a/tests/backend/riscv/test_register_allocation.py
+++ b/tests/backend/riscv/test_register_allocation.py
@@ -23,7 +23,7 @@ def test_default_reserved_registers():
     unallocated = riscv.Registers.UNALLOCATED_INT
 
     def j(index: int):
-        return riscv.IntRegisterType(f"j{index}")
+        return riscv.IntRegisterType(f"j_{index}")
 
     assert register_queue.pop(riscv.IntRegisterType) == j(0)
 
@@ -62,7 +62,7 @@ def j(index: int):
     with pytest.raises(
         DiagnosticException,
         match=re.escape(
-            "Cannot allocate registers to the same register ['!riscv.reg<j2>', '!riscv.reg<j3>']"
+            "Cannot allocate registers to the same register ['!riscv.reg<j_2>', '!riscv.reg<j_3>']"
         ),
     ):
         register_allocator.allocate_same((d0, d1))
@@ -74,7 +74,7 @@ def j(index: int):
     with pytest.raises(
         DiagnosticException,
         match=re.escape(
-            "Cannot allocate registers to the same register ['!riscv.reg', '!riscv.reg<j2>', '!riscv.reg<j3>']"
+            "Cannot allocate registers to the same register ['!riscv.reg', '!riscv.reg<j_2>', '!riscv.reg<j_3>']"
         ),
     ):
         register_allocator.allocate_same((e0, e1, e2))
@@ -116,18 +116,18 @@ def get_register_constraints(self) -> RegisterConstraints:
     # All new registers. The result register is reused by the allocator for the operand.
     op0 = MyInstructionOp.get("", "", "", "")
     register_allocator.process_riscv_op(op0)
-    assert op0.rs0.type == riscv.IntRegisterType("j1")
-    assert op0.rs1.type == riscv.IntRegisterType("j0")
-    assert op0.rd0.type == riscv.IntRegisterType("j1")
-    assert op0.rd1.type == riscv.IntRegisterType("j0")
+    assert op0.rs0.type == riscv.IntRegisterType("j_1")
+    assert op0.rs1.type == riscv.IntRegisterType("j_0")
+    assert op0.rd0.type == riscv.IntRegisterType("j_1")
+    assert op0.rd1.type == riscv.IntRegisterType("j_0")
 
     # One register reserved for inout parameter, the allocator should allocate the output
     # to the same register.
     op1 = MyInstructionOp.get("", "", "", "a0")
     register_allocator.process_riscv_op(op1)
-    assert op1.rs0.type == riscv.IntRegisterType("j2")
+    assert op1.rs0.type == riscv.IntRegisterType("j_2")
     assert op1.rs1.type == riscv.IntRegisterType("a0")
-    assert op1.rd0.type == riscv.IntRegisterType("j2")
+    assert op1.rd0.type == riscv.IntRegisterType("j_2")
     assert op1.rd1.type == riscv.IntRegisterType("a0")
 
 
diff --git a/tests/backend/riscv/test_register_queue.py b/tests/backend/riscv/test_register_queue.py
index 569c88ca11..e919bc1be7 100644
--- a/tests/backend/riscv/test_register_queue.py
+++ b/tests/backend/riscv/test_register_queue.py
@@ -25,11 +25,13 @@ def test_default_reserved_registers():
 def test_push_j_register():
     register_queue = RiscvRegisterQueue()
 
-    register_queue.push(riscv.IntRegisterType("j0"))
-    assert riscv.IntRegisterType("j0") == register_queue.available_int_registers[-1]
+    register_queue.push(riscv.IntRegisterType("j_0"))
+    assert riscv.IntRegisterType("j_0") == register_queue.available_int_registers[-1]
 
-    register_queue.push(riscv.FloatRegisterType("j0"))
-    assert riscv.FloatRegisterType("j0") == register_queue.available_float_registers[-1]
+    register_queue.push(riscv.FloatRegisterType("j_0"))
+    assert (
+        riscv.FloatRegisterType("j_0") == register_queue.available_float_registers[-1]
+    )
 
 
 def test_push_register():
@@ -45,18 +47,18 @@ def test_push_register():
 def test_reserve_register():
     register_queue = RiscvRegisterQueue()
 
-    register_queue.reserve_register(riscv.IntRegisterType("j0"))
-    assert register_queue.reserved_int_registers[riscv.IntRegisterType("j0")] == 1
+    register_queue.reserve_register(riscv.IntRegisterType("j_0"))
+    assert register_queue.reserved_int_registers[riscv.IntRegisterType("j_0")] == 1
 
-    register_queue.reserve_register(riscv.IntRegisterType("j0"))
-    assert register_queue.reserved_int_registers[riscv.IntRegisterType("j0")] == 2
+    register_queue.reserve_register(riscv.IntRegisterType("j_0"))
+    assert register_queue.reserved_int_registers[riscv.IntRegisterType("j_0")] == 2
 
-    register_queue.unreserve_register(riscv.IntRegisterType("j0"))
-    assert register_queue.reserved_int_registers[riscv.IntRegisterType("j0")] == 1
+    register_queue.unreserve_register(riscv.IntRegisterType("j_0"))
+    assert register_queue.reserved_int_registers[riscv.IntRegisterType("j_0")] == 1
 
-    register_queue.unreserve_register(riscv.IntRegisterType("j0"))
-    assert riscv.IntRegisterType("j0") not in register_queue.reserved_int_registers
-    assert riscv.IntRegisterType("j0") not in register_queue.available_int_registers
+    register_queue.unreserve_register(riscv.IntRegisterType("j_0"))
+    assert riscv.IntRegisterType("j_0") not in register_queue.reserved_int_registers
+    assert riscv.IntRegisterType("j_0") not in register_queue.available_int_registers
 
     # Check assertion error when reserving an available register
     reg = register_queue.pop(riscv.IntRegisterType)
diff --git a/tests/dialects/test_riscv.py b/tests/dialects/test_riscv.py
index ef0244c307..075752a15a 100644
--- a/tests/dialects/test_riscv.py
+++ b/tests/dialects/test_riscv.py
@@ -35,7 +35,7 @@ def test_add_op():
     assert a2.type.index == IntAttr(12)
 
     # Registers that aren't predefined should not have an index.
-    assert isinstance(riscv.IntRegisterType("j1").index, NoneAttr)
+    assert isinstance(riscv.IntRegisterType("j_1").index, NoneAttr)
 
 
 def test_csr_op():
diff --git a/tests/filecheck/backend/riscv/canonicalize.mlir b/tests/filecheck/backend/riscv/canonicalize.mlir
index 19833f4ead..bf23790a6f 100644
--- a/tests/filecheck/backend/riscv/canonicalize.mlir
+++ b/tests/filecheck/backend/riscv/canonicalize.mlir
@@ -9,8 +9,8 @@ builtin.module {
 
   %i3 = riscv.li 100 : !riscv.reg
   %i4 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg
-  %i5 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg<j0>
-  "test.op"(%i3, %i4, %i5) : (!riscv.reg, !riscv.reg, !riscv.reg<j0>) -> ()
+  %i5 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg<j_0>
+  "test.op"(%i3, %i4, %i5) : (!riscv.reg, !riscv.reg, !riscv.reg<j_0>) -> ()
 
   %f0, %f1, %f2 = "test.op"() : () -> (!riscv.freg<fa0>, !riscv.freg<fa1>, !riscv.freg)
   %fo0 = riscv.fmv.s %f0 : (!riscv.freg<fa0>) -> !riscv.freg<fa0>
@@ -136,8 +136,8 @@ builtin.module {
 
 // CHECK-NEXT:   %i3 = riscv.li 100 : !riscv.reg
 // CHECK-NEXT:   %i4 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg
-// CHECK-NEXT:   %i5 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg<j0>
-// CHECK-NEXT:   "test.op"(%i3, %i4, %i5) : (!riscv.reg, !riscv.reg, !riscv.reg<j0>) -> ()
+// CHECK-NEXT:   %i5 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg<j_0>
+// CHECK-NEXT:   "test.op"(%i3, %i4, %i5) : (!riscv.reg, !riscv.reg, !riscv.reg<j_0>) -> ()
 
 // CHECK-NEXT:   %{{.*}}, %{{.*}}, %{{.*}} = "test.op"() : () -> (!riscv.freg<fa0>, !riscv.freg<fa1>, !riscv.freg)
 // CHECK-NEXT:   %{{.*}} = riscv.fmv.s %{{.*}} : (!riscv.freg<fa1>) -> !riscv.freg<fa2>
diff --git a/tests/filecheck/backend/riscv/register-allocation/frep.mlir b/tests/filecheck/backend/riscv/register-allocation/frep.mlir
index 0cc7fa69a0..c47db0fcf5 100644
--- a/tests/filecheck/backend/riscv/register-allocation/frep.mlir
+++ b/tests/filecheck/backend/riscv/register-allocation/frep.mlir
@@ -39,17 +39,17 @@ riscv_func.func @main() {
 
 //   CHECK-LIVENESS-BLOCK-NAIVE-J:       builtin.module {
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:    riscv_func.func @main() {
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.li 6 : !riscv.reg<j1>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.li 6 : !riscv.reg<j_1>
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.li 5 : !riscv.reg<s0>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<j1>) -> !riscv.freg<fj0>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<s0>) -> !riscv.freg<fj1>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.fadd.s %{{\d+}}, %{{\d+}} : (!riscv.freg<fj0>, !riscv.freg<fj1>) -> !riscv.freg<fj0>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.add %{{\d+}}, %{{\d+}} : (!riscv.reg<j1>, !riscv.reg<s0>) -> !riscv.reg<j0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<s0>) -> !riscv.freg<fj_1>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.fadd.s %{{\d+}}, %{{\d+}} : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv.add %{{\d+}}, %{{\d+}} : (!riscv.reg<j_1>, !riscv.reg<s0>) -> !riscv.reg<j_0>
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      riscv_snitch.frep_outer %{{\d+}} {
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      }
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv_snitch.frep_outer %{{\d+}} iter_args(%{{\d+}} = %{{\d+}}) -> (!riscv.reg<j0>) {
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:        %{{\d+}} = riscv.mv %{{\d+}} : (!riscv.reg<j0>) -> !riscv.reg<j0>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:        riscv_snitch.frep_yield %{{\d+}} : !riscv.reg<j0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %{{\d+}} = riscv_snitch.frep_outer %{{\d+}} iter_args(%{{\d+}} = %{{\d+}}) -> (!riscv.reg<j_0>) {
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:        %{{\d+}} = riscv.mv %{{\d+}} : (!riscv.reg<j_0>) -> !riscv.reg<j_0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:        riscv_snitch.frep_yield %{{\d+}} : !riscv.reg<j_0>
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      }
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      riscv_func.return
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:    }
diff --git a/tests/filecheck/backend/riscv/register-allocation/generic.mlir b/tests/filecheck/backend/riscv/register-allocation/generic.mlir
index 3780cfdf39..b5ccb500e6 100644
--- a/tests/filecheck/backend/riscv/register-allocation/generic.mlir
+++ b/tests/filecheck/backend/riscv/register-allocation/generic.mlir
@@ -52,17 +52,17 @@ riscv_func.func @main() {
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:    riscv_func.func @external() -> ()
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:    riscv_func.func @main() {
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %zero = riscv.li 0 : !riscv.reg<zero>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %0 = riscv.li 6 : !riscv.reg<j1>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %0 = riscv.li 6 : !riscv.reg<j_1>
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %1 = riscv.li 5 : !riscv.reg<s0>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %2 = riscv.fcvt.s.w %0 : (!riscv.reg<j1>) -> !riscv.freg<fj0>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %3 = riscv.fcvt.s.w %1 : (!riscv.reg<s0>) -> !riscv.freg<fj1>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %4 = riscv.fadd.s %2, %3 : (!riscv.freg<fj0>, !riscv.freg<fj1>) -> !riscv.freg<fj0>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %5 = riscv.add %0, %1 : (!riscv.reg<j1>, !riscv.reg<s0>) -> !riscv.reg<j0>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      riscv_scf.for %6 : !riscv.reg<j2> = %0 to %1 step %5 {
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %2 = riscv.fcvt.s.w %0 : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %3 = riscv.fcvt.s.w %1 : (!riscv.reg<s0>) -> !riscv.freg<fj_1>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %4 = riscv.fadd.s %2, %3 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %5 = riscv.add %0, %1 : (!riscv.reg<j_1>, !riscv.reg<s0>) -> !riscv.reg<j_0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      riscv_scf.for %6 : !riscv.reg<j_2> = %0 to %1 step %5 {
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      }
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %7 = riscv_scf.for %8 : !riscv.reg<j1> = %0 to %1 step %5 iter_args(%9 = %5) -> (!riscv.reg<j0>) {
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:        %10 = riscv.mv %9 : (!riscv.reg<j0>) -> !riscv.reg<j0>
-//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:        riscv_scf.yield %10 : !riscv.reg<j0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %7 = riscv_scf.for %8 : !riscv.reg<j_1> = %0 to %1 step %5 iter_args(%9 = %5) -> (!riscv.reg<j_0>) {
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:        %10 = riscv.mv %9 : (!riscv.reg<j_0>) -> !riscv.reg<j_0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:        riscv_scf.yield %10 : !riscv.reg<j_0>
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      }
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %zero_1 = riscv.li 0 : !riscv.reg<zero>
 //   CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT:      %zero_2 = riscv.li 0 : !riscv.reg<a0>
diff --git a/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir b/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir
index 19ae362886..dd3576a57e 100644
--- a/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir
+++ b/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir
@@ -4,59 +4,59 @@
   riscv_func.func @main() {
     %0 = riscv.li 6 : !riscv.reg<zero>
     // CHECK:      li zero, 6
-    %1 = riscv.li 5 : !riscv.reg<j1>
-    // CHECK-NEXT: li j1, 5
-    %2 = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: add j2, zero, j1
-    %mv = riscv.mv %0 : (!riscv.reg<zero>) -> !riscv.reg<j2>
-    // CHECK-NEXT: mv j2, zero
+    %1 = riscv.li 5 : !riscv.reg<j_1>
+    // CHECK-NEXT: li j_1, 5
+    %2 = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: add j_2, zero, j_1
+    %mv = riscv.mv %0 : (!riscv.reg<zero>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: mv j_2, zero
 
     // RV32I/RV64I: Integer Computational Instructions (Section 2.4)
     // Integer Register-Immediate Instructions
-    %addi = riscv.addi %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j1>
-    // CHECK-NEXT: addi j1, j1, 1
-    %slti = riscv.slti %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j1>
-    // CHECK-NEXT: slti j1, j1, 1
-    %sltiu = riscv.sltiu %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j1>
-    // CHECK-NEXT: sltiu j1, j1, 1
-    %andi = riscv.andi %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j1>
-    // CHECK-NEXT: andi j1, j1, 1
-    %ori = riscv.ori %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j1>
-    // CHECK-NEXT: ori j1, j1, 1
-    %xori = riscv.xori %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j1>
-    // CHECK-NEXT: xori j1, j1, 1
-    %slli = riscv.slli %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j1>
-    // CHECK-NEXT: slli j1, j1, 1
-    %srli = riscv.srli %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j1>
-    // CHECK-NEXT: srli j1, j1, 1
-    %srai = riscv.srai %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j1>
-    // CHECK-NEXT: srai j1, j1, 1
-    %lui = riscv.lui 1: () -> !riscv.reg<j0>
-    // CHECK-NEXT: lui j0, 1
-    %auipc = riscv.auipc 1: () -> !riscv.reg<j0>
-    // CHECK-NEXT: auipc j0, 1
+    %addi = riscv.addi %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: addi j_1, j_1, 1
+    %slti = riscv.slti %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: slti j_1, j_1, 1
+    %sltiu = riscv.sltiu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: sltiu j_1, j_1, 1
+    %andi = riscv.andi %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: andi j_1, j_1, 1
+    %ori = riscv.ori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: ori j_1, j_1, 1
+    %xori = riscv.xori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: xori j_1, j_1, 1
+    %slli = riscv.slli %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: slli j_1, j_1, 1
+    %srli = riscv.srli %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: srli j_1, j_1, 1
+    %srai = riscv.srai %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: srai j_1, j_1, 1
+    %lui = riscv.lui 1: () -> !riscv.reg<j_0>
+    // CHECK-NEXT: lui j_0, 1
+    %auipc = riscv.auipc 1: () -> !riscv.reg<j_0>
+    // CHECK-NEXT: auipc j_0, 1
 
     // Integer Register-Register Operations
-    %add = riscv.add %2, %1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: add j2, j2, j1
-    %slt = riscv.slt %2, %1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: slt j2, j2, j1
-    %sltu = riscv.sltu %2, %1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: sltu j2, j2, j1
-    %and = riscv.and %2, %1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: and j2, j2, j1
-    %or = riscv.or %2, %1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: or j2, j2, j1
-    %xor = riscv.xor %2, %1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: xor j2, j2, j1
-    %sll = riscv.sll %2, %1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: sll j2, j2, j1
-    %srl = riscv.srl %2, %1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: srl j2, j2, j1
-    %sub = riscv.sub %2, %1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: sub j2, j2, j1
-    %sra = riscv.sra %2, %1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: sra j2, j2, j1
+    %add = riscv.add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: add j_2, j_2, j_1
+    %slt = riscv.slt %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: slt j_2, j_2, j_1
+    %sltu = riscv.sltu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sltu j_2, j_2, j_1
+    %and = riscv.and %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: and j_2, j_2, j_1
+    %or = riscv.or %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: or j_2, j_2, j_1
+    %xor = riscv.xor %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: xor j_2, j_2, j_1
+    %sll = riscv.sll %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sll j_2, j_2, j_1
+    %srl = riscv.srl %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: srl j_2, j_2, j_1
+    %sub = riscv.sub %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sub j_2, j_2, j_1
+    %sra = riscv.sra %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sra j_2, j_2, j_1
     riscv.nop
     // CHECK-NEXT: nop
 
@@ -77,8 +77,8 @@
 
     riscv.jalr %0, 1 : (!riscv.reg<zero>) -> ()
     // CHECK-NEXT: jalr zero, 1
-    riscv.jalr %0 1, !riscv.reg<j0> : (!riscv.reg<zero>) -> ()
-    // CHECK-NEXT: jalr j0, zero, 1
+    riscv.jalr %0 1, !riscv.reg<j_0> : (!riscv.reg<zero>) -> ()
+    // CHECK-NEXT: jalr j_0, zero, 1
     riscv.jalr %0 "label" : (!riscv.reg<zero>) -> ()
     // CHECK-NEXT: jalr zero, label
 
@@ -88,67 +88,67 @@
 
 
     // Conditional Branch Instructions
-    riscv.beq %2, %1, 1: (!riscv.reg<j2>, !riscv.reg<j1>) -> ()
-    // CHECK-NEXT: beq j2, j1, 1
-    riscv.bne %2, %1, 1: (!riscv.reg<j2>, !riscv.reg<j1>) -> ()
-    // CHECK-NEXT: bne j2, j1, 1
-    riscv.blt %2, %1, 1: (!riscv.reg<j2>, !riscv.reg<j1>) -> ()
-    // CHECK-NEXT: blt j2, j1, 1
-    riscv.bge %2, %1, 1: (!riscv.reg<j2>, !riscv.reg<j1>) -> ()
-    // CHECK-NEXT: bge j2, j1, 1
-    riscv.bltu %2, %1, 1: (!riscv.reg<j2>, !riscv.reg<j1>) -> ()
-    // CHECK-NEXT: bltu j2, j1, 1
-    riscv.bgeu %2, %1, 1: (!riscv.reg<j2>, !riscv.reg<j1>) -> ()
-    // CHECK-NEXT: bgeu j2, j1, 1
+    riscv.beq %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: beq j_2, j_1, 1
+    riscv.bne %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bne j_2, j_1, 1
+    riscv.blt %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: blt j_2, j_1, 1
+    riscv.bge %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bge j_2, j_1, 1
+    riscv.bltu %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bltu j_2, j_1, 1
+    riscv.bgeu %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bgeu j_2, j_1, 1
 
     // RV32I/RV64I: Load and Store Instructions (Section 2.6)
-    %lb = riscv.lb %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: lb j2, j1, 1
-    %lbu = riscv.lbu %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: lbu j2, j1, 1
-    %lh = riscv.lh %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: lh j2, j1, 1
-    %lhu = riscv.lhu %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: lhu j2, j1, 1
-    %lw = riscv.lw %1, 1 : (!riscv.reg<j1>) -> !riscv.reg<j2>
-    // CHECK-NEXT: lw j2, 1(j1)
-
-    riscv.sb %2, %1, 1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> ()
-    // CHECK-NEXT: sb j2, j1, 1
-    riscv.sh %2, %1, 1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> ()
-    // CHECK-NEXT: sh j2, j1, 1
-    riscv.sw %2, %1, 1 : (!riscv.reg<j2>, !riscv.reg<j1>) -> ()
-    // CHECK-NEXT: sw j1, 1(j2)
+    %lb = riscv.lb %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lb j_2, j_1, 1
+    %lbu = riscv.lbu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lbu j_2, j_1, 1
+    %lh = riscv.lh %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lh j_2, j_1, 1
+    %lhu = riscv.lhu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lhu j_2, j_1, 1
+    %lw = riscv.lw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lw j_2, 1(j_1)
+
+    riscv.sb %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: sb j_2, j_1, 1
+    riscv.sh %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: sh j_2, j_1, 1
+    riscv.sw %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: sw j_1, 1(j_2)
 
     // RV32I/RV64I: Control and Status Register Instructions (Section 2.8)
-    %csrrw_rw = riscv.csrrw %2, 1024 : (!riscv.reg<j2>) -> !riscv.reg<j1>
-    // CHECK-NEXT: csrrw j1, 1024, j2
-    %csrrw_w = riscv.csrrw %2, 1024, "w" : (!riscv.reg<j2>) -> !riscv.reg<zero>
-    // CHECK-NEXT: csrrw zero, 1024, j2
-    %csrrs_rw = riscv.csrrs %2, 1024 : (!riscv.reg<j2>) -> !riscv.reg<zero>
-    // CHECK-NEXT: csrrs zero, 1024, j2
-    %csrrs_r = riscv.csrrs %0, 1024, "r" : (!riscv.reg<zero>) -> !riscv.reg<j2>
-    // CHECK-NEXT: csrrs j2, 1024, zero
-    %csrrc_rw = riscv.csrrc %2, 1024 : (!riscv.reg<j2>) -> !riscv.reg<j0>
-    // CHECK-NEXT: csrrc j0, 1024, j2
-    %csrrc_r = riscv.csrrc %0, 1024, "r": (!riscv.reg<zero>) -> !riscv.reg<j0>
-    // CHECK-NEXT: csrrc j0, 1024, zero
-    %csrrsi_rw = riscv.csrrsi 1024, 8 : () -> !riscv.reg<j1>
-    // CHECK-NEXT: csrrsi j1, 1024, 8
-    %csrrsi_r = riscv.csrrsi 1024, 0 : () -> !riscv.reg<j0>
-    // CHECK-NEXT: csrrsi j0, 1024, 0
-    %csrrci_rw = riscv.csrrci 1024, 8 : () -> !riscv.reg<j0>
-    // CHECK-NEXT: csrrci j0, 1024, 8
-    %csrrci_r = riscv.csrrci 1024, 0 : () -> !riscv.reg<j1>
-    // CHECK-NEXT: csrrci j1, 1024, 0
-    %csrrwi_rw = riscv.csrrwi 1024, 8 : () -> !riscv.reg<j0>
-    // CHECK-NEXT: csrrwi j0, 1024, 8
+    %csrrw_rw = riscv.csrrw %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: csrrw j_1, 1024, j_2
+    %csrrw_w = riscv.csrrw %2, 1024, "w" : (!riscv.reg<j_2>) -> !riscv.reg<zero>
+    // CHECK-NEXT: csrrw zero, 1024, j_2
+    %csrrs_rw = riscv.csrrs %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<zero>
+    // CHECK-NEXT: csrrs zero, 1024, j_2
+    %csrrs_r = riscv.csrrs %0, 1024, "r" : (!riscv.reg<zero>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: csrrs j_2, 1024, zero
+    %csrrc_rw = riscv.csrrc %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrc j_0, 1024, j_2
+    %csrrc_r = riscv.csrrc %0, 1024, "r": (!riscv.reg<zero>) -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrc j_0, 1024, zero
+    %csrrsi_rw = riscv.csrrsi 1024, 8 : () -> !riscv.reg<j_1>
+    // CHECK-NEXT: csrrsi j_1, 1024, 8
+    %csrrsi_r = riscv.csrrsi 1024, 0 : () -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrsi j_0, 1024, 0
+    %csrrci_rw = riscv.csrrci 1024, 8 : () -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrci j_0, 1024, 8
+    %csrrci_r = riscv.csrrci 1024, 0 : () -> !riscv.reg<j_1>
+    // CHECK-NEXT: csrrci j_1, 1024, 0
+    %csrrwi_rw = riscv.csrrwi 1024, 8 : () -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrwi j_0, 1024, 8
     %csrrwi_w = riscv.csrrwi 1024, 8, "w" : () -> !riscv.reg<zero>
     // CHECK-NEXT: csrrwi zero, 1024, 8
 
     // Assembler pseudo-instructions
-    %li = riscv.li 1: !riscv.reg<j0>
-    // CHECK-NEXT: li j0, 1
+    %li = riscv.li 1: !riscv.reg<j_0>
+    // CHECK-NEXT: li j_0, 1
     // Environment Call and Breakpoints
     riscv.ecall
     // CHECK-NEXT: ecall
@@ -161,135 +161,135 @@
     riscv.directive ".align" "2"
     // CHECK-NEXT: .align 2
     riscv.assembly_section ".text" {
-      %inner = riscv.li 5 : !riscv.reg<j1>
-      %nested_addi = riscv.addi %inner, 1 : (!riscv.reg<j1>) -> !riscv.reg<j1>
+      %inner = riscv.li 5 : !riscv.reg<j_1>
+      %nested_addi = riscv.addi %inner, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
     }
     // CHECK-NEXT:  .text
-    // CHECK-NEXT:  li j1, 5
-    // CHECK-NEXT:  addi j1, j1, 1
+    // CHECK-NEXT:  li j_1, 5
+    // CHECK-NEXT:  addi j_1, j_1, 1
     riscv.label "label0"
     // CHECK-NEXT: label0:
 
 
     // Custom instruction
-    %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg<zero>, !riscv.reg<j1>) -> (!riscv.reg<j3>, !riscv.reg<j4>)
-    // CHECK-NEXT:   hello j3, j4, zero, j1
+    %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg<zero>, !riscv.reg<j_1>) -> (!riscv.reg<j_3>, !riscv.reg<j_4>)
+    // CHECK-NEXT:   hello j_3, j_4, zero, j_1
 
 
     // RISC-V Extensions
 
     riscv_snitch.frep_outer %0 {
-      %add_o = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j1>) -> !riscv.reg<j2>
+      %add_o = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
     }
 
     // CHECK:          frep.o zero, 1, 0, 0
-    // CHECK-NEXT:     add  j2, zero, j1
+    // CHECK-NEXT:     add  j_2, zero, j_1
 
     riscv_snitch.frep_inner %0 {
-      %add_i = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j1>) -> !riscv.reg<j2>
+      %add_i = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
     }
     // CHECK:          frep.i zero, 1, 0, 0
-    // CHECK-NEXT:     add  j2, zero, j1
+    // CHECK-NEXT:     add  j_2, zero, j_1
 
     // RV32F: 8 “F” Standard Extension for Single-Precision Floating-Point, Version 2.0
 
-    %f0 = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<j5>
-    // CHECK-NEXT: fcvt.s.w j5, zero
-    %f1 = riscv.fcvt.s.wu %1 : (!riscv.reg<j1>) -> !riscv.freg<j6>
-    // CHECK-NEXT: fcvt.s.wu j6, j1
-    %f2 = riscv.fcvt.s.wu %1 : (!riscv.reg<j1>) -> !riscv.freg<j7>
-    // CHECK-NEXT: fcvt.s.wu j7, j1
-    %fmadd = riscv.fmadd.s %f0, %f1, %f2 : (!riscv.freg<j5>, !riscv.freg<j6>, !riscv.freg<j7>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmadd.s j8, j5, j6, j7
-    %fmsub = riscv.fmsub.s %f0, %f1, %f2 : (!riscv.freg<j5>, !riscv.freg<j6>, !riscv.freg<j7>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmsub.s j8, j5, j6, j7
-    %fnmsub = riscv.fnmsub.s %f0, %f1, %f2 : (!riscv.freg<j5>, !riscv.freg<j6>, !riscv.freg<j7>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fnmsub.s j8, j5, j6, j7
-    %fnmadd = riscv.fnmadd.s %f0, %f1, %f2 : (!riscv.freg<j5>, !riscv.freg<j6>, !riscv.freg<j7>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fnmadd.s j8, j5, j6, j7
-    %fadd_s = riscv.fadd.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fadd.s j8, j5, j6
-    %fsub_s = riscv.fsub.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fsub.s j8, j5, j6
-    %fmul_s = riscv.fmul.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmul.s j8, j5, j6
-    %fdiv_s = riscv.fdiv.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fdiv.s j8, j5, j6
-    %fsqrt = riscv.fsqrt.s %f0 : (!riscv.freg<j5>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fsqrt.s j8, j5
-    %fsgnj = riscv.fsgnj.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fsgnj.s j8, j5, j6
-    %fsgnjn = riscv.fsgnjn.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fsgnjn.s j8, j5, j6
-    %fsgnjx = riscv.fsgnjx.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fsgnjx.s j8, j5, j6
-    %fmin = riscv.fmin.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmin.s j8, j5, j6
-    %fmax = riscv.fmax.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmax.s j8, j5, j6
-    %fcvtws = riscv.fcvt.w.s %f0 : (!riscv.freg<j5>) -> !riscv.reg<j8>
-    // CHECK-NEXT: fcvt.w.s j8, j5
-    %fcvtwus = riscv.fcvt.wu.s %f0 : (!riscv.freg<j5>) -> !riscv.reg<j8>
-    // CHECK-NEXT: fcvt.wu.s j8, j5
-    %fmvxw = riscv.fmv.x.w %f0 : (!riscv.freg<j5>) -> !riscv.reg<j8>
-    // CHECK-NEXT: fmv.x.w j8, j5
-    %feq = riscv.feq.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.reg<j8>
-    // CHECK-NEXT: feq.s j8, j5, j6
-    %flt = riscv.flt.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.reg<j8>
-    // CHECK-NEXT: flt.s j8, j5, j6
-    %fle = riscv.fle.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.reg<j8>
-    // CHECK-NEXT: fle.s j8, j5, j6
-    %fclass = riscv.fclass.s %f0 : (!riscv.freg<j5>) -> !riscv.reg<j8>
-    // CHECK-NEXT: fclass.s j8, j5
-    %fcvtsw = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fcvt.s.w j8, zero
-    %fcvtswu = riscv.fcvt.s.wu %0 : (!riscv.reg<zero>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fcvt.s.wu j8, zero
-    %fmvwx = riscv.fmv.w.x %0 : (!riscv.reg<zero>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmv.w.x j8, zero
-    %flw = riscv.flw %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<j8>
-    // CHECK-NEXT: flw j8, 1(zero)
-    riscv.fsw %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<j5>) -> ()
-    // CHECK-NEXT: fsw j5, 1(zero)
+    %f0 = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<j_5>
+    // CHECK-NEXT: fcvt.s.w j_5, zero
+    %f1 = riscv.fcvt.s.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<j_6>
+    // CHECK-NEXT: fcvt.s.wu j_6, j_1
+    %f2 = riscv.fcvt.s.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<j_7>
+    // CHECK-NEXT: fcvt.s.wu j_7, j_1
+    %fmadd = riscv.fmadd.s %f0, %f1, %f2 : (!riscv.freg<j_5>, !riscv.freg<j_6>, !riscv.freg<j_7>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmadd.s j_8, j_5, j_6, j_7
+    %fmsub = riscv.fmsub.s %f0, %f1, %f2 : (!riscv.freg<j_5>, !riscv.freg<j_6>, !riscv.freg<j_7>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmsub.s j_8, j_5, j_6, j_7
+    %fnmsub = riscv.fnmsub.s %f0, %f1, %f2 : (!riscv.freg<j_5>, !riscv.freg<j_6>, !riscv.freg<j_7>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fnmsub.s j_8, j_5, j_6, j_7
+    %fnmadd = riscv.fnmadd.s %f0, %f1, %f2 : (!riscv.freg<j_5>, !riscv.freg<j_6>, !riscv.freg<j_7>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fnmadd.s j_8, j_5, j_6, j_7
+    %fadd_s = riscv.fadd.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fadd.s j_8, j_5, j_6
+    %fsub_s = riscv.fsub.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fsub.s j_8, j_5, j_6
+    %fmul_s = riscv.fmul.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmul.s j_8, j_5, j_6
+    %fdiv_s = riscv.fdiv.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fdiv.s j_8, j_5, j_6
+    %fsqrt = riscv.fsqrt.s %f0 : (!riscv.freg<j_5>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fsqrt.s j_8, j_5
+    %fsgnj = riscv.fsgnj.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fsgnj.s j_8, j_5, j_6
+    %fsgnjn = riscv.fsgnjn.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fsgnjn.s j_8, j_5, j_6
+    %fsgnjx = riscv.fsgnjx.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fsgnjx.s j_8, j_5, j_6
+    %fmin = riscv.fmin.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmin.s j_8, j_5, j_6
+    %fmax = riscv.fmax.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmax.s j_8, j_5, j_6
+    %fcvtws = riscv.fcvt.w.s %f0 : (!riscv.freg<j_5>) -> !riscv.reg<j_8>
+    // CHECK-NEXT: fcvt.w.s j_8, j_5
+    %fcvtwus = riscv.fcvt.wu.s %f0 : (!riscv.freg<j_5>) -> !riscv.reg<j_8>
+    // CHECK-NEXT: fcvt.wu.s j_8, j_5
+    %fmvxw = riscv.fmv.x.w %f0 : (!riscv.freg<j_5>) -> !riscv.reg<j_8>
+    // CHECK-NEXT: fmv.x.w j_8, j_5
+    %feq = riscv.feq.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.reg<j_8>
+    // CHECK-NEXT: feq.s j_8, j_5, j_6
+    %flt = riscv.flt.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.reg<j_8>
+    // CHECK-NEXT: flt.s j_8, j_5, j_6
+    %fle = riscv.fle.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.reg<j_8>
+    // CHECK-NEXT: fle.s j_8, j_5, j_6
+    %fclass = riscv.fclass.s %f0 : (!riscv.freg<j_5>) -> !riscv.reg<j_8>
+    // CHECK-NEXT: fclass.s j_8, j_5
+    %fcvtsw = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fcvt.s.w j_8, zero
+    %fcvtswu = riscv.fcvt.s.wu %0 : (!riscv.reg<zero>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fcvt.s.wu j_8, zero
+    %fmvwx = riscv.fmv.w.x %0 : (!riscv.reg<zero>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmv.w.x j_8, zero
+    %flw = riscv.flw %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: flw j_8, 1(zero)
+    riscv.fsw %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<j_5>) -> ()
+    // CHECK-NEXT: fsw j_5, 1(zero)
 
     // RV32F: 9 “D” Standard Extension for Double-Precision Floating-Point, Version 2.0
 
-    %fld = riscv.fld %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fld j8, 1(zero)
-
-    %min_val = riscv.fld %0, "hello" : (!riscv.reg<zero>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fld j8, hello, zero
-
-    riscv.fsd %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<j5>) -> ()
-    // CHECK-NEXT: fsd j5, 1(zero)
-
-    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg<j5>, !riscv.freg<j6>, !riscv.freg<j7>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmadd.d j8, j5, j6, j7
-    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg<j5>, !riscv.freg<j6>, !riscv.freg<j7>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmsub.d j8, j5, j6, j7
-    %fadd_d= riscv.fadd.d %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fadd.d j8, j5, j6
-    %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fsub.d j8, j5, j6
-    %fmul_d = riscv.fmul.d %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmul.d j8, j5, j6
-    %fdiv_d = riscv.fdiv.d %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fdiv.d j8, j5, j6
-    %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmin.d j8, j5, j6
-    %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: fmax.d j8, j5, j6
-
-    %fcvt_d_w = riscv.fcvt.d.w %1 : (!riscv.reg<j1>) -> !riscv.freg<j5>
-    // CHECK-NEXT: fcvt.d.w j5, j1
-    %fcvt_d_wu = riscv.fcvt.d.wu %1 : (!riscv.reg<j1>) -> !riscv.freg<j5>
-    // CHECK-NEXT: fcvt.d.wu j5, j1
+    %fld = riscv.fld %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fld j_8, 1(zero)
+
+    %min_val = riscv.fld %0, "hello" : (!riscv.reg<zero>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fld j_8, hello, zero
+
+    riscv.fsd %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<j_5>) -> ()
+    // CHECK-NEXT: fsd j_5, 1(zero)
+
+    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg<j_5>, !riscv.freg<j_6>, !riscv.freg<j_7>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmadd.d j_8, j_5, j_6, j_7
+    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg<j_5>, !riscv.freg<j_6>, !riscv.freg<j_7>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmsub.d j_8, j_5, j_6, j_7
+    %fadd_d= riscv.fadd.d %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fadd.d j_8, j_5, j_6
+    %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fsub.d j_8, j_5, j_6
+    %fmul_d = riscv.fmul.d %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmul.d j_8, j_5, j_6
+    %fdiv_d = riscv.fdiv.d %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fdiv.d j_8, j_5, j_6
+    %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmin.d j_8, j_5, j_6
+    %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: fmax.d j_8, j_5, j_6
+
+    %fcvt_d_w = riscv.fcvt.d.w %1 : (!riscv.reg<j_1>) -> !riscv.freg<j_5>
+    // CHECK-NEXT: fcvt.d.w j_5, j_1
+    %fcvt_d_wu = riscv.fcvt.d.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<j_5>
+    // CHECK-NEXT: fcvt.d.wu j_5, j_1
 
     // Vector Ops
-    %vfadd_s = riscv.vfadd.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: vfadd.s j8, j5, j6
-    %vfmul_s = riscv.vfmul.s %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
-    // CHECK-NEXT: vfmul.s j8, j5, j6
+    %vfadd_s = riscv.vfadd.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: vfadd.s j_8, j_5, j_6
+    %vfmul_s = riscv.vfmul.s %f0, %f1 : (!riscv.freg<j_5>, !riscv.freg<j_6>) -> !riscv.freg<j_8>
+    // CHECK-NEXT: vfmul.s j_8, j_5, j_6
 
     // Terminate block
     riscv_func.return
diff --git a/tests/filecheck/with-riscemu/riscv_emulation.mlir b/tests/filecheck/with-riscemu/riscv_emulation.mlir
index 1a342d0012..289ee78a1e 100644
--- a/tests/filecheck/with-riscemu/riscv_emulation.mlir
+++ b/tests/filecheck/with-riscemu/riscv_emulation.mlir
@@ -3,10 +3,10 @@
 builtin.module {
   riscv.directive ".globl" "main"
   riscv_func.func @main() {
-    %0 = riscv.li 6 : !riscv.reg<j0>
-    %1 = riscv.li 7 : !riscv.reg<j1>
-    %2 = riscv.mul %0, %1 : (!riscv.reg<j0>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    riscv.custom_assembly_instruction %2 {"instruction_name" = "print"} : (!riscv.reg<j2>) -> ()
+    %0 = riscv.li 6 : !riscv.reg<j_0>
+    %1 = riscv.li 7 : !riscv.reg<j_1>
+    %2 = riscv.mul %0, %1 : (!riscv.reg<j_0>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    riscv.custom_assembly_instruction %2 {"instruction_name" = "print"} : (!riscv.reg<j_2>) -> ()
     %3 = riscv.li 93 : !riscv.reg<a7>
     riscv.ecall
     riscv_func.return
@@ -74,10 +74,10 @@ builtin.module {
 builtin.module {
   riscv.directive ".globl" "main"
   riscv_func.func @main() {
-    %0 = riscv.li 6 : !riscv.reg<j0>
-    %1 = riscv.li 7 : !riscv.reg<j1>
-    %2 = riscv.mul %0, %1 : (!riscv.reg<j0>, !riscv.reg<j1>) -> !riscv.reg<j2>
-    riscv_debug.printf %0, %1, %2 "{} x {} = {}" : (!riscv.reg<j0>, !riscv.reg<j1>, !riscv.reg<j2>) -> ()
+    %0 = riscv.li 6 : !riscv.reg<j_0>
+    %1 = riscv.li 7 : !riscv.reg<j_1>
+    %2 = riscv.mul %0, %1 : (!riscv.reg<j_0>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    riscv_debug.printf %0, %1, %2 "{} x {} = {}" : (!riscv.reg<j_0>, !riscv.reg<j_1>, !riscv.reg<j_2>) -> ()
     %3 = riscv.li 93 : !riscv.reg<a7>
     riscv.ecall
     riscv_func.return
diff --git a/xdsl/backend/riscv/riscv_register_queue.py b/xdsl/backend/riscv/riscv_register_queue.py
index 649e9647c4..a71612510e 100644
--- a/xdsl/backend/riscv/riscv_register_queue.py
+++ b/xdsl/backend/riscv/riscv_register_queue.py
@@ -85,10 +85,10 @@ def pop(
             reg = available_registers.pop()
         else:
             if issubclass(reg_type, IntRegisterType):
-                reg = reg_type(f"j{self._j_idx}")
+                reg = reg_type(f"j_{self._j_idx}")
                 self._j_idx += 1
             else:
-                reg = reg_type(f"fj{self._fj_idx}")
+                reg = reg_type(f"fj_{self._fj_idx}")
                 self._fj_idx += 1
 
         reserved_registers = (